KR20110052205A - 외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법 - Google Patents

외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법 Download PDF

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Publication number
KR20110052205A
KR20110052205A KR1020090109151A KR20090109151A KR20110052205A KR 20110052205 A KR20110052205 A KR 20110052205A KR 1020090109151 A KR1020090109151 A KR 1020090109151A KR 20090109151 A KR20090109151 A KR 20090109151A KR 20110052205 A KR20110052205 A KR 20110052205A
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KR
South Korea
Prior art keywords
data
transmission
clock
loopback
external loopback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020090109151A
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English (en)
Korean (ko)
Inventor
신종신
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020090109151A priority Critical patent/KR20110052205A/ko
Priority to US12/895,999 priority patent/US8559492B2/en
Priority to JP2010244211A priority patent/JP2011109654A/ja
Publication of KR20110052205A publication Critical patent/KR20110052205A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31716—Testing of input or output with loop-back
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31724—Test controller, e.g. BIST state machine
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/14—Monitoring; Testing of transmitters for calibration of the whole transmission and reception path, e.g. self-test loop-back
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Electromagnetism (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
KR1020090109151A 2009-11-12 2009-11-12 외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법 Withdrawn KR20110052205A (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020090109151A KR20110052205A (ko) 2009-11-12 2009-11-12 외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법
US12/895,999 US8559492B2 (en) 2009-11-12 2010-10-01 Transmitter-only IC chip having external loopback test function and external loopback test method using the same
JP2010244211A JP2011109654A (ja) 2009-11-12 2010-10-29 外部ループバックテスト機能を有する伝送専用集積回路チップ及びそれによる外部ループバックテスト方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090109151A KR20110052205A (ko) 2009-11-12 2009-11-12 외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법

Publications (1)

Publication Number Publication Date
KR20110052205A true KR20110052205A (ko) 2011-05-18

Family

ID=43974145

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090109151A Withdrawn KR20110052205A (ko) 2009-11-12 2009-11-12 외부 루프백 테스트 기능을 갖는 전송 전용 집적회로 칩 및 그에 따른 외부 루프백 테스트 방법

Country Status (3)

Country Link
US (1) US8559492B2 (enExample)
JP (1) JP2011109654A (enExample)
KR (1) KR20110052205A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014105131A1 (en) * 2012-12-27 2014-07-03 Intel Corporation Input/output delay testing for devices utilizing on-chip delay generation
US8843794B2 (en) 2012-09-24 2014-09-23 Intel Corporation Method, system and apparatus for evaluation of input/output buffer circuitry
KR20150086844A (ko) * 2014-01-20 2015-07-29 삼성전자주식회사 디스큐 기능을 갖는 고속 데이터 인터페이스 방법 및 그 장치
KR101634066B1 (ko) * 2015-08-07 2016-06-28 주식회사 싸인텔레콤 입체 사이니지 플렉시블 IOT통신모듈을 갖는 인터렉션 플랫폼용 스마트 SoC 테스트장치

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Publication number Priority date Publication date Assignee Title
KR101953117B1 (ko) * 2012-09-05 2019-05-22 삼성전자 주식회사 자가 진단 기능을 갖는 전자 장치 및 전자 장치의 자가 진단 방법
US9954517B2 (en) 2012-11-06 2018-04-24 Micron Technology, Inc. Apparatuses and methods for duty cycle adjustment
US9961174B2 (en) * 2014-01-15 2018-05-01 Qualcomm Incorporated Analog behavior modeling for 3-phase signaling
KR102166908B1 (ko) 2014-02-13 2020-10-19 삼성전자주식회사 고속 데이터 인터페이스 장치 및 상기 장치의 스큐 보정 방법
US9413338B2 (en) 2014-05-22 2016-08-09 Micron Technology, Inc. Apparatuses, methods, and circuits including a duty cycle adjustment circuit
KR20160005536A (ko) * 2014-07-07 2016-01-15 에스케이하이닉스 주식회사 반도체 장치의 데이터 입력 회로
KR102336455B1 (ko) * 2015-01-22 2021-12-08 삼성전자주식회사 집적 회로 및 집적 회로를 포함하는 스토리지 장치
US10437883B2 (en) * 2015-11-24 2019-10-08 Cisco Technology, Inc. Efficient graph database traversal
KR102264159B1 (ko) 2017-06-08 2021-06-11 삼성전자주식회사 외부 루프백 테스트를 수행하는 직렬 통신 인터페이스 회로 및 이를 포함하는 전자 장치
KR102738872B1 (ko) * 2020-12-18 2024-12-06 주식회사 엘엑스세미콘 데이터 구동 회로 및 그의 클럭 복원 방법과 디스플레이 장치
CN116137531A (zh) * 2021-11-16 2023-05-19 深圳市中兴微电子技术有限公司 采样电路、采样电路的使用方法、存储介质、电子装置

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
JPH10170606A (ja) 1996-12-10 1998-06-26 Sony Corp 半導体装置
KR19990010539A (ko) 1997-07-16 1999-02-18 윤종용 반도체 칩 테스트 방법 및 그 회로
US6477674B1 (en) * 1999-12-29 2002-11-05 Intel Corporation Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
JP4854456B2 (ja) * 2006-10-04 2012-01-18 富士通セミコンダクター株式会社 半導体集積回路及び試験方法
US7739567B2 (en) * 2008-02-26 2010-06-15 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Utilizing serializer-deserializer transmit and receive pads for parallel scan test data
US8726112B2 (en) * 2008-07-18 2014-05-13 Mentor Graphics Corporation Scan test application through high-speed serial input/outputs
JP4821824B2 (ja) * 2008-09-19 2011-11-24 ソニー株式会社 画像表示装置、コネクタ表示方法、伝送路状態検出装置、伝送路状態検出方法および半導体集積回路

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8843794B2 (en) 2012-09-24 2014-09-23 Intel Corporation Method, system and apparatus for evaluation of input/output buffer circuitry
KR20150028345A (ko) * 2012-09-24 2015-03-13 인텔 코오퍼레이션 입력/출력 버퍼 회로의 평가를 위한 방법, 시스템, 및 장치
WO2014105131A1 (en) * 2012-12-27 2014-07-03 Intel Corporation Input/output delay testing for devices utilizing on-chip delay generation
US9110134B2 (en) 2012-12-27 2015-08-18 Intel Corporation Input/output delay testing for devices utilizing on-chip delay generation
KR20150086844A (ko) * 2014-01-20 2015-07-29 삼성전자주식회사 디스큐 기능을 갖는 고속 데이터 인터페이스 방법 및 그 장치
KR101634066B1 (ko) * 2015-08-07 2016-06-28 주식회사 싸인텔레콤 입체 사이니지 플렉시블 IOT통신모듈을 갖는 인터렉션 플랫폼용 스마트 SoC 테스트장치

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Publication number Publication date
US20110110412A1 (en) 2011-05-12
JP2011109654A (ja) 2011-06-02
US8559492B2 (en) 2013-10-15

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Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20091112

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid