KR20090072333A - 반도체 소자의 제조 방법 - Google Patents
반도체 소자의 제조 방법 Download PDFInfo
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- KR20090072333A KR20090072333A KR1020070140411A KR20070140411A KR20090072333A KR 20090072333 A KR20090072333 A KR 20090072333A KR 1020070140411 A KR1020070140411 A KR 1020070140411A KR 20070140411 A KR20070140411 A KR 20070140411A KR 20090072333 A KR20090072333 A KR 20090072333A
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- film
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- metal
- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 61
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 52
- 239000010937 tungsten Substances 0.000 claims abstract description 52
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 238000004140 cleaning Methods 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 3
- 238000004380 ashing Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
- 실리콘 기판에 소정의 하부 패턴들을 형성하는 단계;상기 소정의 하부 패턴을 가지는 실리콘 기판 상에 층간 절연막을 형성하는 단계;상기 층간 절연막에 비아홀을 형성하는 단계;상기 비아홀을 매립하는 텅스텐을 증착하는 단계;상기 텅스텐을 평탄화하여 텅스텐 플러그를 형성하는 단계;상기 텅스텐 플러그를 갖는 층간절연막 상에 금속막 패턴을 형성하는 단계;상기 금속막 패턴 상부에 질화막 계열의 보호막을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.
- 제 1항에 있어서,상기 질화막 계열의 보호막 상에 층간절연막을 더 증착하는 단계;상기 질화막 계열의 보호막 상의 층간절연막을 식각하여 기판을 노출시키는 콘택홀을 형성하는 단계;상기 콘택홀에 금속 콘택을 형성하는 단계;상기 금속 콘택 상에 금속 패턴을 더 형성하는 단계를 포함함을 특징으로 하는 반도체 소자의 제조 방법.
- 제 2항에 있어서,상기 질화막 계열의 보호막은 상기 홀 형성시 반사방지막으로 이용하는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 제 1항 내지 제 3항 중 어느 한 항에 있어서,상기 질화막 계열의 보호막은 질화산화막(SiON)으로 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 제 1항에 있어서,상기 금속막 패턴 형성단계는;상기 텅스텐 플러그를 갖는 층간절연막 상에 금속막을 증착하는 단계;상기 금속막 패턴 상에 포토레지스트 패턴을 형성하는 단계;상기 포토레지스트 패턴을 이용한 식각 공정을 진행하는 단계;상기 포토레지스트 패턴을 제거하고 세정 공정을 진행하는 단계를 포함함을 특징으로 하는 반도체 소자의 제조 방법.
- 제 1항에 있어서,상기 층간절연막은 FSG 산화막 또는 PE-TEOS 산화막으로 형성함을 특징으로 하는 반도체 소자의 제조 방법.
- 제 1항에 있어서,상기 금속막 패턴은 Ti 계열의 Ti/TiN막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.
- 제 7항에 있어서,상기 금속막 패턴은 400~500Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020070140411A KR100966385B1 (ko) | 2007-12-28 | 2007-12-28 | 반도체 소자의 제조 방법 |
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KR1020070140411A KR100966385B1 (ko) | 2007-12-28 | 2007-12-28 | 반도체 소자의 제조 방법 |
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KR20090072333A true KR20090072333A (ko) | 2009-07-02 |
KR100966385B1 KR100966385B1 (ko) | 2010-06-28 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9330848B2 (en) | 2012-05-08 | 2016-05-03 | Murata Manufacturing Co., Ltd. | Electronic component, electronic-component-embedded substrate, and method for producing electronic component |
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JP3137087B2 (ja) * | 1998-08-31 | 2001-02-19 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2002118167A (ja) * | 2000-10-06 | 2002-04-19 | Nec Corp | 半導体装置の製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9330848B2 (en) | 2012-05-08 | 2016-05-03 | Murata Manufacturing Co., Ltd. | Electronic component, electronic-component-embedded substrate, and method for producing electronic component |
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