KR20090072333A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20090072333A
KR20090072333A KR1020070140411A KR20070140411A KR20090072333A KR 20090072333 A KR20090072333 A KR 20090072333A KR 1020070140411 A KR1020070140411 A KR 1020070140411A KR 20070140411 A KR20070140411 A KR 20070140411A KR 20090072333 A KR20090072333 A KR 20090072333A
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film
pattern
forming
metal
interlayer insulating
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KR1020070140411A
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KR100966385B1 (en
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김종일
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A manufacturing method of a semiconductor device is provided to prevent loss of a tungsten plug by preventing permeation of a cleaning solution inside the tungsten plug by a protecting film during a cleaning process. Predetermined bottom patterns are formed on a silicon substrate(30). An interlayer insulation film(32) is formed on the silicon substrate having the bottom patterns. A via hole is formed on the interlayer insulation film. A tungsten is deposited, and is filled in the via hole. A tungsten plug(38) is formed by flattening the tungsten. A metal film pattern(40) is formed on the interlayer insulation film having the tungsten plug. A protecting film(42) of a nitride film base is formed on a top part of the metal film pattern.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 더욱 상세하게는 텅스텐 플러그 상의 금속 배선 패터닝 후 세정 공정에 의해 텅스텐 플러그가 손실되는 것을 방지하도록 하는 반도체 소자의 제조 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing the loss of a tungsten plug by a cleaning process after patterning a metal wire on the tungsten plug.

일반적으로 금속 배선은 RIE(Reaction Ion Etching)공정, 즉 금속막 상에 마스크 패턴을 형성하고, RIE 공정으로 금속막을 직접 식각하는 방법으로 형성되었다. 그런데, RIE 공정은 금속 배선의 임계 치수(Critical Demension)가 감소되고 있는 추세에서, 그 전기적 특성의 확보가 어려운 문제가 있은바, 새로운 방식의 금속 배선 공정이 필요하게 되었다.In general, the metal wiring is formed by a reaction ion etching (RIE) process, that is, a mask pattern is formed on the metal film, and the metal film is directly etched by the RIE process. However, the RIE process has a problem that it is difficult to secure the electrical characteristics in the trend that the critical dimension of the metal wiring is reduced, so a new metal wiring process is required.

그 하나의 방법으로서, 다마신(Damascene) 공정에 제안되었고, 다마신 공정은 RIE 공정에 의한 금속 배선 형성 방법보다 상대적으로 우수한 전기적 특성을 얻을 수 있기 때문에 반도체 소자의 고집적화 추세에서, 그 이용이 확대되리라 예상된다.As one method, it has been proposed for the damascene process, and since the damascene process can obtain relatively superior electrical characteristics than the metal wiring formation method by the RIE process, its use has been expanded in the trend of high integration of semiconductor devices. It is expected to be.

다마신 공정을 이용한 금속 배선 형성 방법을 도 1의 단면도를 참조하면, 먼저 소자의 하부 패턴들이 형성된 실리콘 기판(10) 상에 제 1 층간절연막(12)을 형성하고, 제 1 층간절연막(12)의 소정 영역을 선택적으로 제거하여 금속 배선용 비아홀을 형성한다.Referring to the cross-sectional view of FIG. 1 for a method of forming a metal wiring using a damascene process, first, a first interlayer insulating film 12 is formed on a silicon substrate 10 on which lower patterns of devices are formed, and then the first interlayer insulating film 12 is formed. The predetermined region of the metal is selectively removed to form a via hole for metal wiring.

이어서, 비아홀 내에 소정의 금속막을 매립하여 금속 플러그 즉 텅스텐 플러그(14)를 형성한다. Subsequently, a predetermined metal film is embedded in the via hole to form a metal plug, that is, a tungsten plug 14.

그리고, 텅스텐 플러그(14)가 형성된 제 1 층간절연막(12) 상에 금속막을 증착한 후 포토레지스트 패턴(미도시함)을 식각 마스크로 사용한 식각을 실시하여, 금속막을 상기 텅스텐 플러그(14)와 연결되는 금속막 패턴(16)으로 형성함으로서 금속 배선을 얻는다. After depositing a metal film on the first interlayer insulating film 12 on which the tungsten plug 14 is formed, etching is performed using a photoresist pattern (not shown) as an etching mask, and the metal film is formed on the tungsten plug 14. The metal wiring is obtained by forming the metal film pattern 16 to be connected.

그런다음, 금속막 패턴을 형성한 후, CF4 가스 또는 산소 가스를 사용한 플라즈마 처리를 실시하여 상기 포토레지스트 패턴을 제거한, 표면에 잔류하는 이물질을 제거하기 위한 세정 공정을 진행한다.Then, after the metal film pattern is formed, a plasma treatment using CF 4 gas or oxygen gas is performed to remove the photoresist pattern, and a cleaning process for removing foreign matter remaining on the surface is performed.

이후, 제 2 층간 절연막(18) 증착과 금속 콘택(20) 형성 및 금속 배선(22) 공정을 진행한다.Thereafter, deposition of the second interlayer insulating layer 18, formation of the metal contact 20, and metal wiring 22 are performed.

여기서, 콘택 또는 비아홀 매립시 도 2에 도시된 바와 같이 텅스텐 플러그(14)에 심(seam; 24) 현상이 발생할 수 있으며, 이는 텅스텐 플러그(14) 상부에 형성하는 금속막 패턴(16)의 스텝 커버리지 특성을 저하시켜, 심(seam)을 노출시키는 홀(26)이 발생하게 된다.Here, as shown in FIG. 2, when the contact or via hole is filled, a seam phenomenon may occur on the tungsten plug 14, which is a step of the metal layer pattern 16 formed on the tungsten plug 14. The coverage 26 is lowered and holes 26 exposing seams are generated.

이에 따라, 금속막 패터닝 시의 포토레지스트 패턴 불량이 발생한 경우 포토레지스트 패턴 형성 재작업(rework) 작업을 진행하기 위하여, 포토레지스트 패턴 제거와 세정 공정을 진행한다.Accordingly, in the case where the photoresist pattern defect occurs during the metal film patterning, the photoresist pattern removal and cleaning process are performed to proceed with the rework of the photoresist pattern formation.

이때, 세정 용액이 금속막의 홀(26)을 통해 텅스텐 플러그의 심(seam;24) 부분에 침투하게 되고, 이에 따라 고온에서 산화되는 성질이 있는 텅스텐 플러그가 부식되며, 후속의 고온에 의해 부식된 텅스텐이 녹아 버리는 문제점이 있다.At this time, the cleaning solution penetrates into the seam portion 24 of the tungsten plug through the hole 26 of the metal film, and thus, the tungsten plug having the property of being oxidized at high temperature is corroded and subsequently corroded by high temperature. There is a problem that tungsten melts.

한편, 국내특허출원 2002-132286호에 텅스텐 플러그의 소실 현상을 방지하는 기술이 개시된 바 있다.On the other hand, Korean Patent Application No. 2002-132286 discloses a technique for preventing the disappearance of the tungsten plug.

이 기술은 텅스텐 플러그 상부의 금속막 패턴 식각시 O3 에싱(ashing) 공정 및 세정 공정을 진행하여 텅스텐 플러그 부식을 방지하는 기술이다.This technology prevents tungsten plug corrosion by performing O 3 ashing process and cleaning process when etching the metal film pattern on the top of tungsten plug.

즉, CF4 가스 또는 산소 가스를 사용한 플라즈마 처리를 통해 포토레지스트 패턴을 제거하는 기술에서, CF4 가스 또는 산소 가스의 이온이 전자 성분보다 매우 많아, 포토레지스트 패턴의 제거로 인하여 상기 금속막 패턴에는 이온의 차지(charge)에 의해, 이온 차지의 하이 포텐셜을 유발하고, 특히 후속의 pH값으로 인해 텅스텐 플러그를 부식시키도 한다.That is, CF 4 in the gas or the technique for removing the photoresist pattern by a plasma treatment using oxygen gas, CF 4 gas or ion of the oxygen gas is very larger than the electronic components, a photoresist due to the removal of the pattern of the metal film pattern, The charge of the ions leads to a high potential of the ion charge and, in particular, to corrode the tungsten plug due to the subsequent pH value.

이를 방지하기 위하여, 이온 차징(charging) 소스가 없는 O3 에싱(ashing) 공정을 진행하여 플러그의 손실을 방지하는 기술이 제안된바 있으나, 이 기술은 텅스텐 플러그 내에 심(seam)이 발생하는 경우에는 텅스텐 플러그의 손실을 효과적으로 방지할 수 없는 문제가 있다.In order to prevent this, a technique of preventing plug loss by performing an O 3 ashing process without an ion charging source has been proposed, but this technique has been proposed in the case of a seam in the tungsten plug. There is a problem that can not effectively prevent the loss of the tungsten plug.

본 발명은 텅스텐 플러그 상부에 형성되는 금속 배선 정의를 위한 포토레지스트 패턴 공정과 같은 세정 공정시 세정 용액에 의해 텅스텐 플러그가 손실되는 문제점을 해소할 수 있는 반도체 소자의 제조 방법을 제공하기 위한 것이다. The present invention is to provide a method for manufacturing a semiconductor device that can solve the problem that the tungsten plug is lost by the cleaning solution during the cleaning process, such as a photoresist pattern process for defining the metal wiring formed on the tungsten plug.

상기 과제를 해결하기 위한 본 발명의 반도체 소자 제조 방법은, 실리콘 기판에 소정의 하부 패턴들을 형성하는 단계와, 상기 소정의 하부 패턴을 가지는 실리콘 기판 상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막에 비아홀을 형성하는 단계와, 상기 비아홀을 매립하는 텅스텐을 증착하는 단계와, 상기 텅스텐을 평탄화하여 텅스텐 플러그를 형성하는 단계와, 상기 텅스텐 플러그를 갖는 층간절연막 상에 금속막 패턴을 형성하는 단계와, 상기 금속막 패턴 상부에 질화막을 형성하는 단계를 포함한다.The semiconductor device manufacturing method of the present invention for solving the above problems comprises the steps of forming a predetermined lower pattern on the silicon substrate, forming an interlayer insulating film on the silicon substrate having the predetermined lower pattern, and the interlayer insulating film Forming via holes in the via holes; depositing tungsten to fill the via holes; planarizing the tungsten to form tungsten plugs; forming a metal film pattern on the interlayer insulating film having the tungsten plugs; And forming a nitride film on the metal film pattern.

본 발명은 상기 질화막 상에 층간절연막을 더 증착하는 단계와, 상기 질화막 상의 층간절연막을 식각하여 기판을 노출시키는 콘택홀을 형성하는 단계와, 상기 홀에 금속 콘택을 형성하는 단계와, 상기 금속 콘택 상에 금속 패턴을 더 형성하는 단계를 포함하며, 상기 질화막은 상기 콘택홀 형성시 반사방지막으로 이용할 수 있다. According to an embodiment of the present invention, the method may further include depositing an interlayer dielectric layer on the nitride layer, forming a contact hole to expose a substrate by etching the interlayer dielectric layer on the nitride layer, and forming a metal contact in the hole; The method may further include forming a metal pattern on the nitride layer, and the nitride layer may be used as an anti-reflection layer when forming the contact hole.

또한, 상기 금속막 패턴 형성 단계는 상기 텅스텐 플러그를 갖는 층간절연막 상에 금속막을 증착하는 단계와, 상기 금속막 패턴 상에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 이용한 식각 공정을 진행하는 단계와, 상기 포토레지스트 패턴을 제거하고 세정 공정을 진행하는 단계를 포함함한다.In addition, the forming of the metal film pattern may include depositing a metal film on the interlayer insulating film having the tungsten plug, forming a photoresist pattern on the metal film pattern, and performing an etching process using the photoresist pattern. And removing the photoresist pattern and performing a cleaning process.

그리고, 상기 포토레지스트 패턴 제거 공정은 O3 에싱 공정으로 진행할 수 있다.In addition, the photoresist pattern removing process may proceed to an O 3 ashing process.

본 발명은 포토레지스트 패턴 제거 및 세정 공정시에 텅스텐 플러그 내로 세정액이 침투되지 않도록 함으로써 텅스텐 플러그의 손실이 방지될 수 있도록 하여, 소자의 특성 개선 및 수율 향상을 도모할 수 있는 이점이 있다.The present invention has the advantage that the loss of the tungsten plug can be prevented by preventing the cleaning solution from penetrating into the tungsten plug during the photoresist pattern removal and cleaning process, thereby improving the characteristics of the device and improving the yield.

도 3a 내지 제 3e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다. 3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a를 참조하면, 트랜지스터와 같은 소정의 하부 패턴이 형성된 실리콘 기판(30)에 층간절연막(32)을 형성한다. Referring to FIG. 3A, an interlayer insulating film 32 is formed on a silicon substrate 30 on which a predetermined lower pattern such as a transistor is formed.

여기서, 층간절연막(32)은 FSG 산화막 또는 PE-TEOS 산화막으로 형성할 수 있다. The interlayer insulating film 32 may be formed of an FSG oxide film or a PE-TEOS oxide film.

도 3b를 참조하면, 층간 절연막(32) 상에 비아홀 영역을 정의하는 포토레지 스트 패턴(34)을 형성한 후 이를 식각 마스크로 이용한 식각 공정을 진행하여 비아홀(36)을 형성한다.Referring to FIG. 3B, after forming the photoresist pattern 34 defining the via hole region on the interlayer insulating layer 32, an etching process using the photoresist pattern 34 as an etching mask is performed to form the via hole 36.

여기서, 비아홀(36) 형성을 위한 식각 공정은 CxFy/O2/Ar 또는 CpHqFr/O2/Ar을 소스 가스로 사용하며, N2 가스를 첨가하는 방식으로 실시할 수 있다. Here, the etching process for forming the via hole 36 uses CxFy / O 2 / Ar or CpHqFr / O 2 / Ar as a source gas, and N 2 This can be done by adding a gas.

도 3c를 참조하면, 비아홀(36)을 매립하도록 화학기상 증착법(CVD)과 같은 방식으로 텅스텐을 증착한다.Referring to FIG. 3C, tungsten is deposited in the same manner as chemical vapor deposition (CVD) to fill the via hole 36.

그리고, 텅스텐에 대하여 에치-백(etch-back) 공정이나, 화학기계적 연마 공정과 같은 평탄화 공정을 진행하여 비아홀(36; 도 3b 참조) 이외 영역의 텅스텐을 제거하여 텅스텐 플러그(38)를 형성한다. Then, tungsten plugs 38 are formed by removing tungsten from regions other than the via holes 36 (see FIG. 3B) by performing a planarization process such as an etch-back process or a chemical mechanical polishing process. .

이와 같이, 텅스텐 플러그(38)를 비아홀(36; 도 3b 참조)에 매립할 경우 스텝 커버리지 불량으로 인하여 비아홀(36; 도 3b 참조)에 심(seam; S)이 발생할 수 있다.As such, when the tungsten plug 38 is embedded in the via hole 36 (see FIG. 3B), a seam S may occur in the via hole 36 (see FIG. 3B) due to poor step coverage.

이때, 도 3c에는 비아홀(36; 도 3b 참조)에 텅스텐을 바로 매립하였으나, 비아홀(36; 도 3b 참조)의 층간절연막(32) 표면을 따라 Ti 또는 TiN/Ti와 같은 장벽 금속층을 더 형성할 수 있다.In FIG. 3C, tungsten is directly buried in the via hole 36 (see FIG. 3B), but a barrier metal layer such as Ti or TiN / Ti may be further formed along the surface of the interlayer insulating layer 32 of the via hole 36 (see FIG. 3B). Can be.

도 3d를 참조하면, 텅스텐 플러그(38)가 형성된 결과물 상에 금속막(40)을 증착하고, 금속막 패턴 영역을 정의하는 포토레지스트 패턴(44)을 형성한다. Referring to FIG. 3D, a metal film 40 is deposited on the resultant product on which the tungsten plug 38 is formed, and a photoresist pattern 44 defining a metal film pattern region is formed.

이때, 금속막(40)은 Ti 계열의 Ti/TiN막을 400~500Å 두께로 형성하되, 바람직하게는 500Å 두께로 형성한다. At this time, the metal film 40 is formed of a Ti-based Ti / TiN film of 400 ~ 500Å thickness, preferably 500Å thickness.

여기서, 금속막 패터닝 시의 포토레지스트 패턴 불량이 발생한 경우 포토레지스트 패턴 형성 재작업(rework) 작업을 진행하기 위하여, 포토레지스트 패턴 제거와 세정 공정을 진행할 수 있다. In this case, when a photoresist pattern defect occurs during metal film patterning, a photoresist pattern removal and cleaning process may be performed to rework the photoresist pattern formation.

이 경우, 세정 용액이 금속막(40)의 홀(H)을 통해 텅스텐 플러그의 심(seam; S) 부분에 침투하게 되고, 이에 따라 고온에서 산화되는 성질이 있는 텅스텐 플러그가 부식되며, 후속의 고온에 의해 부식된 텅스텐이 녹아 버리는 문제점이 있다.In this case, the cleaning solution penetrates into the seam portion of the tungsten plug through the hole H of the metal film 40, thereby corroding the tungsten plug having the property of being oxidized at high temperature, and subsequently There is a problem in that tungsten corroded by high temperature melts.

이를 방지하기 위한 본 발명은 금속막 패턴 이전의 금속막 상부에 질화막(42)을 증착하여, 세정용액 침투를 원천 방지하도록 하는 것이다.The present invention for preventing this is to deposit the nitride film 42 on the upper metal film before the metal film pattern, so as to prevent the penetration of the cleaning solution.

여기서, 질화막(42)은 후속 공정시의 반사방지막 역할을 할 수 있다. Here, the nitride film 42 may serve as an antireflection film in a subsequent process.

이어서, 포토레지스트 패턴(44)을 이용한 식각 공정을 통해 질화막(42)과 금속막(40)을 식각하여 텅스텐 플러그(38)에 연결되는 금속막 패턴(42')을 형성한다. Subsequently, the nitride film 42 and the metal film 40 are etched through an etching process using the photoresist pattern 44 to form a metal film pattern 42 ′ connected to the tungsten plug 38.

이때, 식각 공정은 Cl2/BCl3 혼합 기체를 활성화시킨 플라즈마를 이용한 건식 식각 방식을 이용할 수 있다.In this case, the etching process may use a dry etching method using plasma in which the Cl 2 / BCl 3 mixed gas is activated.

도 3e를 참조하면, O3 에싱 공정을 이용하여 포토레지스트 패턴(44)을 제거하고, 세정 공정을 진행 한 후에 질화막(42) 상에 층간절연막(46)을 증착하고, 층간 절연막(46)을 식각하여 실리콘 기판(30)을 노출시키는 콘택홀(미도시함)을 형성한다. Referring to FIG. 3E, the photoresist pattern 44 is removed using an O 3 ashing process, an interlayer insulating film 46 is deposited on the nitride film 42 after the cleaning process, and the interlayer insulating film 46 is formed. Etching is performed to form contact holes (not shown) exposing the silicon substrate 30.

여기서, 상기 콘택홀(미도시함) 형성은 질화막(42)을 반사방지막으로 이용하여 실시할 수 있다. The contact hole (not shown) may be formed by using the nitride film 42 as an anti-reflection film.

그리고, 상기 콘택홀(미도시함)을 금속물질로 매립한 후 평탄화 공정을 진행하여 금속 콘택(48)을 형성한 후 금속 콘택(48) 상에 금속 물질 증착과 사진 및 식각 공정을 진행하여 금속막 패턴(50)을 형성한다. After filling the contact hole (not shown) with a metal material, the planarization process is performed to form a metal contact 48, and then a metal material is deposited on the metal contact 48, and a photo and etching process is performed. The film pattern 50 is formed.

도 4는 도 3d의 포토레지스트 패턴을 O3 에싱 공정으로 제거한 후의 SEM 사진으로서, 콘택홀(미도시함) 내의 텅스텐 플러그의 일부가 소실된 것을 볼 수 있다.FIG. 4 is a SEM photograph after the photoresist pattern of FIG. 3D is removed by an O 3 ashing process, and a portion of the tungsten plug in the contact hole (not shown) is lost.

여기서, 본 발명의 텅스텐 플러그가 일부 손실된 것을 나타내지만, 본 발명은 O3 에싱 및 세정 공정을 진행하기 때문에 이온의 차징(charging) 소스가 없어 후속의 세정 공정시 텅스텐 플러그의 부식에 의한 손실이 방지되나, 종래 기술은 포토레지스트 패턴을 플라즈마 에싱(ashing) 공정으로 제거하기 때문에 이온의 차징(charging)에 의해 후속 고온의 세정 텅스텐 플러그가 부식되는 문제가 있다. Here, although the tungsten plug of the present invention is shown to be partially lost, the present invention does not have a charging source of ions since the O 3 ashing and cleaning process is performed, so that the loss due to corrosion of the tungsten plug in the subsequent cleaning process is eliminated. Although prevented, the prior art has a problem that the subsequent high temperature cleaning tungsten plugs are corroded by charging of ions because the photoresist pattern is removed by a plasma ashing process.

또한, 본 발명의 금속막 패턴은 두께가 얇아서 식각 공정이 짧아 식각 공정에 의한 차징(charge)은 크게 발생하지 않아 식각 공정에 의한 텅스텐 플러그의 손실이 방지된다. In addition, since the metal film pattern of the present invention has a small thickness, the etching process is short, so that charging by the etching process does not occur significantly, thereby preventing the loss of the tungsten plug due to the etching process.

이상에서 설명한 본 발명의 바람직한 실시예는 예시의 목적을 위해 개시된 것이며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러가지 치환, 변형 및 변경이 가능할 것이나, 이러한 치환, 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope of the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

도 1은 종래 기술에 따른 금속 배선 공정을 진행한 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device undergoing a metal wiring process according to the prior art.

도 2은 도 1 반도체 소자의 결함 상태를 보인 단면도.FIG. 2 is a cross-sectional view illustrating a defect state of the semiconductor device of FIG. 1. FIG.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 4는 도 3d의 포토레지스트 패턴을 O3 에싱 공정으로 제거한 후의 SEM 사진.FIG. 4 is a SEM photograph after removing the photoresist pattern of FIG. 3D by an O 3 ashing process. FIG.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

30 : 실리콘 기판 32 : 층간절연막30 silicon substrate 32 interlayer insulating film

34 : 포토레지스트 패턴 36 : 비아홀34: photoresist pattern 36: via hole

38 : 텅스텐 플러그 40 : 금속막38: tungsten plug 40: metal film

42 : 질화막 48 : 금속 콘택42 nitride film 48 metal contact

50 : 금속막 패턴50: metal film pattern

Claims (8)

실리콘 기판에 소정의 하부 패턴들을 형성하는 단계;Forming predetermined lower patterns on the silicon substrate; 상기 소정의 하부 패턴을 가지는 실리콘 기판 상에 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on the silicon substrate having the predetermined lower pattern; 상기 층간 절연막에 비아홀을 형성하는 단계;Forming via holes in the interlayer insulating film; 상기 비아홀을 매립하는 텅스텐을 증착하는 단계;Depositing tungsten to fill the via hole; 상기 텅스텐을 평탄화하여 텅스텐 플러그를 형성하는 단계;Planarizing the tungsten to form a tungsten plug; 상기 텅스텐 플러그를 갖는 층간절연막 상에 금속막 패턴을 형성하는 단계;Forming a metal film pattern on the interlayer insulating film having the tungsten plug; 상기 금속막 패턴 상부에 질화막 계열의 보호막을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.And forming a nitride film-based protective film on the metal film pattern. 제 1항에 있어서,The method of claim 1, 상기 질화막 계열의 보호막 상에 층간절연막을 더 증착하는 단계;Depositing an interlayer insulating film on the nitride film-based protective film; 상기 질화막 계열의 보호막 상의 층간절연막을 식각하여 기판을 노출시키는 콘택홀을 형성하는 단계;Forming a contact hole exposing the substrate by etching the interlayer insulating layer on the nitride film-based protective film; 상기 콘택홀에 금속 콘택을 형성하는 단계;Forming a metal contact in the contact hole; 상기 금속 콘택 상에 금속 패턴을 더 형성하는 단계를 포함함을 특징으로 하는 반도체 소자의 제조 방법. And forming a metal pattern on the metal contact. 제 2항에 있어서,The method of claim 2, 상기 질화막 계열의 보호막은 상기 홀 형성시 반사방지막으로 이용하는 것을 특징으로 하는 반도체 소자의 제조 방법.The nitride film-based protective film is a semiconductor device manufacturing method, characterized in that used as an anti-reflection film when forming the hole. 제 1항 내지 제 3항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 질화막 계열의 보호막은 질화산화막(SiON)으로 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.The nitride film-based protective film is a semiconductor device manufacturing method, characterized in that consisting of a nitride oxide (SiON). 제 1항에 있어서,The method of claim 1, 상기 금속막 패턴 형성단계는;The metal film pattern forming step; 상기 텅스텐 플러그를 갖는 층간절연막 상에 금속막을 증착하는 단계;Depositing a metal film on the interlayer insulating film having the tungsten plug; 상기 금속막 패턴 상에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the metal film pattern; 상기 포토레지스트 패턴을 이용한 식각 공정을 진행하는 단계;Performing an etching process using the photoresist pattern; 상기 포토레지스트 패턴을 제거하고 세정 공정을 진행하는 단계를 포함함을 특징으로 하는 반도체 소자의 제조 방법. Removing the photoresist pattern and performing a cleaning process. 제 1항에 있어서,The method of claim 1, 상기 층간절연막은 FSG 산화막 또는 PE-TEOS 산화막으로 형성함을 특징으로 하는 반도체 소자의 제조 방법.The interlayer insulating film is a semiconductor device manufacturing method, characterized in that formed of FSG oxide film or PE-TEOS oxide film. 제 1항에 있어서,The method of claim 1, 상기 금속막 패턴은 Ti 계열의 Ti/TiN막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The metal film pattern is a manufacturing method of a semiconductor device, characterized in that formed of Ti-based Ti / TiN film. 제 7항에 있어서, The method of claim 7, wherein 상기 금속막 패턴은 400~500Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The metal film pattern is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 400 ~ 500Å.
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US9330848B2 (en) 2012-05-08 2016-05-03 Murata Manufacturing Co., Ltd. Electronic component, electronic-component-embedded substrate, and method for producing electronic component

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JP2002118167A (en) * 2000-10-06 2002-04-19 Nec Corp Method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9330848B2 (en) 2012-05-08 2016-05-03 Murata Manufacturing Co., Ltd. Electronic component, electronic-component-embedded substrate, and method for producing electronic component

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