KR20090071482A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

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Publication number
KR20090071482A
KR20090071482A KR1020080134561A KR20080134561A KR20090071482A KR 20090071482 A KR20090071482 A KR 20090071482A KR 1020080134561 A KR1020080134561 A KR 1020080134561A KR 20080134561 A KR20080134561 A KR 20080134561A KR 20090071482 A KR20090071482 A KR 20090071482A
Authority
KR
South Korea
Prior art keywords
layer
semiconductor device
insulating layer
semiconductor
antenna
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020080134561A
Other languages
English (en)
Korean (ko)
Inventor
도모하루 후지이
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20090071482A publication Critical patent/KR20090071482A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020080134561A 2007-12-27 2008-12-26 반도체 장치 및 그 제조 방법 Withdrawn KR20090071482A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2007-335690 2007-12-27
JP2007335690A JP5592053B2 (ja) 2007-12-27 2007-12-27 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
KR20090071482A true KR20090071482A (ko) 2009-07-01

Family

ID=40797122

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080134561A Withdrawn KR20090071482A (ko) 2007-12-27 2008-12-26 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (1) US8035192B2 (https=)
JP (1) JP5592053B2 (https=)
KR (1) KR20090071482A (https=)
TW (1) TW200931623A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10340234B2 (en) 2017-03-28 2019-07-02 Samsung Electro-Mechanics Co., Ltd. Substrate having embedded electronic component

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101195786B1 (ko) * 2008-05-09 2012-11-05 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 칩 사이즈 양면 접속 패키지의 제조 방법
US8896136B2 (en) * 2010-06-30 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark and method of formation
US20120306094A1 (en) * 2011-06-06 2012-12-06 Shahrazie Zainal Abu Bakar Signal routing using through-substrate vias
EP2648218B1 (en) * 2012-04-05 2015-10-14 Nxp B.V. Integrated circuit and method of manufacturing the same
US9166284B2 (en) * 2012-12-20 2015-10-20 Intel Corporation Package structures including discrete antennas assembled on a device
TWI544593B (zh) * 2013-09-09 2016-08-01 矽品精密工業股份有限公司 半導體裝置及其製法
JP6869649B2 (ja) 2016-06-13 2021-05-12 ラピスセミコンダクタ株式会社 半導体装置、通信システムおよび半導体装置の製造方法。
JP6483927B2 (ja) * 2016-10-21 2019-03-13 京セラ株式会社 タグ用基板、ｒｆｉｄタグおよびｒｆｉｄシステム
US10181447B2 (en) 2017-04-21 2019-01-15 Invensas Corporation 3D-interconnect
TWI660506B (zh) * 2017-08-15 2019-05-21 Delta Electronics, Inc. 半導體裝置
KR102019354B1 (ko) * 2017-11-03 2019-09-09 삼성전자주식회사 안테나 모듈
KR102684976B1 (ko) 2019-02-15 2024-07-16 삼성전자주식회사 반도체 패키지
US12040284B2 (en) 2021-11-12 2024-07-16 Invensas Llc 3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna
WO2023194882A1 (en) * 2022-04-04 2023-10-12 Mahdi Davarpanah Measuring dissipation factor of voltage divider of capacitor voltage transformers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4010881B2 (ja) 2002-06-13 2007-11-21 新光電気工業株式会社 半導体モジュール構造
JP4290158B2 (ja) * 2004-12-20 2009-07-01 三洋電機株式会社 半導体装置
JP2007049115A (ja) * 2005-07-13 2007-02-22 Seiko Epson Corp 半導体装置
JP2007036571A (ja) * 2005-07-26 2007-02-08 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US7531407B2 (en) * 2006-07-18 2009-05-12 International Business Machines Corporation Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10340234B2 (en) 2017-03-28 2019-07-02 Samsung Electro-Mechanics Co., Ltd. Substrate having embedded electronic component
US11444043B2 (en) 2017-03-28 2022-09-13 Samsung Electro-Mechanics Co., Ltd. Substrate having embedded electronic component

Also Published As

Publication number Publication date
JP5592053B2 (ja) 2014-09-17
US20090166811A1 (en) 2009-07-02
US8035192B2 (en) 2011-10-11
TW200931623A (en) 2009-07-16
JP2009158743A (ja) 2009-07-16

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PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000