KR20090041466A - 모듈 패키지 및 그 제조 방법 - Google Patents
모듈 패키지 및 그 제조 방법 Download PDFInfo
- Publication number
- KR20090041466A KR20090041466A KR1020070106969A KR20070106969A KR20090041466A KR 20090041466 A KR20090041466 A KR 20090041466A KR 1020070106969 A KR1020070106969 A KR 1020070106969A KR 20070106969 A KR20070106969 A KR 20070106969A KR 20090041466 A KR20090041466 A KR 20090041466A
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- bare die
- substrate portion
- module package
- opening
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (7)
- 적어도 하나의 층으로 이루어진 제 1 기판부;상기 제 1 기판부 상에 적어도 하나의 층으로 형성되며, 개구부를 갖는 제 2 기판부;상기 제 2 기판부 상에 형성되며, 상기 개구부를 덮는 제 3 기판부; 및상기 제2기판부 내부에 베어 다이를 포함하는 모듈 패키지.
- 제 1항에 있어서,상기 제 1 기판부는 상기 베어다이가 실장되는 다이랜드와 타 기판부 또는 상기 제 1 기판부의 상부와 하부를 전기적 연결하는 비아패턴을 포함하고, 상기 베어다이는 와이어 본딩되는 모듈 패키지.
- 제 1항에 있어서,상기 개구부에 경화 부재가 형성되는 것을 특징으로 모듈 패키지.
- 제 1항에 있어서,상기 제 3 기판부는 제 2 기판부 또는 상기 제 3 기판부의 상부와 하부를 전기적 연결을 위한 비아 패턴과 상기 비아 패턴과 전기적으로 연결되는 랜드를 포함하는 모듈 패키지.
- 제 1항에 있어서,상기 제 1 기판부 상에 상기 베어 다이의 입출력단자와 전기적으로 연결되는 본딩 랜드가 형성된 것을 포함하는 모듈 패키지.
- 비아 패턴을 갖는 제 1 기판부를 준비하는 단계;상기 제 1 기판부 상에 베어 다이를 실장하는 단계;상기 제 1 기판부 상에 상기 베어 다이와 대응하여 개구부를 갖는 제 2 기판부를 형성하는 단계; 및상기 제 2 기판부 상에 제 3 기판부를 형성하는 단계를 포함하는 모듈 패키지의 제조 방법.
- 제 6항에 있어서,상기 제 1 내지 제 3 기판부를 관통하는 쓰루홀 패턴을 포함하는 것을 특징으로 하는 모듈 패키지의 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070106969A KR100952029B1 (ko) | 2007-10-24 | 2007-10-24 | 모듈 패키지 및 그 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070106969A KR100952029B1 (ko) | 2007-10-24 | 2007-10-24 | 모듈 패키지 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
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KR20090041466A true KR20090041466A (ko) | 2009-04-29 |
KR100952029B1 KR100952029B1 (ko) | 2010-04-08 |
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Application Number | Title | Priority Date | Filing Date |
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KR1020070106969A KR100952029B1 (ko) | 2007-10-24 | 2007-10-24 | 모듈 패키지 및 그 제조 방법 |
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KR (1) | KR100952029B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101431639B1 (ko) * | 2013-10-07 | 2014-08-20 | 주식회사 우심시스템 | 보안 결제 장치 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101133117B1 (ko) * | 2004-06-18 | 2012-04-06 | 삼성테크윈 주식회사 | 전자회로 모듈 패키지 |
KR100697980B1 (ko) * | 2005-09-12 | 2007-03-23 | 삼성전기주식회사 | 전자부품을 내장하는 인쇄회로기판의 제조방법 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101431639B1 (ko) * | 2013-10-07 | 2014-08-20 | 주식회사 우심시스템 | 보안 결제 장치 |
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KR100952029B1 (ko) | 2010-04-08 |
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