KR20090019865A - A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide - Google Patents

Abstract

Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the second layer. The silicon oxide layers are annealed after the gap is filled.

Description

A NOVEL DEPOSITION-PLASMA CURE CYCLE PROCESS TO ENHANCE FILM QUALITY OF SILICON DIOXIDE}

This application is directed to US Provisional Application No. 1, filed May 30, 2006. Claim the advantages of 60 / 803,481. The application is also filed on May 30, 2006, entitled “Chemical Vapor Deposition of High Quality Flowing Silicon Dioxide Using Silicon-Containing Precursors and Atomic Oxygen,” filed by Ingle et al. . Related to 60 / 803,493. The application is also filed in US Provisional Application No. 1, filed by Nemani et al. On May 30, 2006 entitled “Methods for Deposition and Curing Low-k Films for Gap Filling and Conformal Film Applications”. Related to 60 / 803,489. In addition, the present application is a U.S. Provisional Application No. 1 filed by Lubomirsky on May 30, 2006 entitled “Process Chamber for Dielectric Gap Filling”. Related to 60 / 803,499. The entire contents of the priority US provisional patent application and related applications are incorporated herein by reference.

As device density for integrated circuits continues to increase, the size and spacing between device structures continues to decrease. The narrower the widths of the trenches between the structures and the gaps of the structures, the higher the ratio of height to width (ie, aspect ratio) in their formation. In other words, due to the continued miniaturization of integrated circuit members, the horizontal width within and between these members shrinks faster than their vertical height.

As the aspect ratio increases, the ability to fabricate device structures has allowed more structures (eg, transistors, capacitors, diodes, etc.) to be packaged on the same surface area of the semiconductor chip substrate, but this creates manufacturing problems. These problems make it difficult to completely fill gaps and trenches in these structures without creating voids or seams during the filling process. Filling the gaps and trenches with a dielectric material type silicon oxide is necessary to electrically insulate near the device structures from each other. If the gaps remain empty, too much noise and leakage current will be generated for the devices, making the devices unable to operate properly (or at all).

When the gap widths are large (when the aspect ratios are small), the gaps are filled relatively easily by rapid deposition of the dielectric material. The deposition material will continue filling from bottom to top until the crevice or trench is completely filled by covering the sides and bottom of the gap. However, as the aspect ratio increases, it becomes more difficult to fill deep, narrow trenches without blockage initiating voids or seams in the fill volume.

Voids and seams in the dielectric layer can cause problems both during fabrication of semiconductor devices and in finished devices. The voids and seams are randomly formed in the dielectric layer and have unexpected sizes, shapes, positions and distribution densities. This causes unexpected inconsistent post-deposition processing of the layer, such as even etching, polishing, annealing and the like. In addition, voids and seams in finished devices cause a change in the dielectric quality of the gaps and trenches in the device structures. This can lead to non-uniform and poor device performance due to electrical crosstalk, charge leakage and even short circuits within and between the device members.

Techniques have been developed to minimize the formation of voids and seams during the deposition of dielectric materials on high aspect ratio structures. This includes slowing the deposition rate of the dielectric material to remain more conformal to the sidewalls and bottom of the trench. More conformal deposition may be reduced to the extent that the deposited material at the top or center of the trench accumulates and eventually seals from the top of the void. Unfortunately, however, slowing down the deposition rate means increased deposition time, which reduces processing efficiency and manufacturing speed.

Another technique for controlling void formation is to increase the flowability of the deposited dielectric material. Materials with better flow forces can fill voids or seams more quickly to prevent permanent defects in filling capacity. Sometimes increasing the flow force of silicon dioxide dielectric material involves adding water vapor or peroxide (eg, H ₂ O ₂ ) to the mixture of precursors used to form the oxide layer. The vapor creates more Si-OH bonds in the deposited film, giving increased flow to the film. Unfortunately, however, an increase in moisture level during deposition of silicon oxide results in the performance of the deposited film including density (ie, increased wet etch rate ratio (WERR)) and dielectric performance (eg, increased k-value). Could adversely affect

Accordingly, what is needed is a dielectric deposition system and processes capable of depositing void-free, seam-free, dielectric films in gaps, trenches, and other device structures with high aspect ratios. In addition, there is still a need for systems and processes capable of depositing dielectric materials at high deposition rates and flow force characteristics that do not adversely affect the quality of the finished fill. These and other aspects of dielectric film deposition are solved by the present invention.

Embodiments of the present invention include methods for filling a gap on a substrate with silicon oxide. The methods include injecting an organo-silicon precursor and an oxygen precursor into the deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and reducing the carbon content in the layer. Etching the layer. In addition, the methods may include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the layer. Silicon oxide layers may be annealed after the gap is filled.

Embodiments of the present invention also include methods of forming a multilayer silicon oxide film on a substrate. The methods may include forming a plurality of silicon oxide layers on a substrate, each silicon oxide layer having a thickness of about 100 GPa to about 20 GPa. The layers may comprise (i) injecting an organo-silicon precursor and an atomic oxygen precursor into the reaction chamber; (ii) reacting the precursors to form a layer on the substrate; And (iii) etching the layer to reduce impurities in the layer. Multiple layers may then be annealed.

In addition, embodiments of the present invention further include systems for performing multiple periods of bottom-up gap filling of gaps on wafer substrates with silicon oxide. The systems can include a deposition chamber in which a gap containing structure is maintained, and a remote plasma generation system coupled with the deposition chamber, wherein the plasma generation system is used to generate an atomic oxygen precursor. The systems may also include an organo-silicon precursor source used to supply the organo-silicon precursor to the deposition chamber, and a precursor processing system used to direct the flow of atomic oxygen precursor and silicon precursor to the deposition chamber. The precursor processing system prevents atomic oxygen and silicon precursors from mixing prior to entering the deposition chamber. The system also includes an etching system for etching individual silicon oxide layers deposited during each cycle of multi-cycle gap filling.

Additional embodiments and features are set forth in the following description, which will be apparent to those skilled in the art upon reviewing the specification, or may be recognized by practice of the invention. Features and advantages of the invention may be implemented and achieved by means, combinations and methods disclosed in the specification.

Further understanding of the features and advantages of the present invention may be appreciated by reference to the remaining parts and figures of the specification, wherein like reference numerals are used in several figures to refer to like parts. For example, a sublabel is associated with a reference sign and followed by a hyphen to indicate one of a number of similar parts. If reference is made to a reference number without description of an existing sublabel, it refers to all of these many similar parts.

1 is a flow chart showing a brief overview of multi-cycle silicon oxide layer deposition in accordance with embodiments of the present invention;

2 is a flowchart illustrating methods of manufacturing a multilayer silicon oxide film according to embodiments of the present invention;

3 is a flow chart highlighting a two-stage etch step in methods of manufacturing a multilayer silicon oxide film in accordance with embodiments of the present invention;

4 is another flowchart illustrating methods of manufacturing a multilayer silicon oxide film according to embodiments of the present invention;

5A-F illustrate a structure having a gap structure gradually filled with a multilayer silicon film in accordance with embodiments of the present invention;

6A shows a vertical cross sectional view of a substrate processing system that can be used to form silicon oxide layers in accordance with embodiments of the present invention; And

6B is a simplified diagram of a system monitor / controller component of a substrate processing system in accordance with embodiments of the present invention.

Systems and methods for multilayer, multicycle depositions of silicon oxide in gaps and on surfaces of a wafer substrate are disclosed. Each oxide layer is thin enough (eg, about 50 kPa to about 300 kPa) to allow an etching process to decompose and remove impurities such as organic and hydroxyl groups that may adversely affect the quality and dielectric properties of the film. When multiple oxide layers are deposited and etched, annealing may be performed to form the layers into a high-quality, low-K silicon oxide film.

Silicon oxide can be formed from the reaction of highly reactive atomic oxygen and organo-silicon precursors such as OMCATS. Atomic oxygen may be generated outside the chamber where the deposition takes place first and remain isolated from the organo-silicon precursor until the organo-silicon precursor is mixed in the chamber. The silicon oxide formed is carbon rich and highly fluid, providing a deposition film that can easily flow to the bottoms of narrow gaps and trenches. After the etching process removes at least some of the large carbon groups and hydroxyl groups from the deposited film, a subsequent oxide deposit can flow over the first layer and be etched in the next oxide layer. For example, the cycle may be repeated several times until the gap or trench is filled from the bottom by multiple silicon oxide layers. This multicycle process is considered bottom-up gap filling. A more detailed description of the methods, products, and systems of the present invention is disclosed.

Example Oxide Layer Forming Processes

1 is a flow diagram for a simplified overview of multi-cycle silicon-oxide layer deposition in accordance with embodiments of the present invention. The illustrated method 100 includes providing a structure including a gap in the deposition chamber 102. Structures may be formed on the substrate including gaps, trenches, and the like having a height to width aspect ratio of at least about 5: 1, at least 7: 1, at least 10: 1, at least 13: 1, at least 15: 1.

A plurality of silicon oxide layers is then formed in the gaps (and other surfaces) of the substrate 104. Silicon oxide may be deposited by reaction of an oxygen-containing precursor and an organo-silicon precursor in the reaction chamber. The oxygen containing precursor may include atomic oxygen that is generated remotely outside the deposition chamber. Atomic oxygen includes molecular oxygen (O ₂ ), ozone (O ₃ ), nitrogen-oxygen compounds (eg NO, NO ₂ , N ₂ O, etc.), hydrogen-oxygen compounds (eg H ₂ O, H ₂ O ₂ , etc.), carbon-oxygen compounds (eg, CO, CO _2, etc.) and other oxygen containing precursors and combinations of precursors, can be produced by decomposition of the precursors.

Precursor decomposition to generate atomic oxygen can be performed by thermal decomposition, ultraviolet light decomposition, and / or plasma decomposition, among other methods. Plasma decomposition involves charging the plasma from helium, argon, and the like into a remote plasma generation chamber and injecting oxygen into the plasma to generate an atomic oxygen precursor.

Atomic oxygen may first be injected into the organo-silicon precursor in the chamber. The organo-silicon precursor may include compounds having direct Si—C bonds and / or compounds having Si—O—C bonds. Examples of organosilane silicon precursors include, among others, dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (OMTS), octamethylcyclotetrasiloxane (OMCTS), tetramethylcyclotetrasiloxane (TOMCATS), DMDMOS, DEMS, methyl triethoxysilane (MTES), phenyldimethylsilane, and phenylsilane ) May be included.

The organo-silicon precursor may be mixed with the carrier gas prior to or during injection into the deposition chamber. The carrier gas may be an inert gas that does not improperly interfere with the formation of the oxide film on the substrate. Examples of carrier gases include helium, neon, argon and hydrogen (H ₂ ), among other gases.

In embodiments of the method 100, the atomic oxygen and the organo-silicon precursor are not mixed before being injected into the deposition chamber. Precursors can enter the chamber through spatially spaced individual precursor inlets disposed near the reaction chamber. For example, the atomic oxygen precursor may enter from the inlet (or inlets) at the top of the chamber and be located directly above the substrate. The inlet directs the flow of the oxygen precursor in a direction perpendicular to the substrate deposition surface. Meanwhile, the silicon precursor can enter from one or more inlets near the sides of the deposition chamber. The inlets can direct the flow of the silicon precursor in a direction substantially parallel to the deposition surface.

Further embodiments include transferring atomic oxygen and silicon precursors through individual ports of the multi-port showerhead. For example, a showerhead positioned over the substrate includes an opening pattern for the precursor to allow the precursors to enter the deposition chamber. The first subset of openings can be supplied by the atomic oxygen precursor, while the second subset of openings are supplied by the silicon precursor. Precursors moving through different sets of openings may be fluidically isolated from one another until they exit the deposition chamber. A more detailed description of the form and design of the precursor processing equipment is given by Lubomirsky, with the agent docket number AOl 1162 / T72700, filed on the same date as the present application, entitled “Process Chamber for Dielectric Gap Filling”. Co-transferred US Is disclosed in a patent application, which is incorporated herein by reference.

As atomic oxygen and silicon precursors react in the deposition chamber, a silicon oxide layer is formed on the substrate deposition surface. The initial oxide layer has excellent flow force and can quickly move to the bottom of the gaps in the structures on the substrate surface.

After each oxide layer is deposited, an etching step may be performed on the layer to remove impurities. This may include decomposing large organic groups into small carbon containing molecules, and decomposing at least some Si—OH bonds to form water and silicon oxide.

Following deposition and etching of a number of silicon oxide layers, annealing may be performed to remove moisture and transform the layers into a dense, high quality oxide film. Embodiments include performing annealing after each layer of silicon oxide is deposited and etched. Further embodiments may include intermediate annealing after one or more layers are formed, but before all layers are finally annealed. For example, intermediate annealing may be performed after two, three, four, five, etc. layers have been deposited, followed by final annealing of all layers.

2, a flow diagram illustrating a method 200 of manufacturing a multilayer silicon oxide film according to embodiments of the present invention is shown. The method 200 can include injecting precursors into a deposition chamber that includes a substrate 202. As noted above, the precursors may include an atomic oxygen precursor and an organo-silylcone precursor. Atomic oxygen is 400 to 6000 Watts (eg, in a combined gas stream of, for example, molecular oxygen (O ₂ ) flowing at about 600 to about 1200 sccm and argon gas flowing at, for example, about 900 to 1800 sccm 5500 Watts) and can be generated in a remote high density plasma generator that supplies RF power.

The organo-silicon precursor may be injected into the deposition chamber by mixing the organo-silicon compound (gas or liquid) with a carrier gas such as helium or molecular oxygen (H ₂ ). For example, helium bubbles at a flow rate of about 600 to about 2400 sccm through a room temperature organo-silicon precursor such as octamethylcyclotetrasiloxane (OMCTS) to provide a flow of OMCTS to the chamber at a rate of about 800 to about 1600 mgm. Can be bubbled.

The precursors react with each other in the chamber to form a first layer on the substrate 204. The total pressure in the chamber during deposition of the oxide layer is, for example, about 0.5 Torr to about 6 Torr. Higher overall pressures (eg 1.3 Torr) deposit oxide films with more flow-like quality, while lower pressures (eg 0.5 Torr) deposit more conformal oxide layers. do. Since atomic oxygen is highly reactive, the deposition temperature in the reaction chamber is relatively low (eg, about 100 ° C. or less). Oxide deposition rate ranges can range from about 125 mW / min to about 2 μm / min (eg, about 500 mW / min to about 3000 mW / min; about 1500 mW / min, etc.). The thickness of the layer can be from about 5 kPa to about 500 kPa (eg, from about 100 kPa to about 200 kPa).

After the first oxide layer is formed, the flow of precursors into the chamber is stopped and the first oxide layer can be etched (206). An etching step can be used to decompose and remove impurities in the layer and to planarize the layer. As disclosed below with reference to FIG. 3, the etching process may include a single etching step, or multiple etching steps.

Following etching of the first layer, precursors are injected into the deposition chamber (208) and react (210) to form a second oxide layer on the substrate. The second oxide layer can be formed under the same reaction conditions as the first layer, or under different conditions (eg, chamber pressure, temperature, organo-silicon precursor, etc.).

After the second layer is formed, it may be etched 212 to reduce impurity levels and / or planarize the layer. The second layer may be etched using the same process used to etch the first layer, or may be etched using different processes (eg, different number of etch steps, different etch precursors, different power levels, etc.). Can be.

Following formation and etching of the second silicon oxide layer (and any additional oxide layers), the oxide layers may be annealed 214 to form a uniform high quality silicon oxide gapfill. The final gapfill has a dielectric constant (i.e., k-value) of less than 4.0 (e.g., less than 3.5, less than about 3.0, etc.) and less than 2: 1 (e.g., from about 1.8: 1 to about 1.4: 1). It may have a wet-etch rate ratio (WERR). The gapfill is uniform throughout the fill volume and may in some cases include some voids or seams.

3 shows a flowchart highlighting the two-stage etch step of a method 300 of manufacturing a multilayer silicon oxide film in accordance with embodiments of the present invention. The method 300 includes providing 302 a substrate in a reaction chamber, and injecting precursors 304 (eg, oxygen and silicon precursors) into the reaction chamber. The precursors then react 306 to form a second silicon oxide layer on the substrate, followed by a two-stage etch.

Two-stage etch begins by performing a first etch on oxide layer 308. This first etch includes using a low density plasma to decompose the large organic molecules and remove at least some of the carbon from the layer. Such low density plasma etching may include using RPS to generate an Ar / O ₂ plasma that etches the oxide layer. Etching conditions include, for example, striking a plasma from 1600 sccm of O ₂ and 400 sccm of argon at a power of about 5500 Watt, and injecting it into the deposition chamber at a pressure of about 760 mTorr. Such plasma etching can decompose large carbon groups and remove carbon impurities from the oxide layer.

Following the first etch, a second etch of the oxide layer is performed 310 at high plasma density to remove at least some of the hydroxyl groups from the layer. Such high density plasma etching includes exposing a layer to a plasma formed from flow decomposition of molecular oxygen (eg, 600 sccm) using a high power RF field (eg, 6000 Watts). The oxygen plasma can be injected into the deposition chamber at a pressure of, for example, 8 mTorr and react with the -OH groups in the oxide layer to form silicon dioxide and water.

Deposition and etch cycles may be repeated with the next oxide layer 312 formed on top of the previous layer. The deposited and etched layers accumulate until a predetermined number of layers and / or film thicknesses are achieved, and the multiple layers are annealed (314). Annealing can be performed in a single step or in multiple steps. The single stage annealing can be carried out, for example, with a plurality of layers substantially between about 300 ° C. and about 1000 ° C. (eg between about 600 ° C. and about 900 ° C.) in a dry atmosphere (eg dry nitrogen, helium, argon, etc.) By heating them. Annealing removes moisture from the deposited layer and converts the Si-OH groups to silicon oxide.

Multistage annealing may comprise a two-stage annealing where the layers first go through a wet annealing stage, such as heating the bed to the presence of steam, for example at about 700 ° C. This can lead to a dry annealing stage, where the layers can be heated to a high temperature (eg, about 900 ° C.) in a substantially moisture-free atmosphere (eg, dry N ₂ ). The first wet annealing assists hydrolysis of additional Si-C bonds and Si-OH bonds, while dry annealing converts Si-OH into silicon oxide bonds to remove moisture from the layers.

In addition to wet and dry thermal annealing, other annealing techniques (alone or in combination) may be used to anneal multiple oxide layers. This includes, in particular, steam annealing, plasma annealing, plasma annealing, ultraviolet light annealing, e-beam annealing and / or microwave annealing.

Referring to FIG. 4, another flow diagram illustrating a method 400 of manufacturing a multilayer silicon oxide film according to embodiments of the present invention is shown. The method 400 includes providing 402 a substrate in a deposition chamber 402 and injecting precursors (eg, atomic oxygen and organo-silicon precursors) into the chamber. The precursors react to form a silicon oxide layer on the substrate 406, and the next oxide layer is etched 408.

At this time, a check can be made to determine whether the cumulative thickness of the deposited oxide layers has reached a predetermined point (410). Once the predetermined thickness level of the entire oxide film is reached, the deposition and etch cycle ends, and the film may be annealed (412). However, if the thickness levels are not met, other oxide deposition and etching cycles may be made to add at least one additional layer to the oxide film.

Determination of whether the oxide film has reached a predetermined thickness may be made by measuring the thickness of the deposited and etched layers, or by calculating the number of layers required to reach the desired film thickness. For example, if each deposited and etched film thickness is 100 microseconds and the desired film thickness is 1.2 mu m, twelve deposition and etching cycles may be performed to form the film. The thickness of each deposited layer can be set, among other parameters, in particular by controlling parameters that affect the oxide deposition rate, such as the shape and flow rates of the reactive precursors, the overall pressure and temperature of the deposition chamber. As noted above, typical deposition rates for oxide layers are from about 500 kW / min to about 3000 kW / min (eg, about 1500 kW / min).

5A-F illustrate a substrate having a gap structure gradually filled with a multilayer silicon oxide film using embodiments of a multi-cycle deposition-etch oxide layer formation process. 5A shows substrate 502 with gap 504 formed. It will be appreciated that the gap 504 shown in FIGS. 5A-F is shown to have a relatively low aspect ratio to further illustrate the progress of the oxide filled layers. Embodiments of the gap filling methods of the present invention are 5: 1, 6: 1, 7: 1, 8: 1, 9: 1, 10: 1, 11: 1, 12: 1, 13: 1, 14: 1, And void- and seam-free deposition in gaps having aspect ratios greater than 15: 1.

5B shows the first oxide layer 506a deposited in the gap 504. Silicon oxide having a good flow quality of the formed layer causes the film to move quickly to the bottom of the gap 504. Thus, the thickness of the oxide deposited at the bottom of the gap 504 may be greater than the oxide thickness along the sidewalls of the gap.

5C and 5D show additional oxide layers 506b, 506c, etc., deposited on the layers previously deposited and etched in the gap 504. These additional layers may be bottomed up in gap 504 until the desired oxide film thickness level is reached (eg, on top of gap 504).

Once the last oxide layer of the plurality of oxide layers is deposited and etched, annealing may be performed to form the layers into a uniform film 508, as shown in FIG. 5E. The film may be planarized by, for example, plasma etching or CMP to remove deposited materials formed on top of the gap 504. 5F shows the remaining silicon oxide gapfill 510 with some voids or seams in some cases and with high film quality and dielectric properties.

Example Substrate Processing System

Deposition systems that can implement embodiments of the present invention include, among other types of systems, particularly high density plasma chemical vapor deposition (HDP-CVD) systems, plasma enhanced chemical vapor deposition (PECVD) systems, subatmospheric chemical vapor deposition ( SACVD) systems, and thermal chemical vapor deposition systems. Specific examples of CVD systems that may implement embodiments of the present invention include CENTURA ULTIMA ^™ HDP-CVD chambers / systems and PRODUCER ^™ PECVD chambers / systems available from Applied Materials, Inc. of Santa Clara, California.

One suitable substrate processing system that can be modified to utilize embodiments according to the present invention is shown and disclosed in co-transferred US patent applications Nos. 6,387,207 and 6,830,624, which are incorporated herein by reference. 6A is a vertical sectional view of a CVD system 10 having a vacuum or processing chamber 15 that includes a chamber wall 15a and a chamber lid assembly 15b.

The CVD system 10 includes a gas dispersion manifold 11 for distributing process gases to a substrate (not shown) located on a heating pedestal 12 centered in the process chamber 15A. The gas dispersion manifold 11 may be formed from an electrically conductive material to serve as an electrode for forming a capacitive plasma. During processing, the substrate (eg, semiconductor wafer) is placed on the flat (or slightly convex) surface 12a of the pedestal 12. Pedestal 12 moves controllably between the lower loading / off-loading position (shown in FIG. 6A) and the upper processing position adjacent to manifold 11 (shown by dashed line 14 in FIG. 6A). Can be. The centerboard (not shown) includes sensors that provide information about the location of the wafers.

Deposition and carrier gases are injected into the chamber 15 through a conventional flat, circular gas dispersion faceplate 13a. In particular, the deposition process gases flow into the chamber through the conventional perforated blocker plate 42 and the holes 13b of the next gas dispersion faceplate 13a.

Prior to reaching the manifold 11, deposition and carrier gases are input from the gas source 7 to the mixing system 9 via gas supply lines 8, combined and transmitted to the manifold 11. Generally, the supply line for each process gas is (i) several safety shut-off valves (not shown) used to shut off the process gas flow to the chamber either automatically or manually, and (ii) ) A mass flow controller (not shown) for measuring the flow of gas through the supply line. When toxic gases are used in the process, several safety shutoff valves are located in each gas supply line in conventional configurations.

The deposition process performed in the CVD system 10 may be a thermal process or a plasma-enhancing process. In the plasma intensification process, the RF power source 44 is configured to disperse the gas dispersion faceplate 13a and pedestal 12 such that the process gas mixture is excited to produce a plasma in the cylindrical region between the faceplate 13a and the pedestal 12. Apply power between (This region is considered to be a "reaction region" in the present invention). The components of the plasma react to deposit the desired film on the surface of the semiconductor wafer supported on the pedestal 12. RF power source 44 is a mixed frequency RF typically powered at a high RF frequency (RFl) and a low RF frequency (RF2) of 13.56 MHz to enhance the decomposition of reactive species injected into the vacuum chamber 15. It is a power source. In the thermal process, RF power source 44 is not used and the process gas mixture is thermally deposited to deposit the desired film on the surface of the semiconductor wafer supported on the pedestal 12 that is resistively heated to provide thermal energy for the reaction. React with

During the plasma-enhanced deposition process, the plasma heats the entire process chamber 10 including the walls of the chamber body 15a surrounding the exhaust passage 23 and the shutoff valve 24. If the plasma is not turned in the thermal deposition process or during the thermal deposition process, hot liquid is circulated through the walls 15a of the process chamber 15 to maintain the chamber at elevated temperature. The passages in the rest of the chamber walls 15a are not shown. Fluids used to heat the chamber walls 15a include typical types of fluids, that is, water-based ethylene glycol or oil-based heat transfer fluids. This heating (which is considered to be heated by a "heat exchanger") preferably reduces or eliminates the condensation of unwanted reaction byproducts and condenses on the walls of the cooling vacuum passage during periods of no gas flow and moves back to the processing chamber. Improve the elimination of volatile products of process gases and other contaminants that may contaminate the process.

The remainder of the gas mixture not deposited in the layer containing the reaction byproducts is evacuated from the chamber 15 by a vacuum pump (not shown). In particular, the gases are exhausted into the annular discharge plenum 17 through an annular slotted orifice 16 surrounding the reaction zone. The annular slot 16 and plenum 17 are defined by the gap between the top of the cylindrical side wall 15a of the chamber (including the upper dielectric lining 19 on the wall) and the circular chamber lid 20. The 360 degree circular symmetry and uniformity of the slot orifice 16 and the plenum 17 are important for achieving a uniform flow of process gases over the wafer to deposit a uniform film on the wafer.

From the exhaust plenum 17, gases flow below the lateral extension 21 of the exhaust plenum 17, through the down-extended gas passage 23, past an observation port (not shown), and a vacuum shutoff valve ( 24) (the body of the valve is integrated with the lower chamber wall 15a) and flows through the foreline (not shown) to the outlet outlet 25 which is connected to an external vacuum pump (not shown).

The wafer support platter of the pedestal 12 (preferably aluminum, ceramic, or a combination thereof) is a built-in single loop construction configured to make two full turns of parallel concentric circles. The resistive heating is performed using a heater member. The outer part of the heater element extends near the periphery of the support flatter, while the inner part extends in a concentric path with small radii. Wiring to the heater member passes through the stem of the pedestal 12.

Typically, any or all of the chamber linings, gas inlet manifold faceplates and other reactor hardware consist of a material such as aluminum, anodized aluminum, or ceramic. An example of such a CVD apparatus is disclosed in co-transferred U.S. Patent 5,558.717, entitled "CVD Processing Chamber" by Zhao et al., Referenced herein.

As the wafers are transferred into and out of the body of the chamber 15 by a robot blade (not shown) through the insertion / removal opening 26 on the side of the chamber 10, the lift mechanism and motor 32 (FIG. 6A) Heater pedestal assembly 12 and their wafer lift pins 12b are raised and lowered. The motor 32 raises and lowers the pedestal 12 between the processing position 14 and the lower wafer-loading position. The valves of the motor, the flow controllers connected to the supply lines 8, the gas delivery system, the throttle valve, the RF power source 44, and the chamber and substrate heating systems are only part of the control lines 36 shown. All are controlled by the system controller. Controller 34 relies on feedback from optical sensors to determine the position of movable mechanical assemblies, such as susceptors and throttle valves, moved by appropriate motors under the control of controller 34.

In an exemplary embodiment, the system controller includes a hard disk drive (memory) 38, a floppy disk drive, and a processor 37. The processor includes single-board computer (SBC), analog and digital input / output boards, interface boards and stepper motor controller boards. Various components of the CVD system 10 conform to the Versa Modal European (VME) standard, which defines board, card cage, and connector dimensions and shapes. The VME specification also defines a bus structure with a 16-bit data bus and a 24-bit address bus.

System controller 34 controls all operations of the CVD apparatus. The system controller executes system control software, which is a computer program stored on a computer-readable medium, such as memory 38. Preferably, memory 38 is a hard disk drive, but memory 38 may be another type of memory. The computer program includes sets of instructions that indicate timing, mixture of gases, chamber pressure, chamber temperature, RF power levels, susceptor position, and other parameters for a particular process. For example, other computer programs stored in other memory elements, including floppy disks or other additional suitable drives, may be used to operate the controller 34.

루틴들의 목적 코드(object code)와 링크된다. 링크되고 컴파일된 목적 코드를 실행하기 위해, 시스템 사용자는 목적 코드를 호출하여, 컴퓨터 시스템이 메모리내의 코드에 로딩되게 한다. 다음 CPU는 프로그램에서 식별된 업무들을 수행하도록 코드를 판독 및 실행한다.The process of cleaning the chamber 15 or the process of depositing a film on the substrate may be implemented using a computer program product executed by the controller 34. The computer program code may be written in any conventional computer readable program language such as, for example, 68000 assembly language, C, C ++, Pascal, Fortran or others. Appropriate program code is written into a single file or multiple files using a conventional text editor and stored or embedded in a computer usable medium, such as a memory system of a computer. If the code text written is a high level language, the code is compiled and the formed compilation code is precompiled Microsoft Windows.

Linked with the object code of the routines. To execute the linked and compiled object code, the system user calls the object code, causing the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program.

The interface between the user and the controller 34 is via the CRT monitor 50a and the light pen 50b shown in FIG. 6B, which illustrates a system monitor and CVD system 10 in a substrate processing system that may include one or more chambers. ) Is a simplified diagram. In a preferred embodiment, two monitors 50a are used, one mounted on the clean room wall for the operator and the other behind the wall for the service technician. The monitors 50a can display the same information simultaneously, but only one light pen 50b can be used. At the tip of the light pen 50b, an optical sensor detects light emitted by the CRT display. To select a particular screen or function, the operator touches a designated area of the display screen and presses a button on pen 50b. The touched areas change to highlighted colors to confirm communication between the light pen and the display screen, or display a new menu or screen. Other elements, such as a keyboard, mouse, or other pointing or communication elements, may be used instead of or in addition to the light pen 50b to allow communication of the user with the controller 34.

등과 같은 세라믹 물질로 구성될 수 있다. 설치될 때, 혼합 장치(70) 및 세라믹 절연체(66)는 리드 어셈블리(15b)의 일부를 형성할 수 있다. 절연체(66)는 혼합 장치(70) 및 가스 분산 매니폴드(11)로부터 금속 어뎁 터(64)를 절연시켜 하기 보다 상세히 설명되는 바와 같이 리드 어셈블리(15b)에 형성되는 제 2차 플라즈마에 대한 전위를 감소시킨다. 3-웨이 밸브(77)는 원격 플라즈마 발생기(60)를 통해 또는 직접적으로 프로세스 챔버(15)로의 프로세스 가스들의 흐름을 제어한다.6A shows a remote plasma generator 60 mounted to the lid assembly 15b of the process chamber 15 that includes a gas dispersion faceplate 13a and a gas dispersion manifold 11. Mount adapter 64 is mounted to remote plasma generator 60 on lid assembly 15b, as best seen in FIG. 6A. Typically, the adapter 64 is made of metal. The mixing device 70 is coupled with the upstream side of the gas dispersion manifold 11 (FIG. 6A). The mixing device 70 includes a mixing insert 72 disposed inside the slot 74 of the mixing block for mixing the process gases. The ceramic insulator 66 is disposed between the mounting adapter 64 and the mixing device 70 (FIG. 6A). Ceramic insulator 66 is Al ₂ O ₃ (99% purity), Teflon

It may be made of a ceramic material such as. When installed, the mixing device 70 and ceramic insulator 66 may form part of the lead assembly 15b. The insulator 66 insulates the metal adapter 64 from the mixing device 70 and the gas dispersion manifold 11 to the potential for the secondary plasma formed in the lead assembly 15b as described in more detail below. Decreases. The three-way valve 77 controls the flow of process gases through the remote plasma generator 60 or directly to the process chamber 15.

발생기가 있다. ASTRON

발생기는 프로세스 가스를 분해시키기 위해 낮은-필르의 토로이달 플라즈마를 이용한다. 일 실시예에서, 플라즈마는 프로세스 챔버(15)에서의 막 증착물들을 세정하는데 이용될 수 있는 유리 불소(free fluorine)을 생성하기 위해 아르곤과 같은 캐리어 가스 및 NF₃와 같은 불소-함유 가스를 포함하는 프로세스 가스를 분해시킨다.The remote plasma generator 60 is preferably a compact, self-limiting unit that is conveniently mounted on the lid assembly 15b and can be easily calibrated on current chambers without costly and time consuming deformation. One suitable unit is ASTRON, commercially available from Applied Science and Technology Inc. of Warborn, Massachusetts.

There is a generator. ASTRON

The generator uses a low-pill toroidal plasma to decompose the process gas. In one embodiment, the plasma comprises a carrier gas such as argon and a fluorine-containing gas such as NF ₃ to produce free fluorine that can be used to clean film deposits in process chamber 15. Decompose the process gas.

It will be appreciated by those skilled in the art that with a few embodiments disclosed, various modifications, optional configurations, and equivalents may be used without departing from the scope of the present invention. In addition, the number of known processes and members has not been disclosed to avoid unnecessarily obscuring the present invention. Therefore, the above description should not be chosen as limiting the burner of the present invention.

When values are provided, it will be understood that, unless otherwise indicated, intermediate values of about ten of the lower limit units are specifically disclosed between the upper and lower limits of these ranges. Each small range is included between any stated value or intermediate value in the stated range and an intermediate value in any other mentioned or mentioned range. The upper and lower limits of these small ranges may be included or excluded independently of the above ranges, and each range is within the scope of the present invention when one or both of the limits are included or both are not included within the small range. However, it is treated with any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, the range excluding one or both of these included limits is included.

As used in the present invention and the appended claims, the singular forms “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to “a process” includes many such processes, and a reference to “the precursor” refers to one or more precursors and equivalents known and known to those skilled in the art. Include references for.

Also, as used herein and in the claims below, "comprise," "comprising," "include," "including," and "includes" refers to the presence of the mentioned features, integers, parts, or steps. Does not exclude the presence or addition of one or more other features, integers, parts, steps, actions, or groups.

Claims (36)

As a method of filling gaps on a substrate with silicon oxide, Injecting an organo-silicon precursor and an oxygen precursor into the deposition chamber; Reacting the precursors such that a first silicon oxide layer is formed in the gap on the substrate; Etching the first silicon oxide layer to reduce the carbon content in the layer; Forming a second silicon oxide layer on the first layer and etching the second layer to reduce the carbon content in the layer; And Annealing the silicon oxide layers after the gap is filled Including a gap filling method. The method of claim 1, And the oxygen precursor comprises atomic oxygen produced outside of the deposition chamber. The method of claim 2, wherein the atomic oxygen, Forming a plasma from a gas mixture comprising argon; And Injecting an oxygen precursor into the plasma, wherein the oxygen precursor is decomposed to form atomic oxygen- Gap filling method, characterized in that formed by. The method of claim 3, wherein The oxygen precursor is selected from the group consisting of molecular oxygen, ozone and nitrogen dioxide gap filling method. The method of claim 2, wherein the atomic oxygen, Injecting an oxygen precursor into a photodissociation chamber; And Exposing the oxygen precursor to ultraviolet light, the ultraviolet light decomposing the oxygen precursor to form atomic oxygen; Gap filling method, characterized in that formed by. The method of claim 2, Wherein said organo-silicon precursor and said atomic oxygen are not mixed until after they are injected into said deposition chamber. The method of claim 1, The organo-silicon precursor is dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (OMTS), octamethylcyclotetra Siloxane (OMCTS), tetramethylcyclotetrasiloxane (TOMCATS), DMDMOS, DEMS, methyl triethoxysilane (MTES), phenyldimethylsilane, or phenylsilane. Gap filling method. The method of claim 1, Wherein the first and second silicon oxide layers each have a thickness of about 100 GPa to about 200 GPa. The method of claim 1, wherein etching the first and second silicon oxide layers comprises: Exposing the layer to a first plasma having a first density, the first plasma decomposing large carbon molecules in the layer; And Exposing the layer to a second plasma having a second density higher than the first density, the second plasma decomposing a silicon-hydroxide bond in the layer. Gap filling method comprising a. The method of claim 1, Annealing the silicon oxide layers comprises annealing with a test non-reactive gas at a temperature of about 800 ° C. or higher. The method of claim 10, Wherein said non-reactive gas is nitrogen (N ₂ ) and said temperature is 900 ° C. The method of claim 1, The method includes forming additional silicon oxide layers on the first and second silicon layers, each additional silicon oxide layer having a thickness of about 50 kV to about 500 kV. Filling method. The method of claim 12, And the additional silicon oxide layers are etched in the same manner as the first and second silicon oxide layers. The method of claim 12, Wherein the total thickness of the silicon oxide layers is between about 500 GPa and about 10,000 GPa. The method of claim 1, And the annealed silicon oxide layers have a wet etch rate ratio (WERR) of about 2: 1 or less. The method of claim 1, And the annealed silicon oxide layers have a wet etch rate ratio (WERR) of about 1.8: 1 to about 1.4: 1. The method of claim 1, And the annealed silicon oxide layers have a k-value of about 4.0 or less. The method of claim 1, The method further comprises pretreating the substrate with a high density plasma prior to injecting the precursors into the deposition chamber. The method of claim 1, Wherein the gap has a height to width aspect ratio of at least about 5: 1. The method of claim 1, Wherein the gap has a height to width aspect ratio of at least about 13: 1. A method of forming a multilayer silicon oxide film on a substrate, Forming a plurality of silicon oxide layers on the substrate; And Annealing the plurality of layers Wherein each of the silicon oxide layers has a thickness of about 100 GPa to about 200 GPa, and each of the layers is (i) injecting an organo-silicon precursor and an atomic oxygen precursor into the reaction chamber, (ii) reacting the precursors to form the layer on the substrate, and (iii) etching the layer to reduce impurities in the layer A method of forming a multilayer silicon oxide film, which is formed by. The method of claim 21, Wherein the atomic oxygen precursor is generated outside the deposition chamber and the organo-silicon and atomic oxygen precursors are not mixed until after they are injected into the reaction chamber. The method of claim 21, wherein etching the layers comprises: Exposing the substrate to a first plasma having a first density, the first plasma decomposing large carbon molecules in the layer; And Exposing the layer to a second plasma having a second density greater than the first density, the second plasma decomposing a silicon-hydroxide bond in the layer. Forming a multilayer silicon oxide film comprising a. The method of claim 21, Annealing the plurality of layers comprises thermal annealing, steam annealing, plasma annealing, ultraviolet light annealing, e-beam annealing or microwave annealing. The method of claim 21, wherein the annealing the plurality of layers comprises: Heating the substrate to a first annealing temperature in the presence of steam; And Heating the substrate to a second annealing temperature in dry nitrogen The method of forming a multilayer silicon oxide film comprising a. The method of claim 25, Wherein the first annealing temperature is about 650 ° C. and the second annealing temperature is about 900 ° C. 18. The method of claim 21, Wherein each of the plurality of layers is formed at a rate of about 125 μs / min to about 2 μm / min. The method of claim 21, Wherein each of the layers is etched in about 3 minutes or less. The method of claim 21, And wherein said plurality of layers are annealed for about 30 minutes or less. The method of claim 21, Wherein the plurality of layers have a wet etch rate ratio (WERR) of about 1: 8 to about 1.4: 1. The method of claim 21, And wherein the plurality of layers have a k-value of about 4.0 or less. The method of claim 21, Wherein said multilayer silicon oxide film has a thickness of about 1000 GPa to about 3000 GPa. A system for performing a multi-cycle gap filling up gaps on a wafer substrate with silicon oxide, the system comprising: A deposition chamber in which a substrate containing a gap is held; A remote plasma generation system coupled with the deposition chamber, the plasma generation system being used to generate an atomic oxygen precursor; An organo-silicon precursor source used to supply an organo-silicon precursor to the deposition chamber; A precursor processing system used to direct the flow of the atomic oxygen precursor and the silicon precursor into the deposition chamber, the precursor processing system preventing the atomic oxygen and silicon precursors from mixing before entering the deposition chamber -; And Etching system for etching individual silicon oxide layers deposited during each cycle of multi-cycle gap filling Including a multi-cycle performance system. The method of claim 33, wherein And the system further comprises an annealing system for annealing a plurality of silicon oxide layers formed on the substrate. The method of claim 34, wherein The annealing system comprises a thermal annealing system, a steam annealing system, a plasma annealing system, an ultraviolet light annealing system, an e-beam annealing system, or a microwave annealing system. The method of claim 33, wherein The system includes a high density plasma chemical vapor deposition (HDPCVD) system.

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