JP5225268B2 - A novel deposition plasma hardening cycle process to enhance silicon dioxide film quality - Google Patents

Description

Cross-reference of related applications

  [0001] This application claims the benefit of US Provisional Application No. 60 / 803,481, filed May 30, 2006. This application is also referred to as “No. 3 in the United States of America, No. 3 by the United States Application No. 3 by the“ CHEMICAL VAPOR DEPOSITIONOF HIGHQUALITY FLOW-LIKE SILICON DIOXIDUSING ASILICON CONTOURING COORSOR AND ATOMIC OXYLE et al. ”Filed on May 30, 2006. This application is also related to US Provisional Application No. 60 / 803,489 by Nemani et al., Entitled “AMETHOD FORDEPOSITING AND CURING LOW-K FILMFORGAPFILLAND CONFORMALFILM APPLICATIONS” filed on May 30, 2006. Further, this application is related to US Provisional Application No. 60 / 803,499 by Lubomirsky, named “PROCESSSCHAMBER FORDELECTRIC GAPFILL”, filed May 30, 2006. The entire contents of the priority US provisional patent application and related applications are incorporated herein by reference in their entirety.

Background of the Invention

  [0002] As the device density of integrated circuits continues to increase, the size and distance between device structures continues to decrease. Narrower widths in structure gaps and trenches between structures increase the height to width ratio (ie, aspect ratio) in their formation. In other words, the continued miniaturization of integrated circuit elements has reduced the lateral width faster than their vertical height within and between these elements.

  [0003] The ability to create device structures while constantly increasing the aspect ratio allowed more structures (eg, transistors, capacitors, diodes, etc.) to fill the same surface area of a semiconductor chip substrate. Manufacturing problems have also arisen. One of these problems is that it is difficult to completely fill the gaps and trenches in these structures without creating voids or seams during the filling process. Filling the gap and trench with a dielectric material such as silicon oxide is necessary to electrically isolate adjacent device structures from each other. If the gap remained empty, there was too much electrical noise and current leakage of the device to operate properly (or at least).

  [0004] If the gap is wider (the aspect ratio is smaller), the gap is relatively easy to fill with a rapid deposit of dielectric material. Deposited material covers the sides and bottom of the gap and continues to fill from bottom to top until the gap or trench is fully filled. However, as the aspect ratio increased, it became more difficult to fill deep and narrow trenches without the onset of closure having voids or seams in the fill volume.

  [0005] Voids and seams in dielectric layers create problems both during semiconductor device manufacturing and in finished devices. Voids and seams are randomly formed in the dielectric layer and have unpredictable size, shape, position, and population density. This results in unpredictable and inconsistent post-deposition processing such as uniform etching, polishing, annealing and the like. Voids and seams in the finished device change the dielectric properties of the gap and trench in the device structure. This can result in uneven and poor device performance due to crosstalk, charge leakage, and shorts within and between device elements.

  [0006] Techniques have been developed to minimize void and seam formation during the deposition of dielectric materials on high aspect ratio structures. These include slowing the deposition rate of the dielectric material so that it remains more conformal to the sidewalls and bottom of the trench. More conformal deposition can reduce the degree to which deposited material accumulates at the top or middle of the trench and ultimately seals the top of the void. Unfortunately, however, slowing the deposition rate means an increase in deposition time and reduces processing efficiency and production rate.

[0007] Another technique for controlling void formation is to increase the fluidity of the deposited dielectric material. A more fluid material will fill the void or seam faster and prevent permanent defects within the fill volume. Increasing the flowability of silicon oxide dielectric materials involves adding water vapor or peroxide (eg, H ₂ O ₂ ) to the mixture of precursors used to form an oxide layer. Water vapor creates more Si-OH bonds in the deposited layer, giving the film increased fluidity. Unfortunately, however, the increase in moisture levels during silicon oxide deposition is due to the deposited layer including its density (ie, high wet etch rate ratio (WERR)) and dielectric properties (ie, high k value). Can adversely affect the characteristics of

  [0008] Accordingly, there remains a need for dielectric deposition systems and processes that can deposit void-free, seam-free dielectric films into gaps, trenches, and other device structures having high aspect ratios. There remains a need for systems and processes that can deposit dielectric materials with high deposition rates and flow characteristics that do not adversely affect the quality of the finished fill. These and other aspects of dielectric film deposition are described by the present invention.

Brief summary of the invention

  [0009] Embodiments of the invention include a method of filling a gap with silicon oxide on a substrate. The method includes introducing an organosilicon precursor and an oxygen precursor into a deposition chamber, reacting the precursor to form a first silicon oxide layer in a gap on the substrate, and a first silicon oxide layer. Etching to reduce the carbon content in the layer. The method may also include forming a second silicon dioxide layer on the first layer and etching the second layer to reduce the carbon content in the layer. The silicon oxide layer may be annealed after the gap is filled.

  [0010] Embodiments of the present invention also include a method of forming a multilayer silicon oxide layer on a substrate. The method may include forming a plurality of silicon oxide layers on the substrate, each silicon oxide layer having a thickness of about 100 angstroms to about 200 angstroms. The layer consists of (i) introducing an organosilicon precursor and an atomic oxygen precursor into the reaction chamber, (ii) reacting the precursor to form a layer on the substrate, and (iii) etching the layer into the layer It can be formed by reducing the impurities. Thereafter, the plurality of layers can be annealed.

  [0011] Embodiments of the present invention still further include a system for performing multi-cycle silicon oxide bottom-up gap filling on a wafer substrate. The system includes a deposition chamber in which a gap-containing substrate is held, and a remote plasma generation system coupled to the deposition chamber, wherein the remote plasma generation system uses the plasma generation system to generate atomic oxygen precursors. It is good to be. The system also includes an organosilicon precursor source that is used to supply the organosilane precursor to the deposition chamber and a precursor processing system that is used to flow the atomic oxygen precursor and the silicon precursor to the deposition chamber. Should be included. The precursor processing system prevents mixing of atomic oxygen and silicon precursor before entering the deposition chamber. The system still further includes an etching system that etches the individual silicon oxide layers deposited during each cycle of multi-cycle gap filling.

  [0012] Additional embodiments and features are set forth in part in the following description, and in part will be apparent to those skilled in the art upon examination of the specification or may be learned by practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instrumentalities, combinations, or methods described in the specification.

  [0013] An understanding of the nature and advantages of the present invention is further enabled by the remaining portions of the specification and drawings, wherein like reference numerals are used throughout several drawings to refer to like elements. . In some cases, a sublabel is associated with a code, followed by a hyphen to indicate one of a plurality of similar elements. Where a reference is made to a sub-label that is not explicitly stated, it is intended to indicate all such similar elements.

FIG. 1 is a flowchart illustrating an overview of multi-cycle silicon oxide layer deposition according to an embodiment of the present invention. FIG. 2 is a flowchart illustrating a method for manufacturing a silicon oxide film according to an embodiment of the present invention. FIG. 3 is a flowchart highlighting a two-stage etching step in a method of manufacturing a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 4 is another flowchart showing a method for manufacturing a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 5A illustrates a substrate having a gap structure that is gradually filled with a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 5A illustrates a substrate having a gap structure that is gradually filled with a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 5B illustrates a substrate having a gap structure that is gradually filled with a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 5C illustrates a substrate having a gap structure that is gradually filled with a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 5D illustrates a substrate having a gap structure that is gradually filled with a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 5E illustrates a substrate having a gap structure that is gradually filled with a multilayer silicon oxide film according to an embodiment of the present invention. FIG. 6A is a longitudinal cross-sectional view illustrating a substrate processing system that can be used to form a silicon oxide layer according to an embodiment of the present invention. FIG. 6B is a simplified diagram of system monitor / controller elements of a substrate processing system in accordance with an embodiment of the present invention.

Detailed Description of the Invention

  [0021] Systems and methods for multi-layer, multi-cycle deposition of silicon oxide within and on the gap of a wafer substrate are described. Each oxide layer is thin enough (e.g., about 50 angstroms to about 300 angstroms) that the etching process can dissociate and remove impurities such as organic groups and hydroxyl groups that can adversely affect film quality and dielectric properties. ). If multiple oxide layers are deposited and etched, annealing can be performed to form the layers into a high quality, low k silicon oxide film.

  [0022] The silicon oxide layer can be formed from the reaction of highly reactive atomic oxygen with an organosilicon precursor such as OMCATS. Atomic oxygen is generated outside of the chamber in which the deposition is initially performed and remains separated from the organosilicon precursor until mixed in the chamber. The obtained silicon oxide contains a large amount of carbon and is very fluid, and becomes a deposited film that easily flows to the bottom of a narrow gap or trench. After the etching process removes at least some of the larger carbon and hydroxyl groups in the deposited film, subsequent oxide deposition flows over the first layer and etches into the next oxide layer. May be. For example, the cycle may be repeated several times until the gap or trench is filled from the bottom to the top with multiple silicon oxide layers. This multi-cycle process has also been referred to as bottom-up gap filling. Further details regarding the methods, products, and systems of the present invention will now be described.

Exemplary oxide layer formation process
[0023] FIG. 1 is a flowchart that includes steps in a method 100 of forming an oxide layer on a substrate according to an embodiment of the invention. The method 100 includes providing a gap-containing substrate in the deposition chamber 102. The substrate has a structure including gaps, trenches, etc. with a high aspect ratio of height to width of about 5: 1 or more, 7: 1 or more, 10: 1 or more, 13: 1 or more, 15: 1 or more, etc. May be.

[0024] A plurality of silicon oxide layers are then formed in the gap (and on other surfaces) of the substrate 104. Silicon oxide can be deposited by reaction of an oxygen-containing precursor and an organosilicon-containing precursor in the reaction chamber. The oxygen containing precursor may include atomic oxygen generated remotely outside the deposition chamber. Atomic oxygen is molecular oxygen (O ₂ ), ozone (O ₃ ), nitrogen-oxygen compounds (eg, NO, NO ₂ , N ₂ O, etc.), hydrogen-oxygen compounds (eg, H ₂ O, H ₂ O _2). Etc.), as well as carbon-oxygen compounds (eg, CO, CO _2, etc.), as well as other oxygen-containing precursors or precursors such as combinations of precursors.

  [0025] Dissociation of precursors that produce atomic oxygen may be performed by thermal dissociation, ultraviolet light dissociation, and / or plasma dissociation, among other methods. Plasma dissociation may include a step of impinging plasma from helium, argon, or the like in a remote plasma generation chamber and a step of introducing an oxygen precursor into the plasma to generate an atomic oxygen precursor.

  [0026] Atomic oxygen can first be introduced into the organosilicon precursor in the chamber. The organosilicon precursor may include a compound having a direct Si—C bond and / or a compound having a Si—O—C bond. Examples of organosilane silicon precursors include dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (OMTS), and octamethyl. Examples include cyclotetrasiloxane (OMCTS), tetramethyldimethyldimethoxydisilane, tetramethylcyclotetrasiloxane (TOMCATS), DMDMOS, DEMS, methyltriethoxysilane (MTES), phenyldimethylsilane, and phenylsilane.

[0027] The organosilicon precursor may be mixed with a carrier gas before or during introduction to the deposition chamber. The carrier gas may be an inert gas that does not unduly interfere with the formation of the oxide film on the substrate. Examples of carrier gases include helium, neon, argon, hydrogen (H ₂ ), among other gases.

  [0028] In an embodiment of method 100, atomic oxygen and organosilicon precursor are not mixed before being introduced into the deposition chamber. The precursor may enter the chamber through another spatially separated one distributed around the reaction chamber. For example, the atomic oxygen precursor may enter from an inlet (or multiple inlets) located directly above the substrate at the top of the chamber. From the inlet, a flow of oxygen precursor is sent in a direction perpendicular to the deposition surface of the substrate. On the one hand, the silicon precursor may enter from one or more inlets around the side of the deposition chamber. From the inlet, the silicon precursor flow should be directed in a direction substantially parallel to the deposition surface.

  [0029] Embodiments further include sending atomic oxygen and silicon precursor through another port of the multi-port showerhead. For example, a showerhead located over a substrate can include a pattern of openings where precursors enter the deposition chamber. The first subset of openings can be supplied by atomic oxygen precursors and the second subset of openings is supplied by silicon precursors. Precursors traveling through different sets of openings can be fluidly separated from one another until they exit into the deposition chamber. Details on the type and design of the precursor processing apparatus are further described in a co-assigned US provisional application with agent reference number A11162 / T72710 by Lubomirsky named PROCESSCHAMBER FORDELECTRIC GAPFILL filed on the same day as this application, This entire disclosure is incorporated herein for all purposes.

  [0030] As the atomic oxygen and the silicon precursor react in the deposition chamber, a silicon oxide layer is formed on the deposition surface of the substrate. The initial oxide layer has excellent fluidity and can move rapidly to the bottom of the gap in the structure present at the deposition surface.

  [0031] After each oxide layer is deposited, each etching step can be performed on the layer to remove impurities. This may include dissociating larger organic groups into smaller carbon-containing molecules and dissociating at least some of the Si—OH bonds to form water and silicon oxide.

  [0032] Following the deposition and etching of the plurality of silicon oxide layers, the moisture can be further drained and annealed such that the layers are dense and high quality oxide films. Embodiments include the step of depositing and etching all individual layers of the silicon oxide layer followed by annealing. Embodiments may also include an intermediate anneal after one or more of the layers have been performed, but before the final anneal of all layers. For example, an intermediate anneal may be performed after all 2, 3, 4, 5, etc. layers have been deposited, followed by a final anneal of all layers.

[0033] Referring to FIG. 2, a flowchart illustrating a method 200 for manufacturing a multilayer silicon oxide layer according to an embodiment of the present invention is shown. Method 200 may include introducing a precursor into a deposition chamber containing substrate 202. As described above, the precursor may include an atomic oxygen precursor and an organosilicon precursor. Atomic oxygen is, for example, 4000 to 6000 watts (eg, 5500 watts) of RF in both gas flows, argon gas flowing at about 900-1800 sccm and molecular oxygen (O ₂ ) flowing at, for example, about 600 to about 1200 sccm. It may be generated in a remote high density plasma generator that supplies power.

[0034] The organosilicon precursor can be introduced into the deposition chamber by mixing with an organosilicon compound (gas or liquid) and a carrier gas such as helium or molecular hydrogen (H ₂ ). For example, helium is blown into a liquid organosilicon precursor such as octamethylcyclotetrasiloxane (OMCTS) at room temperature at a flow rate of about 600 to about 2400 sccm to obtain a flow of OMCTS into the chamber at a flow rate of about 800 to about 1600 mgm. be able to.

  [0035] The precursors react with each other in the chamber to form a first oxide layer on the substrate 204. The total pressure in the chamber during oxide layer deposition may be, for example, from about 0.5 Torr to about 6 Torr. A higher total pressure (eg, 1.3 Torr) can deposit an oxide film with a more fluid quality, and a lower pressure (eg, 0.5 Torr) may result in a more conformal oxide. A layer can be deposited. Because atomic oxygen is very reactive, the deposition temperature in the reaction chamber may be relatively low (eg, about 100 ° C. or less). The oxide deposition rate may range from about 125 angstroms / minute to about 2 μm / minute (eg, about 500 angstroms / minute to about 300 angstroms / minute; about 1500 angstroms / minute, etc.).

  [0036] After the first oxide layer is formed, the flow of precursor to the chamber may be stopped and the first oxide layer may be etched 206. The etching step can be used to dissociate and remove impurities in the layer and to planarize the layer. As described in the description of FIG. 3 below, the etching process may include a single etching step or multiple etching steps.

  [0037] After etching the first layer, the precursor is reintroduced into the deposition chamber 208 and reacts to form a second oxide layer on the substrate 210. The second oxide layer may be formed under the same reaction conditions as the first layer, or may be formed under different conditions (eg, chamber pressure, temperature, organosilicon precursor, etc.).

  [0038] After the second layer is formed, an etch 212 may be performed to reduce impurity levels and / or planarize the layer. The second layer may be etched using the same process used to etch the first layer, or a different process (eg, different number of etch steps, different etch precursors, different power levels, etc.). May be used to etch.

  [0039] After formation and etching of the second silicon dioxide layer (and any additional oxide layers), the oxide layer may be annealed 214 to form a uniform and high quality silicon oxide gap fill. The last gap filling dielectric constant (ie, k value) is less than 4.0 (eg, less than 3.5, less than 3.0, etc.) and the wet etch rate ratio (WERR) is less than 2: 1 (eg, About 1.8: 1 to 1.4: 1). The gap fill should be uniform throughout the fill volume, and in any case contains little voids or seams.

  [0040] FIG. 3 shows a flowchart highlighting a two-step etching step in a method 300 for fabricating a multilayer silicon oxide film according to an embodiment of the present invention. Method 300 includes preparing a substrate in reaction chamber 302 and introducing precursors (eg, oxygen and silicon precursors) into reaction chamber 304. The precursor then reacts to form a silicon oxide layer on the substrate 306 and then undergoes a two-step etch.

[0041] The two-stage etch begins by performing a first etch on the oxide layer 308. This first etch may include using a lower density plasma to dissociate larger organic molecules and remove at least a portion of the carbon in the layer. This lower density plasma etch may include using an RPS system to generate an Ar / O ₂ plasma that etches the oxide layer. Etching conditions may include, for example, impinging a plasma from 1600 sccm of O ₂ and 400 sccm of argon with a power of about 5500 watts or introducing it into the deposition chamber at a pressure of about 760 millitorr. This plasma etching can dissociate larger carbon groups and remove carbon impurities from the oxide layer.

  [0042] After the first etch, a second etch of the oxide layer is performed 310 with a higher plasma density to remove at least some of the hydroxyl groups in the layer. This higher density plasma etch may include exposing the layer to a plasma formed from the dissociation of a molecular oxygen (eg, 600 sccm) flow at a higher RF field (eg, 6000 watts). An oxygen plasma can be introduced into the deposition chamber, for example, at a pressure of 8 millitorr, and can react with —OH groups in the oxide layer to form silicon dioxide and water.

  [0043] The deposition and etch cycles can be repeated, and the next oxide layer 312 is formed on top of the previous layer. Thereafter, the deposited and etched oxide layer is accumulated until a predetermined number of layers and / or thickness is reached, and the plurality of layers are annealed 314. Annealing may be performed in a single step or multiple steps. Single step annealing, for example, heats multiple layers to about 300 ° C. to about 1000 ° C. (eg, about 600 ° C. to about 900 ° C.) in a substantially dry atmosphere (eg, dry nitrogen, helium, argon, etc.). It is good to be done. Annealing removes moisture from the deposited layer and further converts Si—OH to silicon oxide.

[0044] Multi-step annealing may include a two-step anneal in which the layer is first subjected to a wet anneal step, eg, heating the layer to about 700 ° C. in the presence of steam. This may be followed by a dry annealing step in which the layer is heated to a higher temperature (eg, about 900 ° C.) in an atmosphere that is substantially free of moisture (eg, dry N ₂ ). The first wet anneal can help further hydrolyze the Si—C bonds with Si—OH bonds, and the dry anneal converts the Si—OH to silicon oxide bonds and drains moisture from the layer.

  [0045] In addition to wet and dry thermal annealing, other annealing techniques (alone or in combination) can be used to anneal multiple oxide layers. These include, among others, vapor annealing, plasma annealing, ultraviolet light annealing, electron beam annealing, and / or microwave annealing.

  [0046] Referring now to FIG. 4, another flowchart illustrating a method 400 of fabricating a multilayer silicon oxide film according to an embodiment of the present invention is shown. Method 400 includes providing a substrate in deposition chamber 402 and introducing precursors (eg, atomic oxygen and organosilicon precursor) into chamber 404. The precursors can react to form a silicon oxide layer on the substrate 406, after which the oxide layer can be etched 408.

  [0047] At this point, a test can be made 410 to determine if the accumulated thickness of the deposited oxide layer has reached a set point. If the set thickness level of the total oxide film is reached, the deposition and etch cycle may be terminated and the film can be annealed 412. However, if the thickness level is not met, other oxide deposition and etching cycles can be performed to add at least one or more layers to the oxide film.

  [0048] The determination of whether the oxide film has reached a predetermined thickness can be made by measuring the thickness of the deposited and etched layers, or the number of layers required to achieve the desired film thickness. It may be done by calculation. For example, if each deposited and etched layer is 100 Å thick and the desired film thickness is 1.2 μm, twelve deposition and etching cycles must be performed to form the film. The thickness of each deposited layer can be set by controlling parameters that affect the oxide deposition rate, such as, among other things, the type and flow rate of the reaction precursor, the total pressure in the deposition chamber, and the temperature. As noted above, typical deposition rates for oxide layers are from about 500 angstroms / minute to about 3000 angstroms / minute (eg, about 1500 angstroms / minute).

  [0049] FIGS. 5A-5F illustrate a substrate with a gap structure that is progressively filled with a multilayer silicon oxide film using an embodiment of a multi-cycle deposited etch oxide layer formation process. FIG. 5A is a diagram illustrating the substrate 502 in which the gap 504 is formed. It is understood that the gap 504 shown in FIGS. 5A-5F is drawn with a relatively low aspect ratio to more clearly show the progress of the oxide fill layer. Embodiments of this gap filling method have aspect ratios of 5: 1, 6: 1, 7: 1, 8: 1, 9: 1, 10: 1, 11: 1, 12: 1, 13: 1, 14 It may include deposition without voids or seams in gaps of 1: 1, 15: 1 or more.

  [0050] FIG. 5B shows a first oxide layer 506a deposited in the gap 504. FIG. The layered silicon oxide has good fluidity and allows the film to move rapidly to the bottom of the gap 504. Accordingly, the thickness of the oxide deposited at the bottom of the gap 504 may be greater than the thickness of the oxide along the gap sidewall.

  [0051] FIGS. 5C and 5D are diagrams showing additional oxide layers 506b, 506c, etc. deposited on the previously deposited and etched layers in gap 504. FIG. These additional layers can be formed bottom up in the gap 504 until the desired oxide film thickness level is reached (eg, the top of the gap 504).

  [0052] Once the last plurality of oxide layers have been deposited and etched, annealing can be performed to form the layers into a uniform film 508 as shown in FIG. 5E. The film can be planarized, for example, by plasma etching or CMP to remove the deposited material formed on top of the gap 504. FIG. 5F illustrates the remaining silicon oxide gap fill 510 with high film quality and dielectric properties with little void or seam in any case.

Exemplary substrate processing system
[0053] Deposition systems in which embodiments of the present invention can be implemented are high density plasma chemical vapor deposition (HDP-CVD) systems, plasma enhanced chemical vapor deposition (PECVD), among other types of systems. Sub-atmospheric chemical vapor deposition (SACVD) systems, thermal chemical vapor deposition systems may be included. Specific examples of CVD systems in which embodiments of the present invention can be implemented include CENTURAULTIMA ^™ HDP-CVD chamber / system, PRODUCER ^™ PECVD chamber / system available from Applied Materials, Santa Clara, California.

  [0054] A suitable single substrate processing system that can be modified to use embodiments of the present invention is shown and described in co-assigned US Pat. Nos. 6,387,207, 6,830,624, These disclosures are hereby incorporated by reference in their entirety. FIG. 6A is a longitudinal cross-sectional view of a CVD system 10 having a vacuum chamber or processing chamber 15 that includes a chamber wall 15a and a chamber lid assembly 15b.

  [0055] The CVD system 10 contains a gas distribution manifold 11 for dispersing process gas to a substrate (not shown) on a heated pedestal 12 in the middle of the process chamber 15. The gas distribution manifold 11 may be formed from a conductive material for use as an electrode for forming a capacitive plasma. During processing, the substrate (eg, semiconductor wafer) is located on the flat (or slightly convex) surface 12a of the pedestal 12. The pedestal 12 is controllable between a lower load / release position (shown in FIG. 6A) and an upper processing position (shown by the dashed line 14 in FIG. 6A), which is closely adjacent to the manifold 11. Can move. A center board (not shown) includes sensors that provide information on the position of the wafer.

  [0056] Deposition and carrier gases are introduced into the chamber 15 through the through holes 13b of the conventional flat circular gas distribution faceplate 13a. More specifically, the deposition process gas flows through the injection manifold 11, through the conventional through blocker plate 42, and then through the holes 13b in the gas distribution faceplate 13a to the chamber.

  [0057] Prior to reaching the manifold 11, the deposition gas and carrier gas flow from the gas source 7 through the gas supply line 8 into the mixing system 9, where they are mixed and then sent to the manifold 11. In general, the supply line for each process gas includes (i) a safety shut-off valve (not shown) that can be used to automatically or manually shut off the process gas flow to the chamber, and (ii) a supply line. A mass flow controller (not shown) that measures gas flow through is included. If toxic gases are used in the process, several safety shut-off valves are located on each gas supply line of conventional construction.

  [0058] The deposition process performed in the CVD system 10 can be either a thermal process or a plasma enhanced process. In a plasma enhanced process, the RF power supply 44 applies power between the gas distribution plate 13a and the pedestal 12 to excite the process gas mixture and form a plasma in the cylindrical region between the face plate 13a and the pedestal 12. To do. (This region is referred to herein as the “reaction region”). The plasma components react to deposit the desired film on the surface of the semiconductor wafer supported by the pedestal 12. The RF power supply 44 typically provides power at a high RF frequency (RF1) of 13.56 MHz and a low RF frequency (RF2) of 360 KHz to facilitate decomposition of reactive species introduced into the vacuum chamber 15. It is a mixed frequency RF power source supplied for the purpose. In a thermal process, no RF power source 44 is used, and the process gas mixture reacts thermally and on the surface of a semiconductor wafer supported on a pedestal 12 that is resistively heated to provide thermal energy for the reaction. A desired film is deposited.

  [0059] During the plasma enhanced deposition process, the plasma heats the entire process chamber 10, including the walls of the chamber body 15 a surrounding the exhaust passage 23 and the isolation valve 24. During the thermal deposition process or if no plasma is generated during the thermal deposition process, hot liquid is circulated through the wall 15a of the process chamber 15 to maintain the chamber at an elevated temperature. The remaining passages in the chamber wall 15a are not shown. The fluid used to heat the chamber wall 15a includes typical fluid types, ie water based ethylene glycol or oil based heat transfer fluid. This heating (referred to as heating by “heat exchange”) beneficially reduces or eliminates the condensation of unwanted reaction products and condenses on the volatile products of the process gas and the walls of the cooling vacuum passages and reduces gas flow. Improves removal of other contaminants that contaminate the process when moved to the processing chamber for a period of time.

  [0060] The remainder of the gas mixture that is not deposited in the layer containing reaction by-products is evacuated from the chamber 15 by a vacuum pump (not shown). Specifically, the gas is exhausted to an annular exhaust plenum 17 through an annular slotted orifice 16 surrounding the reaction region. The annular slot 16 and plenum 17 are defined by a gap between the top of the chamber cylindrical sidewall 15a (including the upper dielectric lining 19 on the wall) and the bottom surface of the circular chamber lid 20. The 360 degree circular symmetry and uniformity of the slot orifice 16 and plenum 17 is important to achieve a uniform flow of process gas over the wafer to deposit a uniform film on the wafer.

  [0061] From the exhaust plenum 17, the gas passes under the expansion region 21 next to the exhaust plenum 17, past a viewing port (not shown), through a downwardly extending gas passage 23, and a vacuum shut-off valve 24. Passes through the foreline (not shown) to the outlet 25 which connects to the external vacuum pump (not shown) through the body (which is built into the lower chamber wall 15a).

  [0062] The wafer support platter of the pedestal 12 is resistively heated using a built-in single-loop built-in heater element configured to make two full turns in the form of parallel concentric circles. The exterior of the heater element continues adjacent to the periphery of the support platter and the interior continues to a concentric path with a small radius. The wiring of the heater element passes through the stem of the pedestal 12.

  [0063] Typically, some or all chamber linings, gas injection manifold faceplates, and various other reactor hardware are made of materials such as aluminum, anodized aluminum or ceramic. An example of such a CVD apparatus is described in co-assigned US Pat. No. 5,558,717 entitled “CVD Processing Chamber” issued to Zhao et al., The disclosure of which is incorporated herein in its entirety. ing.

  [0064] Lift mechanism and motor 32 (FIG. 6A) so that wafers are transferred into and out of the body of chamber 15 by robot blades (not shown) through insertion / removal openings 26 on the side of chamber 10. ) Moves the heater pedestal assembly 12 and its wafer lift pins 12b up and down. The motor 32 moves the pedestal 12 up and down between the processing position 14 and the lower wafer loading position. The controller, gas distribution system, throttle valve, RF power supply 44, chamber and substrate heating system connected to the motor, valves or supply line 8 are all controlled by the controller system on the control line 36, only partly shown. The Controller 34 relies on feedback from optical sensors to determine the position of mobile mechanical assemblies such as slot valves and susceptors that are moved by appropriate motors under the control of controller 34.

  [0065] In an exemplary embodiment, the system controller includes a hard disk drive (memory 38), a floppy disk drive, and a processor 37. The processor contains a single board computer (SBC), analog and digital input / output boards, interface boards, and stepper motor controller boards. The various parts of CVD system 10 apply to the VersaModular European (VME) standard that defines board, card gauge, connector dimensions and types. The VME standard also defines a bus structure with a 16-bit data bus and a 24-bit address bus.

  [0066] The system controller 34 controls all of the activities of the CVD machine. The system controller executes system control software, which is a computer program stored in a computer readable medium such as memory 38. Preferably, the memory 38 is a hard disk drive, but the memory 38 can also be other types of memory. The computer program includes a set of instructions for determining timing, gas mixture, chamber pressure, chamber temperature, RF power level, susceptor position, and other parameters of the specific process. For example, other computer programs stored on other memory devices including a floppy disk or other suitable drive may also be used to operate the controller 34.

  [0067] The method of depositing a film on the substrate or the method of cleaning the chamber 15 may be implemented using a computer program product executed by the controller 34. The computer program code can be written in any conventional computer readable programming language: for example, 68000 assembly language, C, C ++, Pascal, Fortran etc. Appropriate program code is entered into a single file or multiple files using a conventional text editor and stored or embodied in a computer usable medium, such as a computer memory system. If the entered code text is in a high level language, the code is compiled and the resulting compiler code is then linked with the precompiled Microsoft Windows® library object code. To execute the linked and compiled object code, the system user activates the object code and causes the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program.

  [0068] The interface between the user and the controller 34 is a CRT monitor 50a and light pen 50b, shown in FIG. 6B, which is a simplified diagram of a system monitor and CVD system 10 in a substrate processing system that may include one or more chambers. Via. In the preferred embodiment, two monitors 50a are used, one attached to the operator's clean room wall and the other behind the wall for the technician. The monitor 50a displays the same information simultaneously, but only a single light pen 50b is possible. The light sensor at the tip of the light pen 50b detects the light emitted by the CRT display. To select a specific screen or function, the operator touches a designated area of the display screen and presses the button on the pen 50b. The touched area changes to the highlighted color or a new menu or screen is displayed, confirming communication between the light pen and the display screen. Other devices such as a keyboard, mouse, or other pointing device or communication device can be used in place of or in addition to the light pen 50b to allow the user to communicate with the controller 34.

FIG. 6A shows a remote plasma generator 60 attached to the lid assembly 15 b of the process chamber 15 that includes the gas distribution faceplate 13 a and the gas distribution manifold 11. As best seen in FIG. 6A, a remote plasma generator 60 is mounted on the lid assembly 15b by a mounting adapter 64. The adapter 64 is typically manufactured from metal. The mixing device 70 is coupled upstream of the gas distribution manifold 11 (FIG. 6A). The mixing device 70 includes a mixing insert 72 disposed inside a mixing block slot 74 for the mixing process gas. The ceramic isolator 66 is disposed between the mounting adapter 64 and the mixing device 70 (FIG. 6A). The ceramic isolator 66 may be manufactured from a ceramic material such as Al ₂ O ₃ (purity 99%), Teflon (registered trademark), or the like. When attached, the mixing device 70 and the ceramic isolator may form part of the lid assembly 15b. The isolator 66 insulates the metal adapter 64 from the mixing device 70 and the gas distribution manifold 11 to minimize the potential of the second plasma that forms in the lid assembly 15b, described in further detail below. Three-way valve 77 controls the flow of process gas to process chamber 15 either directly or through remote plasma generator 60.

[0070] The remote plasma generator 60 is preferably a small built-in unit that is conveniently attached to the lid assembly 15b and can be easily attached to an existing chamber later without cost or time-consuming changes. One suitable unit is an ASTRON® generator available from Applied Science and Technology, Inc. of Woburn, Massachusetts. The ASTRON® generator uses a low electric field toroidal plasma to dissociate the process gas. In one example, the plasma dissociates a process gas that includes a fluorine-containing gas such as NF ₃ and a carrier gas such as argon to produce free fluorine that is used to clean the film deposit in the process chamber 15. .

  [0071] While several embodiments have been described, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. In addition, many well known processes and elements have not been described in order to avoid unnecessarily obscuring the present invention. Accordingly, the above description should not be taken as limiting the scope of the invention.

  [0072] When a range of values is indicated, it is understood that each intervening value is disclosed in detail up to 1/10 of the lower limit unit between the upper and lower limits of the range, unless specifically affected otherwise. The Each smaller range between any stated value or stated intervening value of the range and every other stated value or intervening value of that range is included. The upper and lower limits of these smaller ranges may be independently included or excluded from the range, subject to any specifically excluded limits in the stated range, either, neither or both Each range including is also included in the scope of the present invention. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

  [0073] As used herein and in the appended claims, the singular forms include the plural objects unless the context clearly dictates otherwise. Thus, for example, reference to “process” also applies to a plurality of such processes, and reference to “precursor” refers to one or more precursors and their equivalents known to those skilled in the art. Is included.

  [0074] Also, as used in this specification and the claims below, the words "comprising" and "including" specify the presence of a described feature, integer, component, or step, The presence or addition of these other features, integers, ingredients, steps, actions or groups is not excluded.

  DESCRIPTION OF SYMBOLS 10 ... CVD system, 11 ... Gas distribution manifold, 12 ... Pedestal, 12b ... Wafer lift pin, 13a ... Face plate, 14 ... Processing position, 15 ... Process chamber, 15a ... Chamber wall, 15b ... Chamber lid assembly, 16 ... Annular slot Shape orifice, 17 ... plenum, 19 ... dielectric lining, 20 ... circular chamber lid, 21 ... lateral expansion, 23 ... exhaust passage, 24 ... shutoff valve, 25 ... discharge port, 26 ... insertion / extraction opening, 32 ... Motor, 50a ... Monitor, 50b ... Pen, 60 ... Remote plasma generator, 64 ... Mounting adapter, 66 ... Isolator, 70 ... Mixing device, 72 ... Mixing insert.

Claims (29)

A method of filling a gap on a substrate with silicon oxide:
Introducing an organosilicon precursor and an oxygen precursor into the deposition chamber;
Reacting the precursor to form a first silicon oxide layer in the gap on the substrate;
Etching the first silicon oxide layer to reduce the carbon content in the layer;
Forming a silicon dioxide layer on the first layer and etching the second layer to reduce the carbon content in the layer;
Annealing the silicon oxide layer after filling the gap;
Only including,
Etching the first silicon oxide layer and the second silicon dioxide layer comprises:
Exposing the layer to a first plasma having a first density, wherein the first plasma dissociates larger carbon molecules in the layer;
Exposing the layer to a second plasma having a second density greater than the first density, wherein the second plasma dissociates silicon oxide bonds in the layer;
Including the method.   The method of claim 1, wherein the oxygen precursor comprises atomic oxygen generated outside the deposition chamber. The atomic oxygen is
Generating a plasma from a gas mixture containing argon;
Introducing an oxygen precursor into the plasma, where the oxygen precursor dissociates to form the atomic oxygen;
The method according to claim 2, wherein:   4. The method of claim 3, wherein the oxygen precursor is selected from the group consisting of molecular oxygen, ozone, and nitrogen dioxide. The atomic oxygen is
Introducing an oxygen precursor into the photodissociation chamber;
Exposing the oxygen precursor to ultraviolet light, wherein the ultraviolet light dissociates the oxygen precursor to form atomic oxygen;
The method of claim 2, formed by:   The method of claim 2, wherein the organosilicon precursor and the atomic oxygen are not mixed until introduced into the deposition chamber.   The organic silicon precursor is dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (OMTS), octamethylcyclotetrasiloxane (OMCTS). ), Tetramethylcyclotetrasiloxane (TOMCATS), DMDMOS, DEMS, methyltriethoxysilane (MTES), phenyldimethylsilane, or phenylsilane.   The method of claim 1, wherein the first silicon oxide layer and the second silicon dioxide layer each have a thickness of about 100 angstroms to about 200 angstroms.   The method of claim 1, wherein annealing the silicon oxide layer comprises annealing in a dry non-reactive gas at a temperature of about 800 ° C. or higher. The method of claim 9 , wherein the non-reactive gas is nitrogen (N ₂ ) and the temperature is 900 ° C.   The method of claim 1, wherein the method includes forming additional silicon oxide layers on the first layer and the second layer, each additional silicon oxide layer having a thickness of about 50 angstroms to about 500 angstroms. The method described. The method of claim 11 , wherein the additional silicon oxide layer is etched in the same manner as the first silicon oxide layer and the second silicon dioxide layer. The method of claim 11 , wherein the total thickness of the silicon oxide layer is from about 500 angstroms to about 10,000 angstroms.   The method of claim 1, wherein the annealed silicon oxide layer has a wet etch rate ratio (WERR) of about 2: 1 or less.   The method of claim 1, wherein the annealed silicon oxide layer has a wet etch rate ratio (WERR) of about 1.8: 1 to about 1.4: 1.   The method of claim 1, wherein the annealed silicon oxide layer has a k value of about 4.0 or less.   The method of claim 1, wherein the gap height to width aspect ratio is about 5: 1 or greater.   The method of claim 1, wherein the gap height to width aspect ratio is about 13: 1 or greater. A method of forming a multilayer silicon oxide film on a substrate comprising:
Forming a plurality of silicon oxide layers on the substrate, each silicon oxide layer having a thickness of about 100 angstroms to about 200 angstroms;
(I) introducing an organosilicon precursor and an atomic oxygen precursor into the reaction chamber;
(Ii) reacting the precursor to form the layer on the substrate;
(Iii) etching the layer to reduce impurities in the layer;
Formed by said step;
Annealing the plurality of layers;
Only including,
Etching the layer comprises:
Exposing the layer to a first plasma having a first density, wherein the first plasma dissociates larger carbon molecules in the layer;
Exposing the layer to a second plasma having a second density greater than the first density, wherein the second plasma dissociates silicon hydroxide bonds in the layer;
Including the method. 20. The method of claim 19 , wherein the atomic oxygen precursor is generated outside the deposition chamber and is not mixed until the organosilicon precursor and the atomic oxygen precursor are introduced into the reaction chamber. 20. The method of claim 19 , wherein annealing the plurality of layers comprises thermal annealing, steam annealing, plasma annealing, ultraviolet light annealing, e-beam annealing, or microwave annealing. Annealing the plurality of layers comprises:
Heating the substrate in the presence of steam at a first annealing temperature;
Heating the substrate in dry nitrogen at a second annealing temperature;
20. The method of claim 19 , comprising: 23. The method of claim 22 , wherein the first anneal temperature is about 650 ° C and the second anneal temperature is about 900 ° C. The method of claim 19 , wherein each of the plurality of layers is formed at a rate of about 125 angstroms / minute to about 2 μm / minute. 20. The method of claim 19 , wherein each of the layers is etched within about 3 minutes. 20. The method of claim 19, wherein the plurality of layers are annealed within about 30 minutes. The method of claim 19 , wherein the plurality of layers have a wet etch rate ratio (WERR) of about 1.8: 1 to about 1.4: 1. The method of claim 19 , wherein the k value of the plurality of layers is about 4.0 or less. The method of claim 19 , wherein the thickness of the multilayer silicon oxide film is from about 1000 angstroms to about 3000 angstroms.

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