TW200807558A - A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide - Google Patents

A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide Download PDF

Info

Publication number
TW200807558A
TW200807558A TW096119169A TW96119169A TW200807558A TW 200807558 A TW200807558 A TW 200807558A TW 096119169 A TW096119169 A TW 096119169A TW 96119169 A TW96119169 A TW 96119169A TW 200807558 A TW200807558 A TW 200807558A
Authority
TW
Taiwan
Prior art keywords
layer
precursor
annealing
plasma
layers
Prior art date
Application number
TW096119169A
Other languages
Chinese (zh)
Other versions
TWI366876B (en
Inventor
Xiaolin Chen
Srinivas D Nemani
Shankar Venkataraman
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/753,968 external-priority patent/US7902080B2/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW200807558A publication Critical patent/TW200807558A/en
Application granted granted Critical
Publication of TWI366876B publication Critical patent/TWI366876B/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02277—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition the reactions being activated by other means than plasma or thermal, e.g. photo-CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02359—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the surface groups of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon context in the second layer. The silicon oxide layers are annealed after the gap is filled.

Description

200807558 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種提高二氧化矽膜品質的方法 確地’本發明係關於一種新穎沉積-電漿硬化循環 法0 【先前技術】 隨著積體電路上的元件密度持續地增加，元件 間的尺寸與距離則持續減小。而構造的間隙寬度和 間的溝槽寬度變小則提高這些結構中高度對寬度 (即，深寬比「aspect ratio」）。換言之，積體電路 持續微型化縮減這些元件之中與之·間的水平寬度之 於縮減他們垂直高度的速度。 雖然製造持續增加深寬比之元件構造的能力讓 造（例如電晶體、電容器、二極體等等）設置在半導 基板的相同表面區域上，但這亦產生製造問題。這 的其中之一係難以在充填處理過程中完全填滿這些 的間隙與溝槽而不產生空隙或裂缝。以例如二氧化 電材質來充填間隙與溝槽，對使鄰近的元件構造彼 來說是必須的。假若讓間隙處於空缺狀癌’將會有 電子雜訊與電流滲漏讓元件無法正常運轉（或完全 轉）。 當間隙寬度較大(也就是深寬比較小）時，相對 快速沉積的介電材質來充填間隙。沉積材f會覆蓋 ，更明 I理方 構造之 構造之 的比值 元件的 速度快 更多構 體晶片 些問題 構造内 矽的介 此絕緣 太多的 無法運 谷易以 間隙的 200807558 側邊與底部，且由底部持續向上充填直到裂隙或溝槽被完 全填滿為止。然而隨著深寬比的増加，變得更難以充填^ 窄型溝槽且不具有充填容積中出現空隙或裂缝的阻礙。200807558 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method for improving the quality of a cerium oxide film. The present invention relates to a novel deposition-plasma hardening cycle method. [Prior Art] The density of components on the body circuit continues to increase, and the size and distance between the components continue to decrease. The gap width of the structure and the width of the trench between them increase the height-to-width (i.e., the aspect ratio) of these structures. In other words, the integrated circuit continues to miniaturize and reduce the horizontal width between these elements to reduce their vertical height. While the ability to fabricate components that continue to increase the aspect ratio allows fabrication (e.g., transistors, capacitors, diodes, etc.) to be placed over the same surface area of the semiconductor substrate, this also creates manufacturing problems. One of these is that it is difficult to completely fill these gaps and grooves during the filling process without creating voids or cracks. Filling the gaps and trenches with, for example, a oxidizing material is necessary to structure adjacent components. If the gap is in a vacant state, there will be electronic noise and current leakage that will prevent the component from functioning properly (or fully). When the gap width is large (i.e., the depth is relatively small), a relatively fast deposited dielectric material fills the gap. The deposition material f will cover, and the ratio of the component of the structure of the structure is faster. The structure of the wafer is faster. The problem of the structure of the wafer is that the insulation is too much, and the insulation is too much. And continue to fill upward from the bottom until the crack or groove is completely filled. However, as the aspect ratio increases, it becomes more difficult to fill the narrow groove and does not have the hindrance of voids or cracks in the filling volume.

介電層中的空隙與裂縫導致半導體元件製造上與製成 元件中均產生問題。空隙與裂缝隨機形成於介電層中且具 有無法預期的尺寸、形狀、位置與整體密度。這導致該岸 之沉積後處理（諸如，均勻的蝕刻、研磨與退火等）的無法 預期與不一致性。製成元件中的空隙與裂缝亦對元件構、生 中的間隙與溝槽等介電特性產生變化。由於元件組成之ς 與之間的電子干擾、電荷滲漏（eharge leakage)甚至短路 (shorting) ’會導致不穩定且較差的元件效能。 技術已發展到可在沉積介電材質於高深寬比值構驾 時，減少空隙與裂缝的形成，這些技術包括減缓介電材隻 的沉積速率’因此介雷絲暂仅枝_ 电材質保持更高程度的同开 (conformal)於溝槽的侧壁盥底邱 - 土興魇σΡ 更咼程度的同形沉積？ 減少下述實情的發生，沉藉姑暂古：巷祕^ … 心槓材質在溝槽的頂部或中部向」 ，增進最終封起空隙的頂部。缺而尤去从θ .只邠。然而不幸的是，減緩沉積逮 意味著增加沉積時間，而這降低處理效率與生產速率'。The voids and cracks in the dielectric layer cause problems in both the fabrication of the semiconductor device and the fabrication of the device. The voids and cracks are randomly formed in the dielectric layer and have an unexpected size, shape, position, and overall density. This leads to unpredictable and inconsistent post-deposition treatments (such as uniform etching, grinding and annealing, etc.) on the shore. The voids and cracks in the fabricated component also change the dielectric properties of the component structure, the gaps and the trenches in the growth. Electronic interference, eharge leakage, and even shorting between component components can result in unstable and poor component performance. The technology has been developed to reduce the formation of voids and cracks when depositing dielectric materials at high aspect ratios. These techniques include slowing down the deposition rate of dielectric materials only, so the dielectric filaments are only temporarily branched. A high degree of conformal on the side wall of the trench, Qiu Qiu, Tu Xing, 魇 Ρ, a more uniform degree of homomorphic deposition? Reduce the occurrence of the following facts, Shen borrowed a temporary ancient: the lane secret ^ ... the bar material in the top or middle of the groove, to enhance the top of the final sealed gap. Lack and go from θ. Unfortunately, slowing down sedimentation means increasing deposition time, which reduces processing efficiency and production rate.

另-抑制空隙形成的技術為提高沉積之介電材質的、 動性。更具流動性的材質可更快地充填空隙與裂缝，且: 免其本身變為充填容積中的永久缺陷。提高二氧切介$ 材質的流動性通常包括，加入水蒸氣或過氧化物(例如過i 化氫「Η2。2」）至用來形成氡化層的前趨物混合物中。水; 氣產生更多沉積膜中的矽醇（si_0H)鍵結，此鍵結給予該I 200807558 膜兩流動性。然而不幸的是，在二氧化矽沉積時提高其潮 濕度亦不利地影響沉積膜的特性，該特性包括其密度（例 两濕式钱刻速率比值「wet etch rate ratio，WERR」） 與介電特性（例如，高k值）。 因此’仍需要可沉積無空隙與無裂缝的介電膜進入間 @、溝槽與其它具有高深寬比值的元件構造中之介電沉積 系統與處理方法。同時仍需要可用高沉積速率與流動特性In addition, the technique for suppressing the formation of voids is to improve the mobility of the deposited dielectric material. More fluid materials fill voids and cracks faster, and: Avoid becoming a permanent defect in the fill volume. Increasing the fluidity of the dioxosite material typically involves the addition of water vapor or a peroxide (e.g., hydrogen peroxide "Η2. 2") to the precursor mixture used to form the deuterated layer. Water; gas produces more sterol (si_0H) bonds in the deposited film, which bond gives the I 200807558 membrane two fluidity. However, unfortunately, increasing the humidity during the deposition of cerium oxide adversely affects the properties of the deposited film, including its density (eg, wet etch rate ratio (WERR)) and dielectric. Characteristics (for example, high k values). Therefore, there is still a need for a dielectric deposition system and a processing method in which a dielectric film having no voids and no cracks can be deposited, a trench, and other device structures having a high aspect ratio. At the same time, high deposition rates and flow characteristics are still needed.

來/儿積介電材質的系統與處理方法（不會不利地影響完成 充填的品質）。藉由本發明呈現這些與其他介電膜沉積的態 樣… 【發明内容】 本發明之實施例包括以二氧化矽克填基板上間隙的方 法。這些方法包括下列步驟：將一有機矽前趨物與一氧前 趨物引進一沉積腔；使這些前趨物反應以形成一第一二氧 化發層於基板上的間隙中；然後蝕刻該第—二氧化發層好 減少該層中的碳含量。這些方法亦包括形成一第二二氧化 矽層於該第一層上，然後蝕刻談第二層以減少該層中的碳 含量。間隙被填滿後，退火處理該些二氧北考層。 本發明之實施例亦包括形成多層式二氧化砍膜於一基 板上的方法。這些方法包括形成多個二氡化矽層於基板上 的步驟，而各個二氧化矽層的厚度約10〇A至約2〇〇A。這 些層由下列步驟形成：⑴將一有機矽前趨物與一氧原子前 趨物導入一反應腔，（Η)使該些前趨物反應以形成該層於美 200807558 板上以及（1U)蝕刻該層以減少該層中的 ^ 火處理該多個層。 、雜質。接著以退 本發明之實施例 化發由底部向上充埴=包括執行—多循環式以二氧 ]门上充填晶圓基板上之間金 包括一沉積腔，复中固拄#人 μ的糸統。這些系統 ，、中固持者含間隙基板 沉積腔的遠端電漿產 从及一耦接至該 衣屋生系統，該電漿姦从/ 氧原子前趨物。铲此会姑系統係用來產生 、卿廷些糸統亦包括一 來提供一 ：# it π ^ 夕碉趨物源，其用 术扠供有機矽前趨物給該沉 統，其用來引導早兄4 、 乂及―前趨物處理系 氧原子刚趨物流與矽前趨推 ^ 腔。前趨物_ 4 々丨L進入該/儿積 胺則趨物處理糸統保持氧原 們谁入泞接‘ /引趨物不混合直到他 們進入命積腔。該系統又進一步包括— 個別在吝抵4 Λ彳糸統，好餘刻 别在夕循裱式間隙充填的每一循環中 層。 Τ Α積的二氧化矽 附加的實施例與特徵一部分在接下 品加^ ^ ^ ^ 及的描述中提出， 而一，P /刀哪些熟悉技術人士依靠认 目 + 7从 乃曰的檢驗可顯而易 見或可糟由本發明的實施得知。藉由产 、止釦人、 曰田f田述於說明書的構 化、組合與方法可理解與獲得本發明的特徵與優點。 ' ' ' 【實施方式】 描述用在多層式、多循環式沉積二氧化矽於晶圓基板 的間隙内與表面上之系統與方法。各個氡岛、 土 虱化層薄到（例如， 約50Α至約300幻足以讓蝕刻處理解離队 -與移除諸如有機基 團與氮氧基等雜質（其不利地影響該膜的品質與介電特 性）。當已經沉積與蝕刻多個氧化層後，热— 钒仃一退火處理好 200807558 將該多個層形成一高品質、低k值的二氧化石夕膜、The system and processing method of the dielectric material (without adversely affecting the quality of the finished filling). These and other dielectric film deposition patterns are presented by the present invention. [Invention] Embodiments of the present invention include a method of filling a gap on a substrate with cerium oxide. The method comprises the steps of: introducing an organogermanium precursor and an oxygen precursor to a deposition chamber; reacting the precursors to form a first dioxide layer in a gap on the substrate; and then etching the first - The oxidized hair layer is good for reducing the carbon content in the layer. These methods also include forming a second ruthenium dioxide layer on the first layer and then etching the second layer to reduce the carbon content of the layer. After the gap is filled, the dioxin test layers are annealed. Embodiments of the invention also include a method of forming a multilayer dioxide oxidized chopped film onto a substrate. These methods include the step of forming a plurality of tantalum ruthenium layers on the substrate, and each of the ruthenium dioxide layers has a thickness of from about 10 Å to about 2 Å. These layers are formed by the following steps: (1) introducing an organic ruthenium precursor and an oxygen atom precursor into a reaction chamber, and reacting the precursors to form the layer on the US 200807558 plate and (1U) The layer is etched to reduce the number of layers in the layer. Impurities. Then, in the embodiment of the invention, the filling is performed by the bottom up-filling = including the execution - multi-cycle type of dioxin filling on the wafer substrate. The gold includes a deposition chamber, and the complex medium is fixed. System. These systems, in which the holder holds the distal electrode of the deposition chamber, are coupled to the housing system, which is coupled to the oxygen atom precursor. Shovel this system is used to produce, the Qing dynasty also includes one to provide one: # it π ^ 碉 碉 碉 物 物 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , # Guide the early brothers 4, 乂 and ― ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ The predecessor _ 4 々丨L enters the / amide. The trend of the treatment of steroids keeps the oxygenogens who are splicing ‘ / 引 引 引 引 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入The system further includes – individual 吝 4 4 Λ彳糸 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,矽 The additional examples and features of the enthalpy of ruthenium are presented in the description of the following additions ^ ^ ^ ^ and, in addition, the P / knife which familiar with the technical person relies on the recognition + 7 from the test of Nai's is obvious Or it may be known from the practice of the invention. The features and advantages of the present invention are understood and attained by the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] A system and method for depositing a multi-layer, multi-cycle deposition of cerium oxide in the gaps and surfaces of a wafer substrate is described. Each of the islands, the soil layer is thin enough (for example, about 50 Α to about 300 illusion to allow the etching process to disengage the team - and remove impurities such as organic groups and nitroxides (which adversely affect the quality and interface of the film) Electrical characteristics). After a plurality of oxide layers have been deposited and etched, the heat-vanadium-germanium is annealed to form a high-quality, low-k-type cerium oxide film.

由高度活化的氧原子與有機矽前趨物（例如，八甲基環 四矽氫烷「OMCATS」）之反應形成二氧化矽。首先在沉積 發生的腔室外產生氧原子，且與有機矽前趨物保持分隔直 到他們在腔室内混合。產生的二氧化矽富含碳且具高度流 動性，提供一種容易流至狹窄間隙與溝槽底部的沉積膜。 在蝕刻處理至少移除沉積膜中某些較大的碳基團與氫氧基 後，接著的氧化沉積物會流過該第一層且被蝕刻成第二氧 化層。這個循環會反覆許多次直到，例如間隙或溝槽已藉 由夕個氧化層由底部向上填滿。已經將這個多循環式處理 稱為由底部向上的間隙充填。現在將描述關於本發明方 法、產品與系統的額外詳細内容。 示-範性氧化層形成^^方法 弟1圖顯示根據本發明眚m &gt; 豕+ 月貝施例的多循環式二氧化矽 沉積之簡要概述的流程圖。顯千 口 顯不的方法100包括提供含 隙基板給沉積腔（步驟102v。兮就h )該基板具有形成於其上的 造（包括間隙、溝槽等等），這此椹1 A &gt; fk些構造具有的深寬比（高度 上見度）可能約5 : 1或更萬、7 · ·| a 飞更回7 · 1 .或更高、10 : 1或更高 13 * 1或更南、15 : 1或更高等等。 步驟104中，多個二氧化 乳化夕層接著形成於基板的間 内以及其他表面上。藉由在、 在反應腔中使含氧前趨物與有 石夕前趨物反應而沉積二氧化石夕。人〆 '氣前趨物可包括沉稹 外遠端產生的氧原子。氧原子 ’、 j糟由解離下列前趨物而 生.諸如氧氣（0 2)、臭氧（〇 )、氡&amp; 3; 氣虱化合物（例如，一氡 200807558 氮「NO」、二氧化氮「N〇2」、氧化亞氮「N20」等等）、氫 氧化合物（例如，水「H2〇」、過氧化氫「:H202」等等）、碳 氧化合物（例如，一氧化碳「CO」、二氧化碳「c〇2」等等） 以及其他含氧前趨物與上述前趨物的組合物。The formation of cerium oxide is achieved by the reaction of a highly activated oxygen atom with an organic cerium precursor (for example, octamethylcyclotetrahydrohydrogenane "OMCATS"). First, oxygen atoms are generated outside the chamber where deposition occurs, and are kept separate from the organic ruthenium precursor until they are mixed in the chamber. The resulting cerium oxide is carbon-rich and highly fluid, providing a deposited film that easily flows to the narrow gap and the bottom of the trench. After the etching process removes at least some of the larger carbon groups and hydroxyl groups in the deposited film, the subsequent oxidized deposits will flow through the first layer and be etched into the second oxidized layer. This cycle will be repeated many times until, for example, the gap or trench has been filled up from the bottom by the oxide layer. This multi-cycle process has been referred to as filling from the bottom up gap. Additional details regarding the methods, products, and systems of the present invention will now be described. The present invention shows a flow chart of a brief overview of the multi-cycle cerium oxide deposition of the 眚m &gt; 豕+ 月贝 example according to the present invention. The method 100 of displaying a plurality of displays includes providing a gap-containing substrate to a deposition chamber (step 102v. 兮h) the substrate having a build formed thereon (including gaps, trenches, etc.), and thus 椹1 A &gt; These structures have an aspect ratio (height visibility) of about 5:1 or more, 7 · ·| a fly back to 7 · 1 or higher, 10 : 1 or higher 13 * 1 or more South, 15: 1 or higher, etc. In step 104, a plurality of oxidized emulsified layers are subsequently formed in the interior of the substrate as well as on other surfaces. The oxidized stone is deposited by reacting the oxygen-containing precursor with the stiletto precursor in the reaction chamber. Human 〆 'gas precursors may include oxygen atoms generated at the distal end of the sink. Oxygen atoms ', j are produced by dissociation of the following precursors, such as oxygen (0 2), ozone (〇), 氡 &amp;3; gas compounds (for example, one 200807558 nitrogen "NO", nitrogen dioxide" N〇2", nitrous oxide "N20", etc.), hydroxide (for example, water "H2", hydrogen peroxide ":H202", etc.), carbon oxides (for example, carbon monoxide "CO", carbon dioxide "c〇2", etc.) and other combinations of oxygen-containing precursors and the aforementioned precursors.

亦可由下列方式達到解離前趨物以產生氧原子：熱能 解離、紫外光解離與/或電漿解離等方法。電漿解離包括在 遠端電漿產生腔内由氦、氬等擊出電漿，且將該氧前趨物 導引給電漿好產生氧原子前趨物。 首先在腔室内將氧原子導引給有機矽前趨物。有機石夕 前趨物可包括具有直接石夕-碳鍵結的化合物與/或石夕-氧-碳 鏠結的化合物。有機矽烷類之矽前趨物的實例包括二甲基 矽烧（dimethylsilane)、三曱基石夕烧（trimethylsilane)、四甲 基矽烧(tetramethyl silane)、二乙基矽烷（diethyl si lane)、四 曱基石夕酸鹽（tetramethylorthosilicate，TMOS)、四乙基石夕酸 鹽（tetraethylorthosilicate— TEOS)、八甲基三石夕氧 (octamethyltrisiloxane， QMTS)、八曱基環四石夕氧 (octamethyIcyclotetrasiloxane, OMCTS)、四甲基環四石夕氧 (tetramethylcyclotetrasiloxane，TOMCATS)、二甲基二甲氧 基矽烧（dimethyIdimethoxysilane，DMDMOS)、二乙氧基甲 基石夕烷（dietlioxymethylsilane，DEMS)、甲基三乙氧基矽挽 (methyl triethoy silane, MTES)、笨基二曱基矽烷 (phenyldimethylsilane)、苯基矽烷（phenylsilane)等。 可將有機石夕前趨物與一载氣在導入沉積腔前或導入沉 積腔時混合。載氣為一非活性氣體，其不過度干擾基板上 10 200807558 氧化膜的形成。載氣的實例包括氦、氖、氬與氫氣 氣體。 方法1 0 0的實施例中，氧原子與有機石夕前趨物不藏在 一起直到被導入沉積腔後。前趨物經由空間上分散的攝文 前趨物進入口（分散在反應腔周圍）進入腔室。例如， 气原 子前趨物由位在腔室頂部且位於基板正上方的一進 直於 繞在The dissociation precursor can also be achieved in the following manner to generate oxygen atoms: thermal energy dissociation, ultraviolet photodissociation, and/or plasma dissociation. Plasma dissociation involves the blasting of plasma by helium, argon, etc. in the far-end plasma generating chamber, and directing the oxygen precursor to the plasma to produce an oxygen atom precursor. First, oxygen atoms are directed into the organic ruthenium precursor in the chamber. The organophysical precursor may include a compound having a direct cerium-carbon bond and/or a compound of a stagnation-oxygen-carbon ruthenium. Examples of the oxime precursor of the organic decane include dimethylsilane, trimethylsilane, tetramethyl silane, diethyl si lane, and four. Tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (QMTS), octamethy Icyclotetrasiloxane (OMCTS), IV Tetramethylcyclotetrasiloxane (TOMCATS), dimethydidisilane (DMDMOS), dietlioxymethylsilane (DEMS), methyltriethoxysulfonium (methyl triethoy silane, MTES), phenyldimethylsilane, phenylsilane, and the like. The organolithic precursor can be mixed with a carrier gas prior to introduction into the deposition chamber or into the deposition chamber. The carrier gas is an inert gas that does not excessively interfere with the formation of an oxide film on the substrate. Examples of the carrier gas include helium, neon, argon and hydrogen gases. In the embodiment of the method 100, the oxygen atom and the organolithic precursor are not hidden together until after being introduced into the deposition chamber. The precursors enter the chamber via a spatially dispersed teleconverter entry port (dispersed around the reaction chamber). For example, the gas precursor precursor consists of a straight at the top of the chamber and directly above the substrate.

(或進入口群）進入腔室。進入口將氧前趨物流指向垂 基板沉積表面的方向。同時，石夕前趨物由一或多個環 沉積腔側壁的進入口進入腔室。此類進入口將矽前趨 指向大约平行於沉積表面的方向。 附加的實施例包括經由多埠式喷頭的獨立埠傳遞氣原 子與珍前趨物。例如，位在基板上方的噴頭，其可包括人 讓 前趨物進入沉積腔之開口的一種樣式。以氧原子前趨物供 應一部分開口，而以石夕前趨物供應第二部分開口。缓由y 同部分開口傳遞的前趨物，其彼此之間係分離流動直&gt; j 開進入沉積腔。關於前趨物處理設備形式與設計的領夕卜_ 細内容描述於共同讓渡的美國暫時性專利申請案（案說為 A011162/T72700)，由乙1^〇111^1^在與本說明書相同日期 提申且命名為「介電質間隙充填所用的處理腔」，其全文在 此以參考資料的方式併入本文中。 當氧原子與矽前趨物反應於沉積腔内時，他們形成二 氧化矽層於基板沉積表面上。初步的氧化物層具有出色的 流動性，所以可快速地移動至基板表面上構造内的間隙底 部。 11 200807558 各個氧化物層沉積後’將執行—餘刻步驟於該層上好 移除雜質。這將包括將較大的有機基團解離成較小的含碳 分子’以及至少解離某些Si_0H(矽醇）鍵結好形成水與二 氧化矽。 沉積與蝕刻多個二氧化矽層後，將執行一退火處理以 進一 ^趕出水分而將該層轉換成一密集、高品質的氧化物 膜貝把例包括在所有各個二氧化矽層已經經過沉積與蝕 刻後執行一退火處理。附加的實施例包括在一或多個層形 成後i一在所有層的敢終退火處理前的居中式退火處理。例 如，在沉積每2、3、4、5等層數後可執行:居中式退火處理， 接著所有層的最終退火處理。 現在參照第2圖，顯示一描述根據本發明實施例製造 多層式二氧化矽膜的方法200之流程圖。方法2〇〇包括將 前趨物導入包含基板的沉積腔（步驟2〇2)。如同上述提到， 前趨物包括氧原子前趨物與有機矽前趨物。在一遠端高密 度電蒙產生器中，供以4000至6000瓦特（例如，55〇〇瓦 特）的射頻功率給複合氣體流好產生氧原子，該複合氣體流 包括氬氣（其流速，例如約900至約1 800 seem)與氧氣（其 流速，例如約600至約1200 seem)。 籍由混合有機矽化合物(氣體或液體）與載氣（諸如，氛 或氫氣）將有機矽前趨物導入沉積腔。舉例來說，以約6〇〇 至約2400 seem的流速讓氦通過室溫為液態的有機矽前趨 物（例如，八甲基環四矽氧「OMCTS」）而冒出，以提供流 速約800至約1 600 mgm的八甲基環四石夕氧流給腔室。 12 200807558 腔至中，前趨物彼此互相反應以形成一第一氧化物層 於基板上（步驟204)。氧化物層沉積期間腔室内的整體壓 办為，例如約0.5 Torr至約6 Torr。較高的整體壓力（例如， 1.3 Torr)將沉積更具流動特性的氧化物層，而較低的整體 £力（例如’ 〇·5 Torr)將沉積更高程度的同形（eonformai)氧 化物層。由於氧原子為高度反應物質，所以反應腔内的沉 稹溫度則相當地低（例如，約100 °C或更低）。氧化物沉積 速率在每分鐘約125入至約2y m範圍之間（例如，每分鐘 約5〇〇A至約3000a之間；每分鐘約1 500入等等）^該氧化 層的厚度約50A至約500人（例如，約100A至約200A)。 第一氧化層形成後，停止前趨物流進入腔室，然後餘 刻第一氧化層（步驟2 〇 6)。散刻步驟可用來解離與移除該 層内的雜質，且亦用來平面化該層。如同之後第3圖描述 中所到’餘刻處理可包括單—餘刻步驟或多重钱刻步I。 韻刻第一層後’接著重新將前趨物導入沉積腔（步驟 2Ό8) ’然後進行反應以形成第二氧化物層於基板上（步驟 210) 〇第二氧化物層可在與第一層相同的反應條件下形 成’或在一不同條件（諸如，腔室壓力、溫度、有機矽前趨 物等專)下形成。 已經形成第二層後，其亦被蝕刻（步驟212)好減少雜 質里與/或平面化該層。以钱刻第一層所用的相同處理來蝕 刻第_層，或以不同處理（諸如，不同的蝕刻步驟數、不同 的餘到則趨物、不同的功率位準「p 〇 w㊁r 1 e v e 1」等等）來钱 刻第二層。 13 200807558 形成與蝕刻第二個二氧化矽層（以及任何附加的氧化 物層）後’接箸退火處理氧化物層（步驟214)以形成均一、 高品質的二氧北矽間隙充填物。最終的間 k值），以及低於2 :)(諸如，約丄8 :〗至約1 4 :的濕 式餘刻速率比值。整個充填容積内的間隙充填物為均一， 且包含極少（如果有的話）的空隙或裂缝。(or into the mouth group) into the chamber. The inlet port directs the oxygen precursor stream in the direction of the deposition surface of the substrate. At the same time, the pre-existing material enters the chamber from the inlet of one or more of the side walls of the annular deposition chamber. Such an inlet port will point forward to a direction approximately parallel to the deposition surface. Additional embodiments include the transfer of gas and rare precursors via separate helium of a multi-head nozzle. For example, a showerhead positioned above the substrate can include a pattern in which a person allows the precursor to enter the opening of the deposition chamber. A portion of the opening is supplied with an oxygen atom precursor, and a second portion of the opening is supplied with a Zeolite precursor. The precursors that are transferred by the y-port openings are separated from each other and flowed straight into the deposition chamber. The essay on the form and design of the pre-emphasis processing equipment is described in the US Provisional Patent Application for Co-Transfer (case A011162/T72700), which is composed of B1 and 〇111^1^ The same date is referred to and named "Processing Chamber for Dielectric Clearing", which is hereby incorporated by reference in its entirety. When oxygen atoms and ruthenium precursors react in the deposition chamber, they form a layer of ruthenium dioxide on the substrate deposition surface. The preliminary oxide layer has excellent flow properties so it can be quickly moved to the bottom of the gap in the structure on the surface of the substrate. 11 200807558 After deposition of each oxide layer 'will be performed - a residual step on the layer to remove impurities. This will involve dissociation of larger organic groups into smaller carbon-containing molecules&apos; and at least dissociation of certain Si_0H (sterols) linkages to form water and ruthenium dioxide. After depositing and etching a plurality of ruthenium dioxide layers, an annealing treatment is performed to further remove moisture to convert the layer into a dense, high-quality oxide film. Examples include that all of the ruthenium dioxide layers have been deposited. An annealing treatment is performed after etching. Additional embodiments include a centralized annealing treatment prior to the formation of one or more layers. For example, after depositing a number of layers of 2, 3, 4, 5, etc., a central annealing treatment followed by a final annealing treatment of all layers can be performed. Referring now to Figure 2, there is shown a flow chart depicting a method 200 of fabricating a multilayer ceria film in accordance with an embodiment of the present invention. Method 2 includes introducing a precursor to a deposition chamber comprising a substrate (step 2〇2). As mentioned above, the precursors include an oxygen atom precursor and an organic ruthenium precursor. In a remote high-density electrical-monitor generator, RF power of 4000 to 6000 watts (eg, 55 watts) is supplied to the composite gas stream to produce oxygen atoms, the composite gas stream comprising argon (the flow rate thereof, for example From about 900 to about 1 800 seem) with oxygen (its flow rate, such as from about 600 to about 1200 seem). The organic ruthenium precursor is introduced into the deposition chamber by mixing an organic ruthenium compound (gas or liquid) with a carrier gas such as an atmosphere or hydrogen. For example, the ruthenium is allowed to pass through a room temperature liquid helium precursor (eg, octamethylcyclotetrazepine "OMCTS") at a flow rate of from about 6 Torr to about 2400 seem to provide a flow rate. 800 to about 1 600 mgm of octamethylcyclotetrazepine oxygen is supplied to the chamber. 12 200807558 Cavity to medium, the precursors react with each other to form a first oxide layer on the substrate (step 204). The overall pressure within the chamber during deposition of the oxide layer is, for example, from about 0.5 Torr to about 6 Torr. A higher overall pressure (for example, 1.3 Torr) will deposit a more flowable oxide layer, while a lower overall force (eg ' 〇·5 Torr) will deposit a higher degree of eonformai oxide layer. . Since the oxygen atom is a highly reactive species, the temperature in the reaction chamber is relatively low (e.g., about 100 ° C or lower). The oxide deposition rate is in the range of about 125 in. to about 2 ym per minute (e.g., between about 5 Å and about 3,000 amps per minute; about 1,500 Å per minute, etc.). The thickness of the oxide layer is about 50 Å. Up to about 500 people (eg, from about 100 A to about 200 A). After the first oxide layer is formed, the precursor stream is stopped from entering the chamber, and then the first oxide layer is left (step 2 〇 6). The scatter step can be used to dissociate and remove impurities within the layer and also to planarize the layer. As in the description of Fig. 3 that follows, the 'remaining processing' may include a one-remaining step or a multiple-money step I. After the first layer is engraved, 'the precursor is then reintroduced into the deposition chamber (step 2Ό8)' and then reacted to form a second oxide layer on the substrate (step 210). The second oxide layer can be in the first layer. Formed under the same reaction conditions' or formed under a different condition (such as chamber pressure, temperature, organic ruthenium precursor, etc.). Once the second layer has been formed, it is also etched (step 212) to reduce and/or planarize the layer. The first layer is etched by the same process used to engrave the first layer, or differently processed (such as different number of etching steps, different residuals, different power levels, "p 〇w two r 1 eve 1" Wait a minute) to pay for the second layer. 13 200807558 After forming and etching a second layer of ruthenium dioxide (and any additional oxide layers), the oxide layer is subsequently annealed (step 214) to form a uniform, high quality erbium dioxide gap fill. The final inter-k value), and the ratio of the wet remnant rate below 2:) (such as from about 8: to about 14: the gap filler in the entire filling volume is uniform and contains very little (if If there are any gaps or cracks.

第3圖顯示一根據本發明實施例製造多層式二氧化矽 膜之方法300的流程圖（強調兩階段式蝕刻步驟）。方法3〇〇 包括提供一基板給反應腔（步驟3〇2)，然後將前趨物（諸 如，氧與矽前趨物）導入反應腔（步驟3 〇4):接著前趨物開 始反應以形成二氧化矽層於基板上（步驟3〇6)，該層揍著 經歷兩階段式敍刻。 藉由實施第一次蝕刻於氧化物層上（步驟3 0 8 )開始兩 階段式钕刻。這第一次蝕刻包括利用一較低密度的電漿來 解離較大的有機基團且移除至少一部分該層中的碳。這較 低密度的電漿蝕刻包括利用一遠端電黎供應（Rps)系統產 生一兹刻氧化物層的氬/氧電漿。蝕刻環境包括，諸如以約 5500瓦特功率由流速1600 secm的氧氣與400 sccm的氬擊 出電漿，且將電漿導入壓力约76〇^^的沉積腔。此種 電漿蝕刻法可解離較大的碳基團且由該氧化物層移除碳雜 質。 第一次餘刻後，接著在較高的電漿密度下執行氧化物 層的第二次蝕刻（步驟310)，以移除該層中至少一部分的 14 200807558 氫氧基。此種較高密度的電漿蝕刻法包括暴露該層給一電 漿，該電漿形成於以高功率射頻場（例如，6〇〇〇瓦特）解離 氧分子流（例如，600 seem)。可將氧電聚導入沉積腔（其壓 力，例如約8 mTorr)然後與氧化物層t的氫氧基團（_〇h group)反應以形成二氧化石夕與水。Figure 3 shows a flow diagram of a method 300 of fabricating a multilayer erbium dioxide film in accordance with an embodiment of the present invention (emphasizing a two-stage etch step). Method 3 includes providing a substrate to the reaction chamber (step 3〇2), and then introducing a precursor (such as oxygen and a ruthenium precursor) into the reaction chamber (step 3 〇 4): then the precursor starts to react A layer of ruthenium dioxide is formed on the substrate (step 3〇6), which layer undergoes a two-stage characterization. A two-stage engraving is initiated by performing a first etch on the oxide layer (step 308). This first etch involves the use of a lower density plasma to dissociate the larger organic groups and remove at least a portion of the carbon in the layer. This lower density plasma etch includes the production of an argon/oxygen plasma with a etched oxide layer using a remote power supply (Rps) system. The etching environment includes, for example, blowing plasma at a flow rate of 1600 secm of oxygen and 400 sccm of argon at a power of about 5,500 watts, and introducing the plasma into a deposition chamber having a pressure of about 76 Å. This plasma etching process dissociates larger carbon groups and removes carbon impurities from the oxide layer. After the first pass, a second etch of the oxide layer (step 310) is then performed at a higher plasma density to remove at least a portion of the 14 200807558 hydroxyl groups in the layer. Such higher density plasma etching involves exposing the layer to a plasma formed to dissociate a stream of oxygen molecules (e.g., 600 seem) in a high power RF field (e.g., 6 watts). Oxygen can be electropolymerized into a deposition chamber (whose pressure, e.g., about 8 mTorr) and then reacted with a hydroxyl group (_hh group) of the oxide layer t to form a dioxide dioxide and water.

在下一氧化物層（形成於先前層上）上重複沉積與蝕刻 循環（步驟312)。接著增進沉積與蝕刻過的氧化物層直到 達到預定的層數與/咸薄膜厚度，之後退火處理該多個氧化 物層（步驟314)。可用單一步驟或多個步驟執行退火處理。 舉例來說，可藉由在實質上乾燥的空氣（諸如，乾燥的氮、 氦、氬等等）中加熱多個氧化物層到達約3Q(rc至約i 〇〇〇 。(：之間的溫度（例如，約600°C至約900°C之間）而執行單一 步驟的退火處理。退火處理由沉積層中移除水分且進一步 將石夕醇（S i - Ο Η )基團轉換成二氧化石夕。 多步式退火處理包括兩步式退火處理，在兩步式退火 處理中該層初步經歷濕式退火階段，例如在蒸氣存在下加 熱該層到達約7 0 0 °C (舉例）。這之後可為乾式退火階段， 該層在一實質上沒有水分的空氣（例如，乾燥氣氣）中被加 熱至更兩的溫度（餘如，約9 q 〇 )。初步濕式退火處理可 幫助水解矽碳（Si-C)鍵結成為矽醇（Si-OH)鍵結，而乾式退 火處理將矽醇鍵結（Si-0H)轉換成二氧化矽鍵結以及從該 層中趕出水分。 除了濕室與乾式熱能退火處理外，可應用其他退火技 術（單獨或組合）來退火處理該多個氧化物層。這些退火技 15 200807558 術包括蒸氣退火、電漿退火、紫外光退火、電子束退火與/ 或微波退火等。 現在參…、第4圖，顯示描述根據本發明實施例製造多 曰式氧化石夕膜的方法4〇〇之另—個流程圖。方法4〇〇包 括提供基板給沉積腔（步驟4〇2)，然後將前趨物（諸如，氧 原子與有機矽七趨物）導入腔室内（步驟4〇4)。使前趨物反 應以形成一氧化矽層於基板上（步驟4〇6)，接著蝕刻該氧 化物層（步驟408) 〇 在這個時刻’會執行一個檢查來確定沉積之氧化物層 的累積厚度是否已達到預先設定點（步驟41〇)。假若已經 達到整體氧化物膜的預設厚度，那麼將停止沉積與蝕刻循 環，然後退火處理該膜（步驟412)。然而，假若尚未達到 預疋厚度，那麼將發生另一次沉積與餘刻循環以至少増加 一或更多附加層給該氧化物膜。 確定該氧化物膜是否已經達到預定厚度可由下列方式 來執行·測量沉積與餘刻過之層的厚度；或計算 π ^ ^ ^ ^ ^ ^ ^ ^ ^ '到所欲 、、膜厚度所需的層數。例如，假設每個沉積與飿刻過 層的厚度為100A，而所欲之薄膜厚度為]麻· 要執杆1 7 麼而 丁 1 2 :人沉積與蝕刻循環以形成該膜。各個沉積屛的厚 度可藉由調控影響氧化物沉積速率的參數來設定，* ^ ^ 碌參數 匕諸如反應前趨物的類型與流速、沉積腔中的整體壓力 M及溫度等參數。如上述提到，典型的氧化物層沉積速率 係每分鐘約5〇〇Α至約3〇〇〇Α (例如，約每分鐘15〇〇α)、 第5 A-F圖顯示具有間隙構造的基板，利用多德产气 16 200807558 沉積-蝕刻氧化物層形成處理的者 叹毯的貝施例，以多層式二氧化 膜逐漸填滿該間隙。第5A圄ig - ^ 9 圖顯不一基板502與已經形士 於其上的間隙504。可以理鏟齙一 _ &gt; ^战 理解顯不於第5A_F圖中的 504以相當低的深寬比來绔陳 3不，疋為了更清楚地顯示氡 物充填層的過程。本間隙充埴化 死填法的實施例包括不具空隙赤 裂缝的沉積進入間隙，且該 卜或 或間隙具有5 : 1、6 : 1、7 · ! 8 : 1、9 : 1、10 : 1、11 : !、19 1、 第5 B圖顯示沉積在間 ^ 门隙504内的第一氧化物 506a。形成該層的二氧化 層 , …、有良好的流動特性，讓診胞The deposition and etching cycles are repeated on the next oxide layer (formed on the previous layer) (step 312). The deposited and etched oxide layer is then promoted until a predetermined number of layers and/or salt film thickness is reached, after which the plurality of oxide layers are annealed (step 314). The annealing process can be performed in a single step or in multiple steps. For example, by heating a plurality of oxide layers in substantially dry air (such as dry nitrogen, helium, argon, etc.) to about 3Q (rc to about i 〇〇〇. A single step of annealing is performed at a temperature (for example, between about 600 ° C and about 900 ° C.) The annealing treatment removes moisture from the deposited layer and further converts the Si 醇 ( i Ο Η ) group into The multi-step annealing treatment includes a two-step annealing treatment in which the layer is initially subjected to a wet annealing stage, for example, heating the layer in the presence of steam to about 700 ° C (for example) This can be followed by a dry annealing stage in which the layer is heated to a temperature of two more (for example, about 9 q 〇) in a substantially moisture-free atmosphere (eg, dry gas). Preliminary wet annealing It helps to hydrolyze the ruthenium carbon (Si-C) bond to a sterol (Si-OH) bond, while the dry anneal process converts the sterol bond (Si-0H) into a ruthenium dioxide bond and rushes from the layer Water is removed. In addition to the wet chamber and dry thermal annealing, other annealing techniques can be applied ( The plurality of oxide layers are annealed individually or in combination. These annealing techniques 15 200807558 include steam annealing, plasma annealing, ultraviolet annealing, electron beam annealing, and/or microwave annealing, etc. Now, Fig. 4, A flow chart describing a method of fabricating a multi-type oxidized oxide film according to an embodiment of the present invention is shown. Method 4 includes providing a substrate to a deposition chamber (step 4〇2), and then introducing a precursor ( For example, an oxygen atom and an organic cerium heptasome are introduced into the chamber (step 4〇4). The precursor is reacted to form a ruthenium oxide layer on the substrate (step 4〇6), and then the oxide layer is etched (step 408) At this moment, a check is performed to determine whether the accumulated thickness of the deposited oxide layer has reached a predetermined point (step 41〇). If the preset thickness of the overall oxide film has been reached, the deposition will stop. Etching cycle, then annealing the film (step 412). However, if the pre-thickness has not been reached, then another deposition and residual cycle will occur to add at least one or more additional layers to the oxidation. Determining whether the oxide film has reached a predetermined thickness can be performed by measuring the thickness of the deposited layer and the remaining layer; or calculating π ^ ^ ^ ^ ^ ^ ^ ^ ^ ' to the desired thickness The number of layers required. For example, suppose the thickness of each deposited and etched layer is 100A, and the desired film thickness is 麻······························· Membrane. The thickness of each deposited crucible can be set by adjusting the parameters affecting the oxide deposition rate, such as the type and flow rate of the reaction precursor, the overall pressure M in the deposition chamber, and the temperature. As mentioned above, a typical oxide layer deposition rate is from about 5 Å to about 3 Å per minute (e.g., about 15 〇〇 α per minute), and the fifth AF map shows a substrate having a gap structure, utilizing Dodd gas production 16 200807558 The deposition-etching oxide layer formation process of the sigh blanket, the multilayer oxide film gradually fills the gap. The 5A圄ig-^9 diagram shows a substrate 502 with a gap 504 that has been formed thereon. It can be understood that the 504 in the 5A_F diagram is not shown in the 5A_F diagram with a relatively low aspect ratio. In order to more clearly show the process of the sputum filling layer. The embodiment of the gap filling dead fill method includes a deposition gap without a void red crack, and the gap or gap has 5:1, 6:1, 7 · ! 8 : 1, 9 : 1, 10 : 1 , 11 : !, 19 1 , FIG. 5B shows the first oxide 506a deposited in the gate gap 504. Forming the dioxide layer of the layer, ..., has good flow characteristics, allowing the patient to diagnose

快速地移動至間隙504的底邱 ra L π展口Ρ。因此，沉積在間隙5〇4 部的氧化物厚度會比沿著間 间隙側壁的氧化物厚度來得大。 第5C與5D圖顯示附加的惫 ° Τ刀的乳化物層506b、506c等 將這些層沉積在間隙504中之前p ”灶 ’ 丫（則已》几積且蝕刻過的層上 這些附加的層由間隙504的底部向i 。 _ ί 1门上形成，直到達到所 氧化物膜的厚度（例如，間隙5〇4的頂部）。^&quot; 一旦沉積與蝕刻多個氧化物層的最後一層後，實施一 退火處理將該些層形成均一的薄膜5〇8(如第5g圖所示^ 藉由例如電漿蝕刻或化學機械研磨（CMp)等方式平面化= 膜好移除超過間隙504頂部形成的沉積材質。第51?圖= 示剩下的二氧化梦間隙充填物5〗〇，其具有極少（如果有的 話）的空隙或裂缝且具有高度薄膜品質與介電特性。 色葱性羞板處理系繞 執行本發明實施例的沉積系統包括高密度電漿化學氣 17 200807558Move quickly to the bottom of the gap 504 ra L π spread Ρ. Therefore, the thickness of the oxide deposited in the gap 5〇4 is larger than the thickness of the oxide along the sidewall of the gap. Figures 5C and 5D show additional layers of emulsifier layers 506b, 506c, etc., which deposit these layers in gap 504 before the p""''''''' Formed by the bottom of the gap 504 toward i. _ ί 1 until the thickness of the oxide film is reached (for example, the top of the gap 5〇4). ^&quot; Once the last layer of the oxide layer is deposited and etched An annealing treatment is performed to form the layers into a uniform film 5〇8 (as shown in FIG. 5g) by means of, for example, plasma etching or chemical mechanical polishing (CMp), etc. = the film is removed over the top of the gap 504. The deposited material is formed. Figure 51 shows the remaining dioxide dream fillings, which have very few, if any, voids or cracks and have high film quality and dielectric properties. The shame treatment is performed on a deposition system that performs the embodiments of the present invention including high density plasma chemical gas 17 200807558

相沉積（high-density plasma chemical vapor deposition, HDP-CVD)系統、電漿辅助化學氣相沉積（plasma enhanced chemical vapor deposition，PECVD)系統、次大氣壓化學氣 相沉積(sub-atmospheric chemical vapor deposition, SACVD)系統與熱能化學氣相沉積系統等類型的系統。執 行本發明實施例的化學氣相沉積系統之特定實例包括 CENTURA ULTIMAtm高密度電漿化學氣相沉積腔/系統與 PRODUCERTM電漿輔助化學氣相沉積腔/系統（AppliedHigh-density plasma chemical vapor deposition (HDP-CVD) system, plasma enhanced chemical vapor deposition (PECVD) system, sub-atmospheric chemical vapor deposition (SACVD) System and thermal energy chemical vapor deposition systems and other types of systems. Specific examples of chemical vapor deposition systems embodying embodiments of the present invention include CENTURA ULTIMAtm high density plasma chemical vapor deposition chamber/system and PRODUCERTM plasma assisted chemical vapor deposition chamber/system (Applied)

Materials，Inc·，Santa Clara，California)。 一個適當的基板處理系統（其中可修改用來應用依照 本發明之實施例）顯示與描述於共同讓渡的美國專利申請 案第6,38 7,207與6,83 0,624號中，其在此以參考方式併入 本文中。第6A圖係化學氣相沉積系統i〇的垂直、橫剖面 圖式’該系統具有真空或處理腔i 5，該腔包括腔壁15&amp;與 腔蓋配件1 5b 〇 化學氣相沉積系統1〇包含一氣體分配歧管U，好分 散處理氣體至支撐在加熱底座12(位於處理腔15中心)上 的基板（未顯示）。可用導電材質來構成氣體分配歧管丨丨好 使/、本身作為开》成電容電漿(eapaeiti plas瓜③）的電極。處 理過程中，基板（例如，一半導體晶圓）被置於底座丨2的平 坦（或務微凸起）表面12a上。可操作底座12在較低的負载 /卸载位置（第6A圖中所示）與較高的處理位置（由第6A圖 中的虛線14表不X間移動，而處理位置緊密地鄰近歧管 11中〜電路板包括可提供晶圓位置資訊的感應器。 18 200807558 經由習知平坦、環型之氣體分配面板 13 a的射孔 (perforated hole) 13b，將沉積氣體與载氣導入腔室15。更 明確地，沉積處理氣體經由歧管11進入口，通過習知的射 孔阻擔板（perforated blocker plate)42然後通過氣體分配 面板13a中的孔洞13b流入腔室。Materials, Inc., Santa Clara, California). A suitable substrate processing system (which may be modified to apply an embodiment in accordance with the present invention) is shown and described in the commonly assigned U.S. Patent Application Serial Nos. 6, 387, 207 and 6, 830, the entire disclosure of which is incorporated herein by reference. The manner is incorporated herein. Figure 6A is a vertical, cross-sectional view of a chemical vapor deposition system i. The system has a vacuum or processing chamber i 5, which includes a chamber wall 15 &amp; and a chamber cover assembly 1 5b 〇 chemical vapor deposition system 1 A gas distribution manifold U is included to distribute the process gas to a substrate (not shown) supported on the heating base 12 (located at the center of the processing chamber 15). The conductive material can be used to form the gas distribution manifold so that it can be used as the electrode of the capacitor (eapaeiti plas melon 3). During processing, a substrate (e.g., a semiconductor wafer) is placed on the flat (or micro-protrusion) surface 12a of the pedestal 2. The operable base 12 is moved between the lower load/unload position (shown in FIG. 6A) and the higher processing position (by the dashed line 14 in FIG. 6A, the processing position is closely adjacent to the manifold 11 The medium to circuit board includes an inductor that provides information on the position of the wafer. 18 200807558 A deposition gas and a carrier gas are introduced into the chamber 15 via a perforated hole 13b of a conventional flat, toroidal gas distribution panel 13a. More specifically, the deposition process gas enters the port via the manifold 11 and flows into the chamber through a conventional perforated blocker plate 42 and then through a hole 13b in the gas distribution panel 13a.

到達歧管11前，沉積氣體與載氣由氣體源7經由氣體 供應管線8輸入混合系統9，他們在那混·合然後送至歧管 11。一般而言，各個處理氣體的供應管線包括⑴多個安全 性閉鎖閥（未顯示），其可用來自動或手動關閉進入腔室的 處理氣體流，以及（ii)質量流量控制器(mass flow controllers)(亦未顯示），其可測量通過供應管線的氣體 流。當使用有毒氣體於處理時，將多個安全性閉鎖閥置於 習知結構中的各個氣體供應管線。 執行於化學氣相沉積系統10中的沉積處理可為熱能 處理或電漿辅助處理。電漿辅助處理中，射頻功率供應器 44在氣體分配面板1 3a與底座1 2之間施加電功率，以便 活化處理氣體混合物，好在面板13 a與底座12之間圓柱型 區域中形成電漿。此區域在此將被稱為「反應區域」。使電 漿的組成反應好沉積所欲的薄膜於半導體晶圓（支擒於底 座12上）的表面上。射頻功率供應器44係一種混合型射頻 功率供應器，一般來說其可提供13·56 MHz的高射頻頻率 與360 kHz的低射頻頻率，好辅助導入真空腔15之反應物 質的分解。熱能處理中，不使用射頻功率供應器44，且處 理氣體混合物進行熱能反應好沉積所欲的薄膜於半導體晶 19 200807558 圓（支撐於底座12上）的表面上，而該底座具熱抗性好提供 熱能給反應。 電漿輔助沉積處理過程中，電漿加熱整體處理腔1〇 , 其包括排出通道23與閉鎖閥24周圍的腔室主體之腔壁 15 a。當未發動電聚時或熱能沉積處理過程中，將熱的液體 循環遍及處理腔1 5的腔壁1 5 a以維持腔室處於高溫下。而 腔壁1 5 a其餘部分的通道並未顯示。用來加熱腔壁1 $ a的 液體包括典型液體類型，即水性乙二醇或油性熱能傳導液 體。這類加熱（指的是藉由「熱能交換物」來力σ熱）有益於 減少或排除不欲的反應產物之凝結，且增進排出處理氣體 的揮發性產物與其他可能污染處理的污染物（假若這些物 質凝結於冷的真空通道壁上，且在沒有氣體流動時流回處 理腔内）。 沒有沉積於層内的剩餘氣體混合物（其包括反應副產 品），藉由真空泵（未顯示）而排出腔室15外。明確地說， 氣體經由反應區域周圍的環型、狹缝狀洞口16排出，然後 進入環型排出室17。藉由腔室的圓柱型側壁i5a的頂端'(包 括腔壁上較高的介電内襯丨9)與環型腔蓋2〇底部之間的間 隙界定環型狹缝16與排出室17。360。環型對稱且一致的 狹缝洞口 16與排出室17，對達成晶圓上均句城 流（以便沉積均勻薄膜於晶圓上）而言是重要的。 由’出室” 始’氣體流進排出室17的橫向延展部 分21 ’經過觀察孔（viewing p〇rt)，通過向下延展的氣體通 道23 ’經過真空閉鎖閥24(其本體併入較低的腔壁 20 200807558 中）’然後進入排出口 25，該排出口經由一前置管線 (foreline)(未顯示）連結至外部真空泵（亦未顯示）。 底座12的晶圓支撐板（材質最好為鋁、陶質或上述之 組合物）具抗熱性，其利用一嵌入式單環嵌入加熱元件來加 熱該加熱元件設置成平行同心圓形式的兩個完整圓圈。 加熱元件外側部分位於鄰近支撐板的周圍，而内側部分則 在/、有較小直徑的同心圓路徑上。連接加熱元件的線路 則經過底座12的主桿。 一般而言，任何或所有腔室内襯、氣體進入歧管面板 以及許多其他反應器的硬體，係由諸如鋁、電鍍銘或陶器 等材質製成。此類化學氣相沉積設備的一實例係描述於共 Π讓度且由Zhao等人提伸並命名為「化學氣相沉積處 理腔J的美國專利案第5,558,71 7號，而其全文在此以參 考資料併入本文中。 舉昇機構與馬達32(第6A圖）隨著機械片（未顯示）經 由腔室10側邊的插入/移除開口 26將晶圓傳入與傳出腔室 本體15，提高與降下加熱底座配件12與其晶圓舉昇銷 1 2 b。馬達3 2在處理位置1 4與較低的晶圓負載位置之間提 高與降下底座12。所有下述的裝置均受系統調控器調控 (通過控制管線36，僅顯示某些管線）:馬達；連結至供應 管線8的活門或流量控制器;氣體傳送系統；節流閥·，射 頻功率供應器44 ;以及腔室與基板加熱系統❶調控器34 依靠來自光學感應器的反饋來測定可移動式機械配件的位 置’例如節流闕與力σ熱基板(3113〇601〇1：)在調控器34的調控 21 200807558 下藉由適當的馬達而移動。Before reaching the manifold 11, the deposition gas and carrier gas are fed from the gas source 7 via the gas supply line 8 to the mixing system 9, where they are mixed and then sent to the manifold 11. In general, the supply lines for each process gas include (1) a plurality of safety latching valves (not shown) that can be used to automatically or manually shut off process gas flow into the chamber, and (ii) mass flow controllers. ) (also not shown), which measures the flow of gas through the supply line. When a toxic gas is used for treatment, a plurality of safety latching valves are placed in each gas supply line in a conventional configuration. The deposition process performed in the chemical vapor deposition system 10 may be thermal energy processing or plasma assisted processing. In the plasma assisted process, the RF power supply 44 applies electrical power between the gas distribution panel 13a and the base 12 to activate the process gas mixture to form a plasma in the cylindrical region between the face plate 13a and the base 12. This area will be referred to herein as the "reaction area." The composition of the plasma is reacted to deposit the desired film on the surface of the semiconductor wafer (supported on the base 12). The RF power supply 44 is a hybrid RF power supply that typically provides a high RF frequency of 13.56 MHz and a low RF frequency of 360 kHz to aid in the decomposition of the reactants introduced into the vacuum chamber 15. In the thermal energy treatment, the RF power supply 44 is not used, and the treatment gas mixture is subjected to thermal energy reaction to deposit the desired film on the surface of the semiconductor crystal 19 200807558 (supported on the base 12), and the base is heat resistant. Provide heat for the reaction. During the plasma assisted deposition process, the plasma heats the overall processing chamber 1 , which includes the discharge passage 23 and the chamber wall 15 a of the chamber body surrounding the latching valve 24. When the electropolymerization is not initiated or during the thermal energy deposition process, hot liquid is circulated throughout the chamber wall 15 a of the processing chamber 15 to maintain the chamber at a high temperature. The passage of the rest of the wall 1 5 a is not shown. The liquid used to heat the chamber wall 1 $ a includes a typical liquid type, i.e., aqueous glycol or oily thermal energy transfer liquid. This type of heating (referring to the "heat energy exchange" to force σ heat) is beneficial to reduce or eliminate the condensation of unwanted reaction products, and to enhance the volatile products of the exhausted process gas and other contaminants that may contaminate the treatment ( If these substances condense on the walls of the cold vacuum channel and flow back into the processing chamber when no gas flows. The remaining gas mixture (which includes the reaction by-products) which is not deposited in the layer is discharged outside the chamber 15 by a vacuum pump (not shown). Specifically, the gas is discharged through the ring-shaped, slit-like opening 16 around the reaction zone, and then enters the annular discharge chamber 17. The annular slit 16 and the discharge chamber 17 are defined by a gap between the top end ' of the cylindrical side wall i5a of the chamber (including the higher dielectric liner 9 on the chamber wall) and the bottom of the annular chamber cover 2'. 360. The ring-shaped symmetrical and uniform slit opening 16 and the discharge chamber 17 are important for achieving a uniform flow on the wafer (to deposit a uniform film on the wafer). From the 'outlet chamber', the gas flows into the laterally extending portion 21' of the discharge chamber 17 through the viewing hole, through the downwardly extending gas passage 23' through the vacuum lock valve 24 (the body is incorporated into the lower portion) The cavity wall 20 200807558)) then enters the discharge port 25, which is connected to an external vacuum pump (also not shown) via a foreline (not shown). The wafer support plate of the base 12 (best material) Heat resistant to aluminum, ceramic or a combination thereof, which utilizes an embedded single-ring embedded heating element to heat the heating element in two parallel circles arranged in parallel concentric circles. The outer portion of the heating element is located adjacent to the support plate The inner portion is on a concentric circular path with a smaller diameter. The line connecting the heating elements passes through the main pole of the base 12. In general, any or all of the chamber liners, gases enter the manifold panel, and The hardware of many other reactors is made of materials such as aluminum, electroplating or ceramics. An example of such a chemical vapor deposition apparatus is described in terms of co-management by Zhao et al. U.S. Patent No. 5,558,71, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the A mechanical sheet (not shown) is introduced into and out of the chamber body 15 via the insertion/removal opening 26 on the side of the chamber 10 to raise and lower the heated base assembly 12 and its wafer lift pin 1 2 b. Motor 32 raises and lowers base 12 between processing position 14 and a lower wafer load position. All of the devices described below are regulated by the system controller (through control line 36, only certain lines are shown): motor; a valve or flow controller coupled to the supply line 8; a gas delivery system; a throttle valve, an RF power supply 44; and a chamber and substrate heating system ❶ governor 34 relying on feedback from the optical sensor to determine the movable type The position of the mechanical component 'for example, the throttle and force σ thermal substrate (3113〇601〇1:) is moved by the appropriate motor under the regulation 21 200807558 of the governor 34.

示範性實施例中，系統調控器包括一硬碟（記憶體 3 8)、一軟碟與一處理器 37。處理器包括單板機 (single-borad computer，SBC)、類比與數位输入/輸出板、 介面板與步進式電動控制板（stepper motor controller boards)。化學氣相沉積系統i〇的許多部份遵照歐洲插卡 式模組（Versa Modular European，VME)標準（其界定主機 板、卡槽與連接器的尺寸與類型）。VME標準亦界定匯流 排結構為具有16位元資料匯流排與24位元位址匯流排。 系統調控器34調控化學氣相沉積器械的、所有活動。系 統調控器執行系統調控軟體，其係一存於電腦可讀媒體.（例 如，記憶體38)的電腦程式。記憶體38較佳為硬碟，但記 憶體3 8亦可為其他類型的記憶體。電腦程式包括制定下列 參數的指令組：時間、混合的氣體、腔室壓力、腔室溫度、 射頻功率強度、加熱基板位置與特定處理的其他參數。存 於其他記憶體元件（包括，諸如軟碟或其他合適的裝置）的 其他電腦程式，亦可用來運轉調控器34。 可利用電腦程式產品(由調控器34執行）來實施沉積 一薄膜於基板上的處理或清潔腔室15的處理。可用任何習 知的電腦可讀式程式語言來編寫電腦程式編碼：例如， 68000 組合語言（assembly language)、C、C++、Pascal、 Fortran或其他。利用習知的文件編輯器將適當的程式編碼 輸入成單一檔案或多個檔案，且存於或具現於電腦可用式 媒體（computer usable medium)，例如電腦的記憶體系統〇 22 200807558 假若輸入的編碼文件為高階語言，那麼編譯該編碼，然後 合成的編譯碼接著鏈結（linked)於預先編譯的Microsoft Window®程序庫程序（library routines)之目的碼（object code)。為了執行鏈結、已編譯之目的碼，系統使用者希望 目的碼引發電腦系統讀取記憶體中的編碼。中央處理器 (CPU)接著讀取與執行編碼好完成程式中識別的工作。 使用者與調控器34之間的介面係經由陰極射線管顯In the exemplary embodiment, the system controller includes a hard disk (memory 38), a floppy disk, and a processor 37. Processors include single-borad computers (SBCs), analog and digital input/output boards, interface panels, and stepper motor controller boards. Many parts of the chemical vapor deposition system comply with the Versa Modular European (VME) standard (which defines the size and type of motherboard, card slot and connector). The VME standard also defines a busbar structure with a 16-bit data bus and a 24-bit address bus. System controller 34 regulates all activities of the chemical vapor deposition apparatus. The system controller executes the system control software, which is a computer program stored on a computer readable medium (e.g., memory 38). The memory 38 is preferably a hard disk, but the memory 38 can also be other types of memory. The computer program includes an instruction set that sets the following parameters: time, mixed gas, chamber pressure, chamber temperature, RF power intensity, heated substrate position, and other parameters for specific processing. Other computer programs stored in other memory components, including, for example, floppy disks or other suitable devices, can also be used to operate the controller 34. The processing of depositing a film on the substrate or cleaning the chamber 15 can be performed using a computer program product (performed by the controller 34). Computer program code can be written in any conventional computer readable programming language: for example, 68000 assembly language, C, C++, Pascal, Fortran, or others. Use a conventional file editor to input the appropriate program code into a single file or multiple files, and store it in or on a computer usable medium, such as a computer's memory system. 22 200807558 If the input code The file is a high-level language, then the code is compiled, and the synthesized code is then linked to the object code of the pre-compiled Microsoft Window® library routines. In order to execute the linked, compiled object code, the system user wants the destination code to cause the computer system to read the code in the memory. The central processing unit (CPU) then reads and performs the work identified in the coded completion program. The interface between the user and the controller 34 is displayed via a cathode ray tube

示器（CRT monitor)50a與光筆50b(第6B圖所示），第6B 圖係系統顯示器與基板處理系統（可包括一或多個腔室）中 化學氣相沉積系統1 〇的簡單圖式。較佳的實施例中，運用 兩個顯示器50a，其中一個鑲嵌於清潔室壁（操作者用），雨 另一個位在該壁後面（設備技術員用）。顯示器5〇a可同時 顯示相同的資訊，但僅可用一隻光筆50b。光筆5〇b災端 的光感應器偵測由陰極射線管顯示器散發出來的光線。為 了選擇特定的螢幕區域或功能，操作者觸碰顯示器營幕上 選定的區域，然後按下光筆5〇b上的按鈕。觸碰的區域改 變其強調顏色，或是顯示一個新的選單或螢幕，好確定光 筆與顯示器榮幕之間的訊息傳違。其他諸如鍵盤、滑鼠或 其他和示或傳達裝置等裝置，可用來替代或加強光筆5〇b 好讓使用者與調控器34交流訊息。 第6A圖顯示遠端電漿產生器6〇，其裝設在處理腔15 的腔蓋配件1 5b上（包括氣體分配面板1 3a與氣體分配歧管 11) 木β又接合器（mounting adaptor)64裝設遠端電漿產生 器60於腔蓋配件15b上（如第6A圖所示）。接合器64 一般 23 200807558CRT monitor 50a and light pen 50b (shown in Figure 6B), Figure 6B is a simple diagram of a chemical vapor deposition system 1 in a system display and substrate processing system (which may include one or more chambers) . In the preferred embodiment, two displays 50a are used, one of which is mounted to the clean room wall (for the operator) and the other to the rear of the wall (for the equipment technician). The display 5〇a can display the same information at the same time, but only one light pen 50b can be used. The light sensor of the light pen 5〇b disaster detects the light emitted by the cathode ray tube display. To select a specific screen area or function, the operator touches the selected area on the display screen and then presses the button on the light pen 5〇b. Touch the area to change its accent color, or display a new menu or screen to determine the message between the stylus and the display screen. Other devices such as a keyboard, mouse or other display or communication device can be used to replace or enhance the light pen 5〇b for the user to communicate with the controller 34. Figure 6A shows a distal plasma generator 6〇 mounted on the chamber cover fitting 15b of the processing chamber 15 (including the gas distribution panel 13a and the gas distribution manifold 11). 64 is provided with a distal plasma generator 60 on the chamber cover fitting 15b (as shown in Figure 6A). Adapter 64 General 23 200807558

是由金屬所構成。混合裝置70 I馬接於氣體分配歧管11的 上游端（第6A圖）。混合裝置70包括一配置於混合阻擋物 (用以混合處理氣體）之狹缝 74 内的混合鑲嵌塊 (insert)72。陶質絕緣體66置於架設接合器64與混合裝置 70之間（第6A圖）。可由諸如氧化鋁（純度99% )、Teflon® 等陶器材質來製造陶質絕緣體66。裝設時，混合裝置70 與陶質絕緣體66會構成腔蓋配件15b的一部分。絕緣體 66隔絕金屬接合器64與混合裝置70與氣體分配歧管Π， 好減少第二次電漿形成於腔蓋配件15b中的可能性（更詳 細描述於下）。三通闕77不是直接就是經由遠端電漿產生 器60來調控進入處理腔1 5的處理氣體流動。 樂見遠端電梁產生器60為——緊密、自我調控的組件， 其可方便地裝置於腔蓋配件1 5 b上且可容易地式樣翻新到 現存腔室上而不需要昂貴且耗時的修改。一個適當的組件 為 ASTRON®產生器（Applied Science and Technology，Inc·， Woburn, Mass)。ASTRON㊣產生器利用低場效環型電漿 (low-field toroidal plasma)來解離處理氣體。一實例中， 該電漿解離處理氣體，該處理氣體包括含氟氣體（例如三氟 化氮「NF3」）與載氣（例如氬），而產生自由氟，而自由散 可被用來清潔沉積於處理腔1 5中的薄膜❶ 已經描述許多實施例，熟悉技術的人士可以理解，其 可在不悖離本發明之精神下使用許多修改物、替換構造與 均等物。再者，並未描述許多知名的處理方式與元件好避 免對本發明造成不必要的混淆。因此，上述内容不應被視 24 200807558 為本發明範圍的限制性。 此處所提供的數值範圍，可以理解各個介於範亂較高 與較低限制值之間的中間值（徐非文中另有明確指出，否則 到較低限制值之單位的十分之一）亦明確地被揭示。任何所 述數值之間的各個較小範圍；或所述範圍與任何其他所述 數值的中間值；或所述範圍的中間值均包含在其中。這些 較小範圍的較高與較低限制值可單獨地被包括在範圍内或 排除在範圍外，且各個範圍的限制值（任一、兩者皆無、兩 者皆有m包含在較小範圍亦包含在本發明中，其屬於所述 範圍内任何特別排除在外的限制值。所述範圍包括一或兩 個限制值，亦包括排除任一或兩者限制值的範圍。 此處與附加的專利申請範圍中所甩的單數形式「一 ⑷」、「一 (an)J與「該」包括多個所指對象，除非文中另 有明確指出。目此，舉例來說，提到「一處理」係包括多 :此類處理，而提到「該前趨物」係包括所指的一或多個 月《趨物與熟悉技術人士所知的均等物等等。 同樣地，應用於本說明書與接下來的申請專利範圍之 詞彙「包括丨、「包会 廿扣士 」’八用來明確指明所述之特徵、整體、 成分或步驟的存在，徊* 认 忐八 一、不排除一或多個其他特徵、整體、 成刀、，騍、行動或群組的存在或附加。 【圖式簡單說明】 可藉由參照說明書剩餘部分與圖式來實現 質與優點的進一步了 _ ' 〆了解，在圖式内不同圖中相同的 25 200807558 號代表相同的部件。某些實例中，次要符號連結於元件符 號且跟在連字號後以代表許多相同部件的其中之一。當沒 有詳述現行的次要符號之元件編號當作參考時，意指代表 所有這類的多個相同元件： 第1圖係顯示一根據本發明實施例的多循環式二氧化 石夕層沉積方法之簡要概述的一流程圖； 第2圖係描述一根據本發明實施例製造多層式二氧化 石夕膜之方法的一流程圖； 第3圖係強調一根據本發明實施例製造多層式二氧化 石夕膜之方法内兩階段式蝕刻步驟的一流程圖； 第4圖係描述一根據本發明實施例製造多層式二氧化 矽膜之方法的另一流程亂； 第5A-F圖顯示根據本發明實施例具有間隙構造的一 基板，該間隙逐漸以多層式二氧化矽膜充填； 第6A圖顯示一根據本發明實施例之一基板處理系統 的垂直橫剖面圖式，該系統可用來形成二氧化矽層；以及 第6B圖係一根據本發明實施例之基板處理系統的系 統顯示器/調控器部件的簡草圖式。 【主要元件符號說明】 10 化學氣相沉積系統 11 氣體分配歧管 12 底座 12a 底座表面 12b 舉昇銷 13a 氣體分配面板 1 3 b 射孔 14 處理位置 26 200807558 15 處理腔 15a 腔壁 15b 腔蓋配件 16 狹缝洞口 17 排出室 19 介電内襯 20 環型腔蓋 21 橫向延展部分 23 通道 24 閉鎖閥 25 排出口 26 開口 32 馬達' 3 4 調控器 3 6 控制管線 3 7 處理器 38 記憶體 42 射孔阻擔板 44 射頻功率供應器 5 0a 顯示器 50b 光筆 6 0 遠端電漿產生器 64 揍合器 6 6 絕緣體 70 混合裝置 72 混合鑲嵌塊 74 狹缝 7 7 三通閥It is made of metal. The mixing device 70 is coupled to the upstream end of the gas distribution manifold 11 (Fig. 6A). Mixing device 70 includes a hybrid insert 72 disposed within slit 74 of the mixing barrier (for mixing the process gas). The ceramic insulator 66 is placed between the erecting adapter 64 and the mixing device 70 (Fig. 6A). The ceramic insulator 66 can be made of a ceramic material such as alumina (purity 99%), Teflon®, or the like. When installed, the mixing device 70 and the ceramic insulator 66 will form part of the chamber cover fitting 15b. Insulator 66 isolates metal bonder 64 from mixing device 70 and gas distribution manifold 好 to reduce the likelihood of a second plasma formation in chamber cover fitting 15b (described in more detail below). The three-way port 77 does not regulate the flow of process gas into the process chamber 15 either directly or via the remote plasma generator 60. It is appreciated that the remote beam generator 60 is a compact, self-regulating assembly that can be conveniently mounted to the chamber cover assembly 15 b and can be easily retrofitted to an existing chamber without the need for costly and time consuming Modifications. One suitable component is the ASTRON® generator (Applied Science and Technology, Inc., Woburn, Mass). The ASTRON positive generator utilizes a low-field toroidal plasma to dissociate the process gas. In one example, the plasma dissociates the process gas, which includes a fluorine-containing gas (such as nitrogen trifluoride "NF3") and a carrier gas (such as argon) to produce free fluorine, and the free dispersion can be used for clean deposition. A number of embodiments have been described in the processing of the membranes in the chamber 15. It will be appreciated by those skilled in the art that many modifications, alternative constructions and equivalents may be used without departing from the spirit of the invention. Furthermore, many well-known processes and components have not been described in order to avoid unnecessarily obscuring the present invention. Therefore, the above should not be construed as limiting the scope of the invention. The range of values provided here can be used to understand the intermediate values between the higher and lower limit values (also explicitly stated in Xu Feiwen, otherwise one tenth of the unit of the lower limit value) Clearly revealed. Each of the smaller ranges between the recited values; or the intermediate values of the recited ranges and any other recited values; or intermediate values of the ranges are included. The higher and lower limit values of these smaller ranges may be included in the range alone or excluded from the range, and the limit values of each range (any, neither, or both, are included in the smaller range) It is also included in the present invention, and it is intended to include any limitation that is specifically excluded. The range includes one or two limit values, and includes the exclusion of either or both of the limits. The singular forms "a", "an" and "the" are used in the singular, and unless the The system includes more than: such treatment, and the reference to "the predecessor" includes one or more months referred to as "the trend and the equivalents known to those skilled in the art, etc.. Similarly, applied to this specification. And the following vocabulary of the scope of the patent application "including 丨, "包会廿扣士"' eight is used to clearly indicate the existence of the characteristics, the whole, the composition or the steps mentioned, 徊* 忐 忐 、 、 、 、 、 、 、 Multiple other features, overall, knife The existence, or addition, of 骒, action, or group. [Simple description of the diagram] The quality and advantages can be further improved by referring to the rest of the specification and the schema _ ' 〆 understand, the same in different figures in the schema 25 200807558 represents the same component. In some instances, the minor symbol is linked to the component symbol and follows the hyphen to represent one of many identical components. When the component number of the current secondary symbol is not detailed, By reference, it is meant to represent a plurality of identical elements of all such: Figure 1 is a flow chart showing a brief overview of a multi-cycle type smectite layer deposition method in accordance with an embodiment of the present invention; A flow chart for a method of fabricating a multilayered dioxide dioxide film in accordance with an embodiment of the present invention is described; FIG. 3 is an illustration of a two-stage etching step in a method of fabricating a multilayered dioxide dioxide film in accordance with an embodiment of the present invention. A flow chart; FIG. 4 is a diagram showing another flow of a method of manufacturing a multilayered ceria film according to an embodiment of the present invention; and FIGS. 5A-F are diagrams showing an embodiment according to the present invention. a substrate constructed, the gap being gradually filled with a multi-layered hafnium oxide film; FIG. 6A is a vertical cross-sectional view showing a substrate processing system according to an embodiment of the present invention, which system can be used to form a hafnium oxide layer; Figure 6B is a simplified sketch of a system display/regulator component of a substrate processing system in accordance with an embodiment of the present invention. [Main component symbol description] 10 chemical vapor deposition system 11 gas distribution manifold 12 base 12a base surface 12b Upsell 13a gas distribution panel 1 3 b perforation 14 treatment position 26 200807558 15 treatment chamber 15a chamber wall 15b chamber cover fitting 16 slit opening 17 discharge chamber 19 dielectric lining 20 annular cavity cover 21 lateral extension 23 channel 24 Blocking valve 25 Discharge port 26 Opening 32 Motor ' 3 4 Governor 3 6 Control line 3 7 Processor 38 Memory 42 Perforation blocking plate 44 RF power supply 5 0a Display 50b Light pen 60 0 Remote plasma generator 64 Clutch 6 6 Insulator 70 Mixing device 72 Hybrid inlay block 74 Slit 7 7 3-way valve

100、200、300、400 方法 102 、 104 v 106 、 202 、 204 、 206 、 208 、 210 、 212 、 214 、 3 02、3 04、3 06、308、310、3 1 2、3 1 4、402、4 04、406、 408 、 410 、 412 步驟 502 基板 ^ ^ 504 間隙 5 06a、5 06b、5 0 6c··· 5 06η 氧化物層 508 薄膜 510 二氧化矽間隙充填 27100, 200, 300, 400 Method 102, 104 v 106, 202, 204, 206, 208, 210, 212, 214, 3 02, 3 04, 3 06, 308, 310, 3 1 2, 3 1 4, 402 4 04, 406, 408, 410, 412 Step 502 Substrate ^ ^ 504 Clearance 5 06a, 5 06b, 5 0 6c··· 5 06η Oxide layer 508 Thin film 510 Ceria gap filling 27

Claims (1)

200807558 十、申請專利範圍： 1. 一種以二氧化矽充填一基板上的一間隙之方法，該 方法至少包含： 將一有機梦前趨物與一氧前趨物導入一沉積腔； 使該些前趨物反應以形成一第一二氧化梦層於該基板 上的間隙中； 蝕刻該第一二氧化矽層以減少該層中的碳含量；200807558 X. Patent Application Range: 1. A method for filling a gap on a substrate with cerium oxide, the method comprising at least: introducing an organic dream precursor and an oxygen precursor into a deposition chamber; The precursor reacts to form a first dioxide mask layer in the gap on the substrate; etching the first layer of germanium dioxide to reduce the carbon content in the layer; 形成一第二二氧化矽層於該第一層上，然後蝕刻該第二 層以減少該層中的碳含量;以及 待該間隙被填滿後退火處理該些二氧化矽層。 2. 如申請專利範圍第1項之方法，其中該氧前趨物包 括產生於該沉積腔外的氧原子。 3. 如申請專利範圍第2項之方法，其中該氧原子係藉 由下述步驟而形成： 由一包含氬之氣體混合物形成一電漿；以及 將一氧前趨物導入該電漿，其中該氧前趨物解離以形成 該氧原子。 4.如申請專利範圍第3項之方法，其中該氧前趨物係 選自氧分子、臭氧與二氧化氮組成的群組中。 28 200807558 5·如申請專利範圍第2項之方法，其中該氧原子係藉 由下述步驟而形成·· 將一氧前趨物導入一光解離腔；以及 暴露該氧前趨物給紫外光，其中該紫外光解離該氧前趨 物以形成該氧原子。Forming a second cerium oxide layer on the first layer, then etching the second layer to reduce the carbon content in the layer; and annealing the cerium oxide layer after the gap is filled. 2. The method of claim 1, wherein the oxygen precursor comprises oxygen atoms generated outside the deposition chamber. 3. The method of claim 2, wherein the oxygen atom is formed by: forming a plasma from a gas mixture comprising argon; and introducing an oxygen precursor into the plasma, wherein The oxygen precursor dissociates to form the oxygen atom. 4. The method of claim 3, wherein the oxygen precursor is selected from the group consisting of oxygen molecules, ozone and nitrogen dioxide. 28. The method of claim 2, wherein the oxygen atom is formed by the following steps: introducing an oxygen precursor into a photodissociation chamber; and exposing the oxygen precursor to ultraviolet light Wherein the ultraviolet light dissociates the oxygen precursor to form the oxygen atom. 6·如申請專利範圍第2項之方法，其中該有機梦前趨 物與該氧原子不混在一起直到被導入該沉積腔後。 7.如申請專利範圍第1項之方法，其中該有機矽前趨 物包括二甲基矽烷、三甲基矽烷、四甲基矽烷、二乙基石夕 烧、四甲基正石夕酸鹽（{64&amp;11161:1171〇1：1:11〇3111(^16，丁1^08)、四 乙基正石夕酸鹽（tetraethylorthosilicate，ΤΈΟ S)、八甲基三發 氧(octamethyltrisiloxane， 0MTS)、八曱基環四矽氣 (octamethylcyclotetrasiloxane，OMCTS)、四甲基環四發氧 (tetramethylcyclotetrasiloxane5 TOMCATS)、二曱基二甲氧 基矽烧（dimethyl dimethoxy si lane，DM DM OS)、二乙氧基甲 基矽烧(di ethoxy methyl silane，DEM S)、甲基三乙氧基石夕燒 (methyl triethoxy silane, MTES)、苯基二甲基矽燒 (phenyldimethylsilane)、苯基矽烷（phenylsilane)。 8·如申請專利範圍第1項之方法，其中該第一與第二 二氧化矽層各自的厚度在約1 00A至約200A之間。 29 200807558 9.如申請專利範圍第1項之方法，其中該蝕刻第一與 第二二氧化矽層的步驟包括： 將該層暴露在一具有一第一密度的第一電漿下，其中該 第一電漿可解離該層中較大的碳分子；以及6. The method of claim 2, wherein the organic dream precursor is not mixed with the oxygen atom until after being introduced into the deposition chamber. 7. The method of claim 1, wherein the organic ruthenium precursor comprises dimethyl decane, trimethyl decane, tetramethyl decane, diethyl cerium, tetramethyl chloroform ( {64&amp;11161:1171〇1:1:11〇3111(^16,丁1^08), tetraethylorthosilicate (ΤΈΟS), octamethyltrisiloxane (0MTS) , octamethylcyclotetrasiloxane (OMCTS), tetramethylcyclotetrasiloxane 5 TOMCATS, dimethyl dimethoxy si lane (DM DM OS), diethoxy Di ethoxy methyl silane (DEM S), methyl triethoxy silane (MTES), phenyldimethylsilane, phenylsilane. The method of claim 1, wherein the first and second cerium oxide layers each have a thickness of between about 100 A and about 200 A. 29 200807558 9. The method of claim 1, wherein Step package for etching the first and second cerium oxide layers Include: exposing the layer to a first plasma having a first density, wherein the first plasma dissociates a larger carbon molecule in the layer; 將該層暴露在一具有一第二密度的第二電漿，其中該第 二密度高於該第一密度且該第二電漿可解雞該層中的矽醇 (Si-OH)鍵結。 10. 如申請專利範圍第1項之方法，其中該退火處理二 氧化矽層的步驟包括一在乾燥無活性氣體中約800°c或更 高溫度下進行退火處理。 11. 如申請專利範圍第10項之方法，其中該無活性氣 體為氮（N2)而該溫度係900°C。 12. 如申請專利範圍第1項之方法，其中該方法包括形 成附加的二氧化矽層於該第一與第二層上，且其中各個附 加的二氧化矽層的厚度為約50A至約500A間。 13. 如申請專利範圍第12項之方法，其中該附加的二 氧化矽層係以如同蝕刻該第一與第二二氧化矽層的方式被 餘刻。 30 200807558 14. 如申請專利範圍第1 2項之方法，其中該二氧化矽 層的一總厚度係約500A至約10,000A。 15. 如申請專利範圍第1項之方法，其中該退火處理過 的二氧化石夕層的濕式钱刻速率比值（wet etch rate ratio, WERR)約2 : 1或更低。Exposing the layer to a second plasma having a second density, wherein the second density is higher than the first density and the second plasma cleaves a sterol (Si-OH) bond in the layer . 10. The method of claim 1, wherein the step of annealing the ruthenium dioxide layer comprises annealing at a temperature of about 800 ° C or higher in the dry inert gas. 11. The method of claim 10, wherein the inactive gas is nitrogen (N2) and the temperature is 900 °C. 12. The method of claim 1, wherein the method comprises forming an additional layer of ruthenium dioxide on the first and second layers, and wherein each additional layer of ruthenium dioxide has a thickness of from about 50 A to about 500 Å. between. 13. The method of claim 12, wherein the additional ruthenium dioxide layer is engraved as if the first and second ruthenium dioxide layers were etched. The method of claim 12, wherein the total thickness of the cerium oxide layer is from about 500 Å to about 10,000 Å. 15. The method of claim 1, wherein the annealed sulphur dioxide has a wet etch rate ratio (WERR) of about 2:1 or less. 1 6.如申請專利範圍第1項之方法，其中該退火處理過 的二氧化矽層的濕式蝕刻速率比值約 1 · 8 : 1至約1.4:1 間。 17. 如申請專利範圍第1項之方法，其中該退火處理過 的二氧化石夕層的k值約4.0或更低。The method of claim 1, wherein the annealed ruthenium dioxide layer has a wet etch rate ratio of between about 8.6:1 and about 1.4:1. 17. The method of claim 1, wherein the annealed treated silica layer has a k value of about 4.0 or less. 18. 如申請專利範爵第1項之方法，其中該方法更包括 在將該前趨物導入該沉積腔前，預先以一高密度電漿處理 該基板。 1 9.如申請專利範圍第1項之方法，其中該間隙的深寬 比約5 r 1或更高。 -- . '- 2 0.如申請專利範圍第1項之方法，其中該間隙的课寬 31 200807558 比约13 : 1或更高。 21. —種形成一多層式二氧化矽膜於——基板上之方 法，該方法至少包含： 形成多個二氧化矽層於該基板上，其中各個二氧化矽層 的厚度約100A至約200A間，且其中各個層係藉由下列步 驟而形成；18. The method of claim 1, wherein the method further comprises pre-treating the substrate with a high density plasma prior to introducing the precursor to the deposition chamber. 1 9. The method of claim 1, wherein the gap has a depth to width ratio of about 5 r 1 or higher. --- ' 0. The method of claim 1 wherein the gap is 31 200807558 or about 13 : 1 or higher. 21. A method of forming a multilayer erbium dioxide film on a substrate, the method comprising: forming a plurality of ruthenium dioxide layers on the substrate, wherein each ruthenium dioxide layer has a thickness of about 100 Å to about 200A, and each layer is formed by the following steps; (i) 將一有機砍前趨物與一氧原子前趨物導入一反應 腔； (ii) 使該些前趨物進行反應以形成該層於該基板上；以 及 (iii) 蝕刻該層好減少該層中的雜質；以及退火處理該 多個層。 22 ·如申請專利範圍第2 1項之方法，其中該氧原子前 趨物係在談沉積腔外產生，且其中該有機矽與氧原子前趨 物不混在一起直到被導入該反應腔後。 2 3.如申請專利範圍第21項之方法，其中該蝕刻該層 包括： 一 將該層暴露在——具有一第一密度的第一電漿下，其中該 第一電漿可解離該層中較大的碳分子；以及 將該層暴露在一具有一第二密度（高於該第一密度）的 32(i) introducing an organic chop precursor and an oxygen atom precursor into a reaction chamber; (ii) reacting the precursors to form the layer on the substrate; and (iii) etching the layer Reducing impurities in the layer; and annealing the plurality of layers. 22. The method of claim 2, wherein the oxygen atom precursor is produced outside the deposition chamber, and wherein the organic ruthenium and the oxygen atom precursor are not mixed until after introduction into the reaction chamber. 2. The method of claim 21, wherein the etching the layer comprises: exposing the layer to a first plasma having a first density, wherein the first plasma can dissociate the layer a larger carbon molecule; and exposing the layer to a 32 having a second density (above the first density) 200807558 第二電漿下，其中該第二電漿可解離該層中的矽 24.如申請專利範爵第21項之方法，其中該 該多個層的步驟包括一熱能退火、——蒸氣退火、 火、——紫外光退火、一電子束退火或一微波退火 25.如申請專利範圍第21項之方法，其中該 該多個層的步驟包括： 在一第一退火溫度與蒸氣存在下加熱該基板； 在一第二退火溫度下與乾燥氮氣中加熱該基 26.如申請專利範圍第25項之方法，其中 溫度係約650T：而該第二退火溫度係約900X：。 27.如申請專利範圍第21項之方法，其中 自係於每分鐘約125A至約2 μ m的一速率下形 28.如申請專利範圍第21項之方法，其中 係於約3分鐘或更短時間内被蝕刻。 29.如申請專利範圍第21項之方法，其中 被退火處理约30分鐘或更短時間。 醇鍵結。 退火處理 一電漿退 處理。 退火處理 以及 第一退火 :多個層各 「些層各自 ?多假層係 33 200807558 3〇.如申請專利範圍第21項之方法，其中該多個層的 濕式餘刻速率比值在約18 : 1至約14 : i間。 31.如申請專利範圍第21項之方法，其中該多個層的 k值為約4 · 0或更低。 32.如申請專利範圍第21項之方法，其中該多層式二 氧化矽膜的厚度在約1000A至約3000A間。 3 3. —種執行一多循環式二氧化矽由底部向上間隙充 填一晶圓基板上間隙的系統，該系統至少包含： 一沉積腔，其中固持著該含有間隙的基板； 一遠端電漿產生系統，其搞揍於該沉積腔，其中該電黎 產生系統係用來產生一氧原子前趨物； 一有機矽前趨物源，其用來供應一有機矽前趨物給該沉 積腔； 二 ^ ^ ^ ^ ^ ^ &gt; 一前趨物處理系統，其用來導引該氧原子前趨物與該矽 前趨物流進入該沉積腔，其中該前趨物處理系統保持該氧 原子與該石夕前趨物不混在一起直到他們進入該沉積腔；以 及 、 一蝕刻系統，其用來蝕刻在該多循環式間隙充填的各個 循環令沉積的各個二氧化石夕層。 34 200807558 3 4.如申請專利範圍第33項之系統，其中該系統更包 括一退火處理系統，其用來退火處理多個形成於該基板上 的二氧化矽層。 35·如申請專利範園第34項之系統，其中該退火處理 系統包括一熱能退火、一蒸氣退火、一電漿退火、一紫外 光退火、一電子束退火或一徵波退火處理系統。200807558 The second plasma, wherein the second plasma can dissociate the crucible in the layer. 24. The method of claim 21, wherein the step of the plurality of layers comprises a thermal annealing, a vapor annealing The method of claim 21, wherein the step of the plurality of layers comprises: heating at a first annealing temperature and in the presence of steam, a fire, an ultraviolet anneal, an electron beam anneal, or a microwave anneal. The substrate is heated at a second annealing temperature with dry nitrogen. The method of claim 25, wherein the temperature is about 650T: and the second annealing temperature is about 900X:. 27. The method of claim 21, wherein the method is at a rate of from about 125 A to about 2 μm per minute. The method of claim 21, wherein the method is about 3 minutes or more. It is etched in a short time. 29. The method of claim 21, wherein the annealing is performed for about 30 minutes or less. Alcohol bonding. Annealing treatment A plasma retreat treatment. Annealing treatment and first annealing: a plurality of layers each of which has a plurality of layers. The method of claim 21, wherein the ratio of the wet residual rate of the plurality of layers is about 18 The method of claim 21, wherein the k value of the plurality of layers is about 4 · 0 or lower. 32. The method of claim 21, Wherein the multi-layered hafnium oxide film has a thickness of between about 1000 A and about 3000 A. 3 3. A system for performing a multi-cycle ceria to fill a gap on a wafer substrate from the bottom to the upper gap, the system comprising at least: a deposition chamber in which the substrate containing the gap is held; a distal plasma generating system that smashes the deposition chamber, wherein the electricity generation system is used to generate an oxygen atom precursor; a source of material for supplying an organic ruthenium precursor to the deposition chamber; a ^ ^ ^ ^ ^ ^ ^ &gt; a precursor processing system for guiding the oxygen atom precursor and the front Flowing into the deposition chamber, wherein the precursor processing system remains The oxygen atoms are not mixed with the effluent precursor until they enter the deposition chamber; and an etching system is used to etch the respective layers of the dioxide deposited in each of the multiple cycles of the gap filling. 4. The system of claim 33, wherein the system further comprises an annealing treatment system for annealing a plurality of ruthenium dioxide layers formed on the substrate. 35. The system of claim 34, wherein the annealing treatment system comprises a thermal energy annealing, a vapor annealing, a plasma annealing, an ultraviolet annealing, an electron beam annealing or a undulation annealing treatment system. 3 6·如申請專利範圍第33項之系統，其中該系統包括 一高密度電漿化學氣相沉猜（HDPCVD)系統。3 6. The system of claim 33, wherein the system comprises a high density plasma chemical vapor deposition (HDPCVD) system. 3535
TW096119169A 2006-05-30 2007-05-29 A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide TWI366876B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80348106P 2006-05-30 2006-05-30
US11/753,968 US7902080B2 (en) 2006-05-30 2007-05-25 Deposition-plasma cure cycle process to enhance film quality of silicon dioxide

Publications (2)

Publication Number Publication Date
TW200807558A true TW200807558A (en) 2008-02-01
TWI366876B TWI366876B (en) 2012-06-21

Family

ID=38779413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096119169A TWI366876B (en) 2006-05-30 2007-05-29 A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide

Country Status (6)

Country Link
EP (1) EP2036120A4 (en)
JP (1) JP5225268B2 (en)
KR (1) KR101115750B1 (en)
CN (1) CN101454877B (en)
TW (1) TWI366876B (en)
WO (1) WO2007140377A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557799B (en) * 2008-03-14 2016-11-11 應用材料股份有限公司 Methods for oxidation of a semiconductor device
TWI638402B (en) * 2013-03-15 2018-10-11 應用材料股份有限公司 Apparatus and methods for pulsed photo-excited deposition and etch

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7498273B2 (en) * 2006-05-30 2009-03-03 Applied Materials, Inc. Formation of high quality dielectric films of silicon dioxide for STI: usage of different siloxane-based precursors for harp II—remote plasma enhanced deposition processes
US8329587B2 (en) * 2009-10-05 2012-12-11 Applied Materials, Inc. Post-planarization densification
CN102054734B (en) * 2009-11-10 2013-01-30 中芯国际集成电路制造(上海)有限公司 Method for improving filling capacity of wafer channel
US8528224B2 (en) * 2009-11-12 2013-09-10 Novellus Systems, Inc. Systems and methods for at least partially converting films to silicon oxide and/or improving film quality using ultraviolet curing in steam and densification of films using UV curing in ammonia
US8512809B2 (en) 2010-03-31 2013-08-20 General Electric Company Method of processing multilayer film
US8318584B2 (en) * 2010-07-30 2012-11-27 Applied Materials, Inc. Oxide-rich liner layer for flowable CVD gapfill
US9234276B2 (en) * 2013-05-31 2016-01-12 Novellus Systems, Inc. Method to obtain SiC class of films of desired composition and film properties
US10325773B2 (en) 2012-06-12 2019-06-18 Novellus Systems, Inc. Conformal deposition of silicon carbide films
US8889566B2 (en) 2012-09-11 2014-11-18 Applied Materials, Inc. Low cost flowable dielectric films
CN104885196B (en) * 2012-12-31 2018-02-06 Fei 公司 Charged particle beam system and induce deposition using charged particle beam and fill the method in hole
US9018108B2 (en) 2013-01-25 2015-04-28 Applied Materials, Inc. Low shrinkage dielectric films
CN103972146B (en) * 2013-01-30 2016-12-28 中芯国际集成电路制造(上海)有限公司 The forming method of groove isolation construction
US9354508B2 (en) 2013-03-12 2016-05-31 Applied Materials, Inc. Planarized extreme ultraviolet lithography blank, and manufacturing and lithography systems therefor
JP5943888B2 (en) * 2013-08-28 2016-07-05 株式会社東芝 Manufacturing method of semiconductor device
US20150340274A1 (en) * 2014-05-23 2015-11-26 GlobalFoundries, Inc. Methods for producing integrated circuits with an insultating layer
US9412581B2 (en) 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
KR20160061129A (en) * 2014-11-21 2016-05-31 주식회사 원익아이피에스 Method of fabricating stacked film
CN107430991A (en) * 2015-02-23 2017-12-01 应用材料公司 For forming the circulation continuous processing of high-quality thin film
CN108140578B (en) * 2015-10-23 2022-07-08 应用材料公司 Bottom-up gapfill by surface poisoning
US9935005B2 (en) * 2015-11-13 2018-04-03 Applied Materials, Inc. Techniques for filling a structure using selective surface modification
US10115601B2 (en) 2016-02-03 2018-10-30 Tokyo Electron Limited Selective film formation for raised and recessed features using deposition and etching processes
US9768034B1 (en) * 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
CN106783535A (en) * 2016-11-28 2017-05-31 武汉新芯集成电路制造有限公司 The method and semiconductor structure of a kind of improvement PETEOS film defects
WO2018191484A1 (en) * 2017-04-13 2018-10-18 Applied Materials, Inc. Method and apparatus for deposition of low-k films
CN109166787B (en) * 2018-08-26 2019-06-28 合肥安德科铭半导体科技有限公司 A kind of flowable chemical vapor deposition method of silicon oxide film
US20200090980A1 (en) * 2018-09-13 2020-03-19 Nanya Technology Corporation Method for preparing semiconductor structures
KR20230085953A (en) 2018-10-19 2023-06-14 램 리써치 코포레이션 Doped or undoped silicon carbide deposition and remote hydrogen plasma exposure for gapfill
KR102224128B1 (en) 2019-08-05 2021-03-09 한양대학교 산학협력단 Deposition method of carbon thin-film
JP7227122B2 (en) 2019-12-27 2023-02-21 株式会社Kokusai Electric Substrate processing method, semiconductor device manufacturing method, substrate processing apparatus, and program
JP7072012B2 (en) 2020-02-27 2022-05-19 株式会社Kokusai Electric Substrate processing method, semiconductor device manufacturing method, substrate processing device, and program

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0616505B2 (en) * 1987-08-18 1994-03-02 株式会社半導体エネルギ−研究所 Insulation film formation method
JP2980340B2 (en) * 1990-04-28 1999-11-22 科学技術振興事業団 CVD method
US5393708A (en) 1992-10-08 1995-02-28 Industrial Technology Research Institute Inter-metal-dielectric planarization process
JP2684942B2 (en) * 1992-11-30 1997-12-03 日本電気株式会社 Chemical vapor deposition method, chemical vapor deposition apparatus, and method for manufacturing multilayer wiring
US5576071A (en) * 1994-11-08 1996-11-19 Micron Technology, Inc. Method of reducing carbon incorporation into films produced by chemical vapor deposition involving organic precursor compounds
US5558717A (en) 1994-11-30 1996-09-24 Applied Materials CVD Processing chamber
JPH0982696A (en) * 1995-09-18 1997-03-28 Toshiba Corp Manufacture of semiconductor device and semiconductor manufacturing equipment
JP3522917B2 (en) * 1995-10-03 2004-04-26 株式会社東芝 Semiconductor device manufacturing method and semiconductor manufacturing apparatus
JPH11145131A (en) * 1997-03-18 1999-05-28 Toshiba Corp Manufacture of semiconductor device, semiconductor manufacturing apparatus, and semiconductor device
US6413583B1 (en) * 1998-02-11 2002-07-02 Applied Materials, Inc. Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound
US6197658B1 (en) 1998-10-30 2001-03-06 Taiwan Semiconductor Manufacturing Company Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity
US6387207B1 (en) 2000-04-28 2002-05-14 Applied Materials, Inc. Integration of remote plasma generator with semiconductor processing chamber
JP4698813B2 (en) * 2000-10-19 2011-06-08 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6531413B2 (en) * 2000-12-05 2003-03-11 United Microelectronics Corp. Method for depositing an undoped silicate glass layer
US6770521B2 (en) * 2001-11-30 2004-08-03 Texas Instruments Incorporated Method of making multiple work function gates by implanting metals with metallic alloying additives
US7723242B2 (en) * 2004-03-15 2010-05-25 Sharp Laboratories Of America, Inc. Enhanced thin-film oxidation process
US7205248B2 (en) * 2003-02-04 2007-04-17 Micron Technology, Inc. Method of eliminating residual carbon from flowable oxide fill
US6867086B1 (en) * 2003-03-13 2005-03-15 Novellus Systems, Inc. Multi-step deposition and etch back gap fill process
US6830624B2 (en) 2003-05-02 2004-12-14 Applied Materials, Inc. Blocker plate by-pass for remote plasma clean
US6958112B2 (en) * 2003-05-27 2005-10-25 Applied Materials, Inc. Methods and systems for high-aspect-ratio gapfill using atomic-oxygen generation
KR100538882B1 (en) * 2003-06-30 2005-12-23 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557799B (en) * 2008-03-14 2016-11-11 應用材料股份有限公司 Methods for oxidation of a semiconductor device
TWI638402B (en) * 2013-03-15 2018-10-11 應用材料股份有限公司 Apparatus and methods for pulsed photo-excited deposition and etch
US10508341B2 (en) 2013-03-15 2019-12-17 Applied Materials, Inc. Apparatus and methods for pulsed photo-excited deposition and etch

Also Published As

Publication number Publication date
CN101454877A (en) 2009-06-10
KR101115750B1 (en) 2012-03-07
JP5225268B2 (en) 2013-07-03
EP2036120A2 (en) 2009-03-18
JP2009539266A (en) 2009-11-12
WO2007140377A2 (en) 2007-12-06
EP2036120A4 (en) 2012-02-08
WO2007140377A3 (en) 2008-08-28
CN101454877B (en) 2012-07-04
WO2007140377A9 (en) 2008-10-16
TWI366876B (en) 2012-06-21
KR20090019865A (en) 2009-02-25

Similar Documents

Publication Publication Date Title
TW200807558A (en) A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide
TWI399453B (en) Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen
US7902080B2 (en) Deposition-plasma cure cycle process to enhance film quality of silicon dioxide
KR101329285B1 (en) Formation of high quality dielectric films of silicon dioxide for sti: usage of different siloxane-based precursors for harp ii - remote plasma enhanced deposition processes
TWI395269B (en) Curing methods for silicon dioxide thin films deposited from alkoxysilane precurson with harp ii process
KR101161074B1 (en) Methods for forming a silicon oxide layer over a substrate
US7888273B1 (en) Density gradient-free gap fill
JP2009539268A (en) Chemical vapor deposition of high quality fluidized silicon dioxide using silicon-containing precursors and atomic oxygen
TW201133624A (en) Stress management for tensile films
TW201126010A (en) Curing non-carbon flowable CVD films
TW201246329A (en) Reduced pattern loading using silicon oxide multi-layers
TW201233842A (en) Radical steam CVD