KR20080087722A - 반도체장치의 제작 방법 - Google Patents

반도체장치의 제작 방법 Download PDF

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Publication number
KR20080087722A
KR20080087722A KR1020080027674A KR20080027674A KR20080087722A KR 20080087722 A KR20080087722 A KR 20080087722A KR 1020080027674 A KR1020080027674 A KR 1020080027674A KR 20080027674 A KR20080027674 A KR 20080027674A KR 20080087722 A KR20080087722 A KR 20080087722A
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KR
South Korea
Prior art keywords
single crystal
crystal semiconductor
layer
layers
substrate
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Ceased
Application number
KR1020080027674A
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English (en)
Korean (ko)
Inventor
순페이 야마자키
이쿠코 카와마타
야수유키 아라이
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20080087722A publication Critical patent/KR20080087722A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/24—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement by concurrent transfer of multiple parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
KR1020080027674A 2007-03-26 2008-03-26 반도체장치의 제작 방법 Ceased KR20080087722A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007079787 2007-03-26
JPJP-P-2007-00079787 2007-03-26

Publications (1)

Publication Number Publication Date
KR20080087722A true KR20080087722A (ko) 2008-10-01

Family

ID=39560776

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080027674A Ceased KR20080087722A (ko) 2007-03-26 2008-03-26 반도체장치의 제작 방법

Country Status (4)

Country Link
US (3) US7682931B2 (https=)
EP (1) EP1975998A3 (https=)
JP (1) JP2008270775A (https=)
KR (1) KR20080087722A (https=)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1975998A3 (en) * 2007-03-26 2013-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a plurality of island-shaped SOI structures
CN102623400B (zh) * 2007-04-13 2015-05-20 株式会社半导体能源研究所 显示器件、用于制造显示器件的方法、以及soi衬底
KR101443580B1 (ko) * 2007-05-11 2014-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Soi구조를 갖는 기판
JP5264237B2 (ja) * 2007-05-15 2013-08-14 キヤノン株式会社 ナノ構造体およびナノ構造体の製造方法
TWI437696B (zh) * 2007-09-21 2014-05-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
US8455331B2 (en) * 2007-10-10 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
JP5464843B2 (ja) * 2007-12-03 2014-04-09 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
SG160295A1 (en) * 2008-09-29 2010-04-29 Semiconductor Energy Lab Method for manufacturing semiconductor device
JP5607399B2 (ja) * 2009-03-24 2014-10-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8043938B2 (en) * 2009-05-14 2011-10-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and SOI substrate
JP5268792B2 (ja) * 2009-06-12 2013-08-21 パナソニック株式会社 半導体装置
JP2011029609A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法およびｓｏｉ基板
JP5866088B2 (ja) * 2009-11-24 2016-02-17 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8525370B2 (en) * 2009-11-30 2013-09-03 Broadcom Corporation Wireless power circuit board and assembly
US9094054B2 (en) * 2009-11-30 2015-07-28 Broadcom Corporation IC controlled wireless power operation and applications thereof including control channel communication configuration
JP5926887B2 (ja) * 2010-02-03 2016-05-25 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8587045B2 (en) * 2010-08-13 2013-11-19 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of forming the same
US8841196B1 (en) * 2010-09-29 2014-09-23 Crossbar, Inc. Selective deposition of silver for non-volatile memory device fabrication
US9401475B1 (en) 2010-08-23 2016-07-26 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
JP5696882B2 (ja) * 2010-12-16 2015-04-08 日立化成株式会社 帯電体並びにそれを用いた電界効果トランジスタ及びメモリ素子
US8486791B2 (en) 2011-01-19 2013-07-16 Macronix International Co., Ltd. Mufti-layer single crystal 3D stackable memory
FR2971885A1 (fr) * 2011-02-18 2012-08-24 Commissariat Energie Atomique Procédé de réalisation d'un support de substrat
US20140199823A1 (en) * 2011-06-10 2014-07-17 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
JP6009226B2 (ja) * 2011-06-10 2016-10-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2013084715A (ja) * 2011-10-07 2013-05-09 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
FR2995445B1 (fr) * 2012-09-07 2016-01-08 Soitec Silicon On Insulator Procede de fabrication d'une structure en vue d'une separation ulterieure
US9224474B2 (en) 2013-01-09 2015-12-29 Macronix International Co., Ltd. P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals
US9171636B2 (en) 2013-01-29 2015-10-27 Macronix International Co. Ltd. Hot carrier generation and programming in NAND flash
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
JP2017224676A (ja) * 2016-06-14 2017-12-21 株式会社ジャパンディスプレイ 半導体装置及び表示装置
CN110085550A (zh) * 2018-01-26 2019-08-02 沈阳硅基科技有限公司 一种半导体产品用绝缘层结构及其制备方法
FR3091010B1 (fr) 2018-12-24 2020-12-04 Soitec Silicon On Insulator Structure de type semi-conducteur pour applications digitales et radiofréquences, et procédé de fabrication d’une telle structure
US11030426B2 (en) * 2019-10-24 2021-06-08 Asianlink Technology Incorporation Electronic book for detecting page codes by using wireless radio-frequency technology

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738435B2 (ja) * 1986-06-13 1995-04-26 松下電器産業株式会社 半導体装置の製造方法
JP3277403B2 (ja) * 1993-03-26 2002-04-22 ソニー株式会社 Ｓｏｉ基板のｍｏｓトランジスタの製造方法
US6191007B1 (en) 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JPH11111839A (ja) * 1997-10-01 1999-04-23 Denso Corp 半導体基板およびその製造方法
JPH1145862A (ja) 1997-07-24 1999-02-16 Denso Corp 半導体基板の製造方法
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JPH1174208A (ja) * 1997-08-27 1999-03-16 Denso Corp 半導体基板の製造方法
JPH11317506A (ja) * 1998-05-01 1999-11-16 Nippon Steel Corp 半導体装置及びその製造方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6380019B1 (en) * 1998-11-06 2002-04-30 Advanced Micro Devices, Inc. Method of manufacturing a transistor with local insulator structure
JP4507395B2 (ja) * 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
KR100511656B1 (ko) * 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US6759277B1 (en) * 2003-02-27 2004-07-06 Sharp Laboratories Of America, Inc. Crystalline silicon die array and method for assembling crystalline silicon sheets onto substrates
US6864149B2 (en) * 2003-05-09 2005-03-08 Taiwan Semiconductor Manufacturing Company SOI chip with mesa isolation and recess resistant regions
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JP4540359B2 (ja) * 2004-02-10 2010-09-08 シャープ株式会社 半導体装置およびその製造方法
US7115463B2 (en) * 2004-08-20 2006-10-03 International Business Machines Corporation Patterning SOI with silicon mask to create box at different depths
JP2006210899A (ja) * 2004-12-28 2006-08-10 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウェーハ
JP4261532B2 (ja) 2005-09-13 2009-04-30 株式会社東芝 論理ディスク管理方法及び仮想化装置
US7288458B2 (en) * 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
US8629490B2 (en) * 2006-03-31 2014-01-14 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor storage device with floating gate electrode and control gate electrode
US7846817B2 (en) * 2007-03-26 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
EP1975998A3 (en) * 2007-03-26 2013-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a plurality of island-shaped SOI structures

Also Published As

Publication number Publication date
US7811884B2 (en) 2010-10-12
US20080242051A1 (en) 2008-10-02
US7972935B2 (en) 2011-07-05
EP1975998A3 (en) 2013-12-04
JP2008270775A (ja) 2008-11-06
US20100311222A1 (en) 2010-12-09
US20100120226A1 (en) 2010-05-13
US7682931B2 (en) 2010-03-23
EP1975998A2 (en) 2008-10-01

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