KR20080039542A - 강유전체 메모리 장치 및 그 제조 방법, 반도체 장치의제조 방법 - Google Patents
강유전체 메모리 장치 및 그 제조 방법, 반도체 장치의제조 방법 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
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Abstract
Description
Claims (8)
- 강유전체 메모리 장치의 제조 방법으로서,트랜지스터가 형성된 반도체 기판 위에, 상기 트랜지스터를 덮도록 층간 절연막을 형성하는 공정과,상기 층간 절연막 중에, 상기 트랜지스터의 확산 영역에 컨택트하는 도전성의 컨택트 플러그를 형성하는 공정과,상기 컨택트 플러그 위에, 하부 전극과 강유전체막과 상부 전극을 순차적으로 적층하여 강유전체 커패시터를 형성하는 공정을 포함하고,상기 컨택트 플러그를 형성하는 공정 후, 상기 하부 전극을 형성하는 공정 전에, 상기 층간 절연막 및 상기 컨택트 플러그의 표면을 OH기로 종단하는 공정과,상기 OH기로 종단된 상기 층간 절연막 및 상기 컨택트 플러그의 표면에, Si와 산소와 CH기를 포함하는 층을, 분자 중에 Si 원자와 CH기를 포함하는 Si 화합물을 도포함으로써 형성하는 공정과,상기 Si와 산소와 CH기를 포함하는 층 중의 CH기를, 적어도 그 표면에 있어서 질소 원자에 의해 치환하여, 상기 Si와 산소와 CH기를 포함하는 층을, 표면에 있어서 질소를 포함하는 층으로 변환하는 공정과, 상기 질소를 포함하는 표면 위에 자기 배향성을 갖는 막을 형성하는 공정을 더 포함하는 것을 특징으로 하는 강유전체 메모리 장치의 제조 방법.
- 제1항에 있어서,상기 Si 화합물로서, 헥사메틸디실라잔을 사용하는 것을 특징으로 하는 강유전체 메모리 장치의 제조 방법.
- 제1항에 있어서,상기 산소를 포함하는 층을 형성하는 공정은, 상기 층간 절연막 및 상기 컨택트 플러그의 표면에, 산소 라디칼 및 수소 라디칼 또는 OH 라디칼을 작용시켜 상기 층간 절연막 및 컨택트 플러그의 표면을 OH 종단하는 공정을 포함하는 것을 특징으로 하는 강유전체 메모리 장치의 제조 방법.
- 제1항에 있어서,상기 CH기를 질소 원자에 의해 치환하는 공정은, 상기 Si와 산소와 CH기를 포함하는 층의 표면에 NH 라디칼 또는 질소 라디칼과 수소 라디칼을 작용시키는 것을 특징으로 하는 강유전체 메모리 장치의 제조 방법.
- 제1항에 있어서,상기 자기 배향성을 갖는 막을 형성하는 공정은, 300℃ 이하의 온도에서 실행되는 것을 특징으로 하는 강유전체 메모리 장치의 제조 방법.
- 제5항에 있어서,상기 자기 배향성을 갖는 막을 형성하는 공정은, Ti막을 스퍼터링에 의해 퇴적하는 공정으로 이루어지는 것을 특징으로 하는 강유전체 메모리 장치의 제조 방법.
- 기능막을 갖는 반도체 장치의 제조 방법으로서,트랜지스터가 형성된 반도체 기판 위에, 상기 트랜지스터를 덮도록 층간 절연막을 형성하는 공정과,상기 층간 절연막 중에, 상기 트랜지스터의 확산 영역에 컨택트하는 도전성의 컨택트 플러그를 형성하는 공정과,상기 컨택트 플러그 위에, 기능막을 형성하는 공정을 포함하고,상기 컨택트 플러그를 형성하는 공정 후, 상기 기능막을 형성하는 공정 전에, 상기 층간 절연막 및 상기 컨택트 플러그의 표면을 OH기로 종단하는 공정과, 상기 OH기로 종단된 상기 층간 절연막 및 상기 컨택트 플러그의 표면에, Si와 산소와 CH기를 포함하는 층을, 분자 중에 Si 원자와 CH기를 포함하는 Si 화합물을 도포함으로써 형성하는 공정과, 상기 Si와 산소와 CH기를 포함하는 층 중의 CH기를, 적어도 그 표면에 있어서 질소에 의해 치환하여, 상기 Si와 산소와 CH기를 포함하는 층을, 표면에 있어서 질소를 포함하는 층으로 변환하는 공정과, 상기 질소를 포함하는 표면 위에 자기 배향성을 갖는 막을 형성하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 반도체 기판과,상기 반도체 기판 위에 형성된, 제1 및 제2 확산 영역을 포함하는 전계 효과 트랜지스터와,상기 반도체 기판 위에, 상기 전계 효과 트랜지스터를 덮도록 형성된 층간 절연막과,상기 층간 절연막 중에 형성되어, 상기 제1 확산 영역과 컨택트하는 도전성 플러그와,상기 층간 절연막 위에, 상기 도전성 플러그에 컨택트하여 형성되는 강유전체 커패시터로 이루어지는 강유전체 메모리 장치로서,상기 강유전체 커패시터는 강유전체막과, 강유전체막을 상하에 협지(挾持)하는 상부 전극 및 하부 전극으로 이루어지며, 상기 하부 전극은 상기 도전성 플러그에 전기적으로 접속되어 있고,상기 도전성 플러그와 상기 하부 전극의 사이에는, 탄소와 수소를 포함하는 SiON막이 개재하고,상기 SiON막과 상기 하부 전극의 사이에는, 자기 배향성을 갖는 물질로 이루어지는 자기 배향층이 개재하는 것을 특징으로 하는 강유전체 메모리 장치.
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DE102007020258B4 (de) * | 2007-04-30 | 2018-06-28 | Globalfoundries Inc. | Technik zur Verbesserung des Transistorleitungsverhaltens durch eine transistorspezifische Kontaktgestaltung |
US8021514B2 (en) * | 2007-07-11 | 2011-09-20 | Applied Materials, Inc. | Remote plasma source for pre-treatment of substrates prior to deposition |
JP2009135216A (ja) * | 2007-11-29 | 2009-06-18 | Nec Electronics Corp | 半導体装置 |
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US8889478B2 (en) * | 2010-11-19 | 2014-11-18 | Panasonic Corporation | Method for manufacturing nonvolatile semiconductor memory element, and nonvolatile semiconductor memory element |
US20140110838A1 (en) * | 2012-10-22 | 2014-04-24 | Infineon Technologies Ag | Semiconductor devices and processing methods |
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US20170092753A1 (en) * | 2015-09-29 | 2017-03-30 | Infineon Technologies Austria Ag | Water and Ion Barrier for III-V Semiconductor Devices |
US10062630B2 (en) | 2015-12-31 | 2018-08-28 | Infineon Technologies Austria Ag | Water and ion barrier for the periphery of III-V semiconductor dies |
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US4992306A (en) * | 1990-02-01 | 1991-02-12 | Air Products Abd Chemicals, Inc. | Deposition of silicon dioxide and silicon oxynitride films using azidosilane sources |
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