KR20070067379A - Stack type package - Google Patents

Stack type package Download PDF

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Publication number
KR20070067379A
KR20070067379A KR1020050128610A KR20050128610A KR20070067379A KR 20070067379 A KR20070067379 A KR 20070067379A KR 1020050128610 A KR1020050128610 A KR 1020050128610A KR 20050128610 A KR20050128610 A KR 20050128610A KR 20070067379 A KR20070067379 A KR 20070067379A
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South Korea
Prior art keywords
sub
chips
package
molding layer
contact hole
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KR1020050128610A
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Korean (ko)
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KR100818083B1 (en
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정종서
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주식회사 하이닉스반도체
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Priority to KR1020050128610A priority Critical patent/KR100818083B1/en
Publication of KR20070067379A publication Critical patent/KR20070067379A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

A stack type package is provided to form a stack package with a smaller thickness and a high density by forming a contact hole in a molding layer to make the contact hole come in contact with an inner lead and by filling a conductive member in the contact hole. In a sub stack package, a plurality of chips(111) are stacked on and under a leadframe(112). The inner lead of the leadframe is wire-bonded to the plurality of chips. A molding layer(114) is formed on the leadframe to protect the plurality of chips and the wire(113) from the outside. A contact hole is formed in the molding layer to expose the inner lead to the outside. A conductive member(116) is filled in the contact hole. A plurality of sub chips are mounted on the sub stack package. Each sub chip is electrically connected to the conductive member by a sub wire. The plurality of sub chips and the sub wire are sealed by a sub molding layer. The contact hole can be formed in at least one of the upper or the lower portion of the molding layer.

Description

적층형 패키지{Stack type package}Stack type package

도 1a 및 도 1b는 종래 적층형 패키지를 나타낸 단면도,1a and 1b is a cross-sectional view showing a conventional stacked package,

도 2는 본 발명의 일 실시예에 따른 서브 스택 패키지를 나타낸 단면도,2 is a cross-sectional view showing a sub stack package according to an embodiment of the present invention;

도 3은 도 2의 서브 스택 패키지를 이용한 적층형 패키지를 나타낸 단면도,3 is a cross-sectional view illustrating a stacked package using the sub stack package of FIG. 2;

도 4는 도 2의 서브 스택 패키지를 이용한 또 다른 적층형 패키지를 나타낸 단면도.4 is a cross-sectional view illustrating another stacked package using the sub stack package of FIG. 2.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100... 적층형 패키지 110... 서브 스택 패키지100 ... Stackable Package 110 ... Sub-Stack Package

111... 칩 112... 리드 프레임111 ... chip 112 ... lead frame

113... 와이어 114... 몰딩층113 ... wire 114 ... molding layer

115... 콘택홀 116... 전도성 부재115 ... contact hole 116 ... conductive member

본 발명은 적층형 패키지에 관한 것으로서, 특히 전체 두께가 얇으면서 높은 밀도를 가진 적층형 패키지에 관한 것이다.TECHNICAL FIELD The present invention relates to stacked packages, and more particularly, to stacked packages having a high overall density and thinness.

반도체 패키지는 웨이퍼 공정에 의해 만들어진 개개의 다이를 실제 전자 부 품으로써 사용할 수 있도록 전기적 연결을 해주고, 외부의 충격으로부터 보호되도록 밀봉 포장한 것을 말하며, 최근 고용량, 고집적, 초소형화된 반도체 제품에 대한 요구에 부응하기 위해 다양한 반도체 패키지들이 개발되고 있다.The semiconductor package is a sealed package that is electrically connected to each die made by the wafer process to be used as an actual electronic component, and is protected from external shock. Recently, a demand for high capacity, high density, and miniaturized semiconductor products is required. To meet this demand, various semiconductor packages are being developed.

이러한 반도체 패키지 중 칩의 덴서티를 높이기 위하여 도 1a와 같이 칩(11)을 다수개 적층하는 적층형 패키지(10)와, 도 1b와 같이 패키지(20a)를 다수개 적층하는 적층형 패키지(20)가 출현하였다.Among these semiconductor packages, a stacked package 10 for stacking a plurality of chips 11 as shown in FIG. 1A and a stacked package 20 for stacking a plurality of packages 20a as shown in FIG. Appeared.

그런데, 칩(11)을 다수개 적층하는 적층형 패키지(10)의 경우 적층된 칩(11) 각각과 리드 프레임(12) 사이의 와이어(13) 본딩 시, 다수의 와이어(13) 사이에 쇼트 등이 발생되어 적층되는 칩(11)의 수가 제한되어 높은 덴서티(density)를 얻는데 한계가 있는 문제점이 있고, 다수의 패키지(20a)를 적층하여 적층형 패키지(20)의 경우, 덴서티 향상에 한계는 없으나 초소형화되어 가는 추세에 반하게 적층형 패키지(20)의 두께가 증가되어 대형화되는 문제점이 있다.However, in the case of the stacked package 10 in which a plurality of chips 11 are stacked, when a wire 13 is bonded between each of the stacked chips 11 and the lead frame 12, a short is formed between the plurality of wires 13. There is a problem in that the number of chips 11 that are generated and stacked is limited to obtain a high density, and in the case of the stacked package 20 by stacking a plurality of packages 20a, there is a limitation in improving the density. However, there is a problem in that the thickness of the stacked package 20 is increased due to an increase in the size of the micro package.

미설명 부호 14,24는 몰딩층, 21은 칩, 22는 리드 프레임, 23은 와이어이다.Reference numerals 14 and 24 denote molding layers, 21 chips, 22 lead frames, and 23 wires.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 패키지의 두께 증가를 억제하면서, 높은 덴서티를 얻을 수 있는 개선된 적층형 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an improved laminated package which can obtain a high density while suppressing an increase in the thickness of the package.

상기의 목적을 달성하기 위한 본 발명의 적층형 패키지는, 리드 프레임 상하에 다수의 칩이 적층되고, 상기 리드 프레임의 이너 리드와 상기 다수의 칩 각각이 와이어 본딩되며, 상기 다수의 칩과 상기 와이어를 외부로부터 보호하기 위하여 상기 리드 프레임 상에 마련된 몰딩층 및 상기 이너 리드가 외부로 노출되도록 상기 몰딩층에 콘택홀이 형성된 서브 스택 패키지; 상기 콘택홀에 충진된 전도성 부재; In the stacked package of the present invention for achieving the above object, a plurality of chips are stacked above and below a lead frame, the inner lead of the lead frame and each of the plurality of chips are wire bonded, and the plurality of chips and the wires are A sub-stack package in which a contact hole is formed in the molding layer so that the molding layer and the inner lead are exposed to the outside so as to be protected from the outside; A conductive member filled in the contact hole;

상기 서브 스택 패키지 상에 실장된 다수의 서브 칩; 상기 다수의 서브 칩 각각과 상기 전도성 부재를 전기적으로 연결하는 서브 와이어; 및 상기 다수의 서브 칩과 상기 서브 와이어를 밀봉하는 서브 몰딩층을 포함한 것이 바람직하다.A plurality of subchips mounted on the sub stack package; A subwire electrically connecting each of the plurality of subchips to the conductive member; And a sub molding layer sealing the plurality of sub chips and the sub wires.

여기서, 상기 콘택홀은 상기 몰딩층의 상부 및 하부 중 적어도 어느 한 측에는 형성된 것이 바람직하다.Here, the contact hole is preferably formed on at least one side of the upper and lower portions of the molding layer.

또한, 상기 다수의 서브 칩은 상기 서브 스택 패키지의 상부 및 하부 중 적어도 어느 한 측에는 적층된 것이 바람직하다.In addition, the plurality of sub-chips are preferably stacked on at least one side of the top and bottom of the sub stack package.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 서브 스택 패키지를 나타낸 단면도이고, 도 3은 도 2의 서브 스택 패키지를 이용한 적층형 패키지를 나타낸 단면도이고, 도 3은 도 2의 서브 스택 패키지를 이용한 또 다른 적층형 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a sub stack package according to an embodiment of the present invention, FIG. 3 is a cross-sectional view illustrating a stacked package using the sub stack package of FIG. 2, and FIG. 3 is still another view using the sub stack package of FIG. 2. A cross-sectional view showing a stacked package.

도면을 참조하면, 적층형 패키지(100)는 서브 스택 패키지(110)와, 전도성 부재(115)와, 다수의 서브 칩(111a)과 다수의 서브 와이어(113a) 및 서브 몰딩층(114a)을 포함한다.Referring to the drawings, the stacked package 100 includes a sub stack package 110, a conductive member 115, a plurality of sub chips 111a, a plurality of sub wires 113a, and a sub molding layer 114a. do.

서브 스택 패키지(110)는 다수의 칩이 리드 프레임 상하에 적층된 칩 적층 패키지의 일종으로, 리드 프레임(112)과, 이 리드 프레임(112) 상하부에 적층된 다수의 칩(111)과, 리드 프레임(112)과 다수의 칩(111) 각각을 연결하는 와이어(113) 및 다수의 칩(111)과 와이어(113)를 외부로부터 보호하기 위하여 리드 프레임(112) 상에 마련된 몰딩층(114)을 포함한다.The sub stack package 110 is a type of chip stack package in which a plurality of chips are stacked above and below a lead frame, and includes a lead frame 112, a plurality of chips 111 stacked above and below the lead frame 112, and leads. Wire 113 connecting the frame 112 and each of the plurality of chips 111 and a molding layer 114 provided on the lead frame 112 to protect the plurality of chips 111 and the wires 113 from the outside. It includes.

여기서, 몰딩층(114)에는 리드 프레임(112)의 이너 리드(112a)가 노출되도록 콘택홀(115)이 형성된다.Here, the contact hole 115 is formed in the molding layer 114 to expose the inner lead 112a of the lead frame 112.

이 콘택홀(115)은 리드 프레임(112) 상부의 몰딩층(114)에만 형성될 수도 있고, 상부 및 하부 양 방향에 형성될 수도 있다.The contact hole 115 may be formed only in the molding layer 114 on the lead frame 112 or may be formed in both upper and lower directions.

이 콘택홀(115)에는 전도성 부재(116)가 충진된 후, 경화된다.The contact hole 115 is filled with a conductive member 116 and then cured.

다수의 서브 칩(111a)은 서브 스택 패키지(110)의 몰딩층(114) 상에 실장되는데, 이때 몰딩층(114) 상부 또는 하부에만 실장될 수도 있고, 상부 및 하부 양측에 모두 실장될 수도 있다.The plurality of sub-chips 111a may be mounted on the molding layer 114 of the sub stack package 110, and may be mounted only on or under the molding layer 114, or may be mounted on both top and bottom sides thereof. .

상하부 양측에 다수의 서브 칩(111a)이 실장되기 위하여는 콘택홀(115)이 몰딩층(114) 상하부에 모두 형성된 후, 이 콘택홀(115) 모두에 전도성 부재(116)가 충진 경화되어야 한다.In order for the plurality of sub-chips 111a to be mounted on both upper and lower sides, the contact holes 115 are formed at both the upper and lower parts of the molding layer 114, and then the conductive members 116 are filled and cured in all of the contact holes 115. .

그리고 서브 와이어(113a)는 서브 스택 패키지(110) 상에 실장된 다수의 서브 칩(111a)과 콘택홀(115)을 전기적으로 연결하기 위한 것이다.The sub wire 113a is for electrically connecting the plurality of sub chips 111a and the contact holes 115 mounted on the sub stack package 110.

서브 몰딩층(114a)은 서브 스택 패키지(110) 상에 실장된 다수의 서브 칩(111a)과 다수의 서브 와이어(113a)를 외부 환경으로부터 보호하기 위하여 서브 스택 패키지(110)의 몰딩층(114) 상에 마련된다.The sub molding layer 114a may include the molding layer 114 of the sub stack package 110 to protect the plurality of sub chips 111a and the plurality of sub wires 113a mounted on the sub stack package 110 from an external environment. ) Is provided.

이와 같은 구조의 적층형 패키지(100)에 의하면, 서브 스택 패키지(110)에 포함된 다수의 칩(111)과, 이 서브 스택 패키지(110) 상에 실장된 다수의 서브 칩(111a)에 의하여 칩의 덴서티를 높일 수 있을 뿐만 아니라, 종래와 같이 칩의 덴서티 증가에 비례하여 패키지의 두께가 증가되던 것을, 칩의 덴서티 대비 전체적인 적층형 패키지의 두께를 줄일 수 있게 된다.According to the stacked package 100 having such a structure, a plurality of chips 111 included in the sub stack package 110 and a plurality of sub chips 111a mounted on the sub stack package 110 are used. In addition to increasing the density of the package, the thickness of the package is increased in proportion to the increase of the chip's density as in the prior art, thereby reducing the thickness of the overall stacked package compared to the chip's.

상술한 바와 같이 본 발명의 적층형 패키지에 의하면, 이너 리드와 콘택되도록 몰딩층에 콘택홀을 형성한 후, 이 콘택홀에 전도성 부재를 충진시켜 전기적 연결을 함으로써, 칩 스택 적층형 패키지와 패키지 스택 적층형 패키지의 혼합에 의해 전체적인 두께의 소폭 증가와 더불어 높은 칩 덴서티를 얻을 수 있는 효과를 제공한다.As described above, according to the stacked package of the present invention, a chip stack stacked package and a package stack stacked package are formed by forming a contact hole in the molding layer to be in contact with the inner lead, and then filling the contact hole with an electrical member to make an electrical connection. By mixing, a small increase in the overall thickness and a high chip density can be obtained.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (3)

리드 프레임 상하에 다수의 칩이 적층되고, 상기 리드 프레임의 이너 리드와 상기 다수의 칩 각각이 와이어 본딩되며, 상기 다수의 칩과 상기 와이어를 외부로부터 보호하기 위하여 상기 리드 프레임 상에 마련된 몰딩층 및 상기 이너 리드가 외부로 노출되도록 상기 몰딩층에 콘택홀이 형성된 서브 스택 패키지; A plurality of chips stacked above and below the lead frame, the inner lead of the lead frame and each of the plurality of chips are wire bonded, and a molding layer provided on the lead frame to protect the plurality of chips and the wires from the outside; A sub-stack package in which contact holes are formed in the molding layer so that the inner lead is exposed to the outside; 상기 콘택홀에 충진된 전도성 부재; A conductive member filled in the contact hole; 상기 서브 스택 패키지 상에 실장된 다수의 서브 칩; A plurality of subchips mounted on the sub stack package; 상기 다수의 서브 칩 각각과 상기 전도성 부재를 전기적으로 연결하는 서브 와이어; 및 A subwire electrically connecting each of the plurality of subchips to the conductive member; And 상기 다수의 서브 칩과 상기 서브 와이어를 밀봉하는 서브 몰딩층을 포함한 것을 특징으로 하는 적층형 패키지.And a sub-molding layer sealing the plurality of sub-chips and the sub-wires. 제1항에 있어서,The method of claim 1, 상기 콘택홀은 상기 몰딩층의 상부 및 하부 중 적어도 어느 한 측에는 형성된 것을 특징으로 하는 적층형 패키지.The contact hole is a laminated package, characterized in that formed on at least one side of the top and bottom of the molding layer. 제1항에 있어서,The method of claim 1, 상기 다수의 서브 칩은 상기 서브 스택 패키지의 상부 및 하부 중 적어도 어느 한 측에는 적층된 것을 특징으로 하는 적층형 패키지.And the plurality of sub-chips are stacked on at least one side of an upper side and a lower side of the sub stack package.
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KR101455749B1 (en) * 2007-08-23 2014-11-04 삼성전자주식회사 Semiconductor Chip Stack Type Package and Method of Fabricating the Same
WO2015017959A1 (en) * 2013-08-06 2015-02-12 Jiangsu Changjiang Electronics Technology Co., Ltd First-packaged and later-etched three-dimensional flip-chip system-in-package structure and processing method therefor

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KR19990060952A (en) * 1997-12-31 1999-07-26 김영환 Semiconductor package
KR100600213B1 (en) * 2000-08-14 2006-07-13 앰코 테크놀로지 코리아 주식회사 Semiconductor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101455749B1 (en) * 2007-08-23 2014-11-04 삼성전자주식회사 Semiconductor Chip Stack Type Package and Method of Fabricating the Same
WO2015017959A1 (en) * 2013-08-06 2015-02-12 Jiangsu Changjiang Electronics Technology Co., Ltd First-packaged and later-etched three-dimensional flip-chip system-in-package structure and processing method therefor

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