KR20080074662A - Stack package - Google Patents

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Publication number
KR20080074662A
KR20080074662A KR1020070014056A KR20070014056A KR20080074662A KR 20080074662 A KR20080074662 A KR 20080074662A KR 1020070014056 A KR1020070014056 A KR 1020070014056A KR 20070014056 A KR20070014056 A KR 20070014056A KR 20080074662 A KR20080074662 A KR 20080074662A
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South Korea
Prior art keywords
printed circuit
circuit board
semiconductor chip
substrate
stack package
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Application number
KR1020070014056A
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Korean (ko)
Inventor
황찬기
이승호
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주식회사 하이닉스반도체
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Priority to KR1020070014056A priority Critical patent/KR20080074662A/en
Publication of KR20080074662A publication Critical patent/KR20080074662A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A stack package is provided to prevent the defect of a wire bonding by stacking center pad type semiconductor chips using a substrate for a rewire. A lead frame includes a die paddle(100), an inner lead, and an outer lead. A printed circuit board(102) is attached to the die paddle. Electrode terminals are formed at both edges of the printed circuit board. At least two center pad type semiconductor chips(108) are stacked on an upper surface of the printed circuit board. A substrate(112) for a rewire is attached to each semiconductor chip and has a circuit pattern. A side of the circuit pattern is electrically connected to a bonding pad of the semiconductor chip. A first metal wire(114) connects the other side of the circuit pattern of the substrate for a rewire to the electrode terminal of the printed circuit board. A second metal wire(118) electrically connects the inner lead of the lead frame to the electrode terminal of the printed circuit board. A sealing member(122) seals a spatial region including the stacked semiconductor chip, the first and second metal wires, the substrate for a rewire, the dia paddle, and an inner lead of the lead frame.

Description

스택 패키지{Stack package}Stack package

도 1은 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a stack package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 다이 패들 102 : 인쇄회로기판100: die paddle 102: printed circuit board

104 : 전극 단자 106 : WBL(Wafer backside lamination) 테입104: electrode terminal 106: wafer backside lamination (WBL) tape

108 : 반도체칩 110 : 스페이서 테입108: semiconductor chip 110: spacer tape

112 : 재배선용 기판 114 : 제1금속와이어112: substrate for redistribution 114: first metal wire

116 : 범프 118 : 제2금속와이어116: bump 118: second metal wire

120 : 리드 122 : 봉지제120: lead 122: sealing agent

H : 홈  H: home

본 발명은 스택 패키지에 관한 것으로, 보다 자세하게는, 스택 패키지 구현시 와이어본딩 길이를 최소화시킨 스택 패키지에 관한 것이다.The present invention relates to a stack package, and more particularly, to a stack package that minimizes wirebonding length when implementing a stack package.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨데, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and the mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. In addition, as miniaturization of electric and electronic products and high performance is required, various technologies for providing a high capacity semiconductor module have been researched and developed.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of a semiconductor chip.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(stack) 기술이 제안되었다. However, the high integration of such a memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

상기와 같은 스택기술은 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 2개의 단품의 패키지를 스택하는 방법이 있다. 그러나, 상기와 같이 2개의 단품의 패키지를 스택하는 방법은 전기·전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이의 한계가 있다.Such a stacking technique includes a method of embedding two stacked chips in one package and stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

따라서, 하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 적층 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근 들어 활발하게 진행되고 있다. Therefore, research on a stack package and a multi chip package in which two or three semiconductor chips of one package are mounted has been actively conducted in recent years.

여기서, 상기 멀티 칩 패키지는, 통상, 여러개의 반도체 칩들을 기판 상에 단순 나열하여 패키징하는 방법과 두 개 이상의 반도체 칩들을 적층 구조로 쌓아 올려 패키징하는 방법이 있다. Here, the multi-chip package generally includes a method of simply arranging and packaging a plurality of semiconductor chips on a substrate, and a method of packaging two or more semiconductor chips in a stacked structure.

그러나, 자세하게 도시하고 설명하지는 않았지만, 상기와 같이 두 개 이상의 반도체 칩들을 적층구조로 쌓아 올려 패키징을 하게 되면, 전기 전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이에 한계가 발생하며, 스택 패키지의 목적과 부합되지 않게 된다.However, although not shown and described in detail, when packaging two or more semiconductor chips in a stacked structure as described above, there is a limit in the height of the semiconductor package according to the trend of miniaturization of electrical and electronic products, and stacking This does not match the purpose of the package.

또한, 에지패드 형의 반도체칩이 아닌 센터패드 형의 반도체칩을 상기와 같은 적층구조로 쌓아 올려 패키징을 하게 되면, 전기적 연결을 이루는 상기 반도체칩의 금속와이어와 인쇄회로기판의 전극단자간의 이격거리가 적층되는 반도체칩의 갯수 만큼 증가하게 되어 와이어본딩시 그에 따른 작업상의 불량이 발생하게 된다.In addition, when the center pad-type semiconductor chip, not the edge pad-type semiconductor chip, is stacked and packaged as described above, the separation distance between the metal wire of the semiconductor chip and the electrode terminal of the printed circuit board, which are electrically connected, are packaged. Is increased by the number of stacked semiconductor chips, resulting in operational defects during wire bonding.

따라서, 본 발명은 높이를 감소시킨 스택 패키지를 제공한다.Thus, the present invention provides a stack package with reduced height.

또한, 본 발명은 와이어본딩길이를 감소시킨 스택 패키지를 제공한다.The present invention also provides a stack package with reduced wire bonding length.

일 실시예에 있어서, 스택 패키지는, 다이 패들과 인너리드 및 아우터리드를 포함하는 리드프레임; 상기 다이 패들 상에 부착되며, 양측 가장자리에 전극단자가 구비된 인쇄회로기판; 상기 인쇄회로기판의 상면에 스택된 적어도 둘 이상의 센터패드형 반도체칩; 상기 각 반도체칩 상에 부착되며, 일측이 반도체칩의 본딩패드와 전기적으로 연결되는 회로패턴을 구비한 재배선용 기판; 상기 재배선용 기판의 회로패턴 타측과 인쇄회로기판의 전극단자를 연결하는 제1금속와이어; 상기 리드프레임의 인너리드와 인쇄회로기판의 전극단자 간을 전기적으로 연결하는 제2금속와이 어; 및 상기 스택된 반도체칩, 제1 및 제2금속와이어 및 재배선용 기판과 리드프레임의 다이 패들 및 인너리드를 포함한 공간적 영역을 밀봉하는 봉지제;를 포함한다.In one embodiment, a stack package comprises: a leadframe comprising a die paddle and an inner lead and an outer lead; A printed circuit board attached to the die paddle and having electrode terminals at both edges thereof; At least two center pad type semiconductor chips stacked on an upper surface of the printed circuit board; A redistribution board attached to each of the semiconductor chips and having a circuit pattern on one side thereof electrically connected to a bonding pad of the semiconductor chip; A first metal wire connecting the other side of the circuit pattern of the redistribution board and the electrode terminal of the printed circuit board; A second metal wire electrically connecting an inner lead of the lead frame and an electrode terminal of a printed circuit board; And an encapsulant for sealing the spatial region including the stacked semiconductor chip, the first and second metal wires, the redistribution substrate, and the die paddle and the inner lead of the lead frame.

상기 센터패드형 반도체칩은 중앙부에 본딩패드가 2열로 배열된 것을 특징으로 한다.The center pad-type semiconductor chip is characterized in that the bonding pads are arranged in two rows at the center.

상기 인쇄회로기판은 각 반도체칩과 WBL(wafer backside lamination) 테입을 매개로 하여 부착된다.The printed circuit board is attached to each semiconductor chip through a wafer backside lamination (WBL) tape.

상기 각 반도체칩은 각각 WBL(wafer backside lamination) 테입을 매개로 하여 부착된다.Each of the semiconductor chips is attached via a wafer backside lamination (WBL) tape, respectively.

상기 재배선용 기판은 일면에 홈이 구비된다.The rewiring substrate is provided with a groove on one surface.

상기 홈 내에 삽입되어 상기 재배선용 기판을 반도체칩 상에 부착시키는 스페이서 테입을 더 포함한다.And a spacer tape inserted into the groove to attach the redistribution substrate to the semiconductor chip.

(실시예)(Example)

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은, 적어도 둘 이상의 센터패드형의 반도체칩을 적층구조로 스택 시, 인쇄회로기판과 각 반도체칩간을 상기 각 반도체칩 상면에 배치시킨 패턴이 형성되고 일면에 홈이 형성된 적어도 둘 이상의 재배선용 기판을 매개로 전기적으로 연결하여 스택 패키지를 구성한다.According to the present invention, when stacking at least two or more center pad-type semiconductor chips in a stacked structure, at least two or more redistribution lines for forming a pattern in which a printed circuit board and each semiconductor chip are disposed on an upper surface of each semiconductor chip are formed and grooves are formed on one surface thereof. The stack package is formed by electrically connecting the substrate.

이렇게 하면, 상기 재배선용 기판을 사용하여 센터 패드 형의 반도체칩들간 을 스택함으로써, 종래의 센터 패드 형의 스택패키지에서의 긴 와이어본딩에서 발생하는 와이어 본딩의 작업 불량을 방지할 수 있다.In this case, by stacking the center pad semiconductor chips using the redistribution board, it is possible to prevent the work defect of the wire bonding occurring in the long wire bonding in the conventional center pad stack package.

또한, 상기 재배선용 기판 내에 형성된 홈내에 스페이서 테입을 안착시켜 스팩 패키지를 구성함으로써, 그에 따른 전체 패키지의 높이를 감소시킬 수 있어, 반도체칩의 적층 갯수를 증가시킬 수 있다. In addition, by forming a spacer package in a groove formed in the redistribution substrate, the package package can be reduced, thereby reducing the height of the entire package, thereby increasing the number of stacked semiconductor chips.

도 1은 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도로서, 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도시된 바와 같이, 본 발명의 스택 패키지는, 인쇄회로기판 상에 적어도 둘 이상의 본딩패드가 중앙부에 2열로 배치된 센터패드형의 반도체칩이 WBL(wafer backside lamination) 테입을 매개로 부착되며, 상기 각 반도체칩들 사이에는 적어도 둘 이상의 재배선용 기판이 배치되어, 금속와이어 및 범프를 이용하여 인쇄회로기판과 전기적으로 연결된 구조이다.As shown, the stack package of the present invention is a center pad semiconductor chip in which at least two bonding pads are arranged in two rows at the center of the printed circuit board is attached to the wafer via a wafer backside lamination (WBL) tape. At least two redistribution boards are disposed between the semiconductor chips, and are electrically connected to the printed circuit board using metal wires and bumps.

자세하게는, 내부에 회로패턴이 형성되고 일면에 전극단자(104)가 구비된 인쇄회로기판(102) 하면에 반도체칩(108)을 탑재하기 위한 다이 패들(100)이 배치되고, 상기 다이 패들(100)의 양측에는 외부 모듈기판과의 전기적인 연결을 위하여 일부가 인출된 리드프레임의 리드(120)가 형성된다.In detail, a die paddle 100 for mounting the semiconductor chip 108 is disposed on a lower surface of the printed circuit board 102 having a circuit pattern formed therein and an electrode terminal 104 disposed on one surface thereof. Both ends of the lead 100 are formed with leads 120 of a lead frame partially drawn out for electrical connection with an external module substrate.

상기 다이 패들(100)의 상면에는 WBL(wafer backside lamination : 106)을 매개로 적어도 둘 이상의 센터 패드 형의 반도체칩(108)이 부착되며, 상기 반도체칩(108)의 상면의 양측에는 적어도 둘 이상의 재배선용 기판(112)이 배치된다.At least two center pad-type semiconductor chips 108 are attached to the upper surface of the die paddle 100 via WBL (wafer backside lamination) 106, and at least two or more surfaces on both sides of the upper surface of the semiconductor chip 108. The redistribution substrate 112 is disposed.

여기서, 상기 재배선용 기판(112)은 내부에 홈(H)이 형성되며 상기 홈(H) 내 부에는 스페이서 테입(110)이 배치되어 상기 반도체칩(108)과 물리적으로 연결되며, 또한 상기 재배선용 기판(112)은 패턴이 형성되어 반도체칩(108)과 범프(116)를 매개로 전기적 및 물리적으로 연결되고, 상기 패턴을 통하여 인쇄회로기판(102)의 전극 단자(104)와 적어도 하나 이상의 제1금속와이어(114)를 매개로 전기적으로 연결된다.Here, the redistribution substrate 112 has a groove H formed therein, and a spacer tape 110 is disposed inside the groove H to be physically connected to the semiconductor chip 108. The line substrate 112 is formed with a pattern to be electrically and physically connected through the semiconductor chip 108 and the bumps 116, and at least one electrode terminal 104 of the printed circuit board 102 is formed through the pattern. The first metal wire 114 is electrically connected to each other.

또한, 상기 인쇄회로기판(102)의 전극 단자(104)와 상기 리드프레임의 리드(120) 간은 제2금속와이어(118)에 의해 전기적으로 연결되며, 상기 반도체칩(108), 제1 및 제2금속와이어(114, 118) 및 재배선용 기판(112)을 포함한 인쇄회로기판(102)의 일면 및 상기 리드프레임의 일부분인 리드(120)를 포함하는 공간적 영역이 외부의 스트레스로부터 보호하기 위해 EMC(epoxy molding compound)와 같은 봉지제(122)로 밀봉된 구조이다.In addition, between the electrode terminal 104 of the printed circuit board 102 and the lead 120 of the lead frame is electrically connected by a second metal wire 118, the semiconductor chip 108, the first and To protect from external stress a spatial region including one side of the printed circuit board 102 including the second metal wires 114 and 118 and the rewiring substrate 112 and the lead 120 which is part of the lead frame. It is a structure sealed with an encapsulant 122 such as an epoxy molding compound (EMC).

이 경우, 본 발명은 상기 재배선용 기판을 사용하여 센터 패드 형의 반도체칩들간을 스택함으로써, 종래의 센터 패드 형의 스택 패키지에서의 긴 와이어본딩에서 발생하는 와이어 본딩의 작업 불량을 방지할 수 있다.In this case, the present invention can stack the center pad-type semiconductor chips using the redistribution substrate, thereby preventing work defects in wire bonding caused by long wire bonding in a conventional center pad type stack package. .

또한, 상기 재배선용 기판 내에 형성된 홈 내에 스페이서 테입을 안착시켜 스팩 패키지를 구성함으로써, 그에 따른 전체 패키지의 높이를 감소시킬 수 있어, 반도체칩의 적층 갯수를 증가시킬 수 있다.In addition, by forming a spacer package by seating a spacer tape in a groove formed in the redistribution substrate, the height of the entire package can be reduced, thereby increasing the number of stacked semiconductor chips.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

이상에서와 같이 본 발명은, 상기 재배선용 기판을 사용하여 센터 패드 형의 반도체칩들간을 스택함으로써, 긴 와이어본딩에서 발생하는 와이어 본딩의 작업 불량을 방지할 수 있다.As described above, the present invention, by stacking the center pad-type semiconductor chips using the redistribution substrate, it is possible to prevent the operation of the wire bonding caused in the long wire bonding.

또한, 본 발명은 재배선용 기판 내에 형성된 홈 내에 스페이서 테입을 안착시킴으로써, 그에 따른 전체 패키지의 높이를 감소시킬 수 있다In addition, the present invention can reduce the height of the overall package by seating the spacer tape in the groove formed in the redistribution substrate.

따라서, 본 발명은 상기와 같이 전체 패키지의 높이를 감소시킬 수 있어, 반도체칩의 적층 갯수를 증가시킬 수 있다.Therefore, the present invention can reduce the height of the entire package as described above, it is possible to increase the number of stacked semiconductor chips.

Claims (6)

다이 패들과 인너리드 및 아우터리드를 포함하는 리드프레임;A leadframe comprising a die paddle and an inner lead and an outer lead; 상기 다이 패들 상에 부착되며, 양측 가장자리에 전극단자가 구비된 인쇄회로기판;A printed circuit board attached to the die paddle and having electrode terminals at both edges thereof; 상기 인쇄회로기판의 상면에 스택된 적어도 둘 이상의 센터패드형 반도체칩;At least two center pad type semiconductor chips stacked on an upper surface of the printed circuit board; 상기 각 반도체칩 상에 부착되며, 일측이 반도체칩의 본딩패드와 전기적으로 연결되는 회로패턴을 구비한 재배선용 기판; A redistribution board attached to each of the semiconductor chips and having a circuit pattern on one side thereof electrically connected to a bonding pad of the semiconductor chip; 상기 재배선용 기판의 회로패턴 타측과 인쇄회로기판의 전극단자를 연결하는 제1금속와이어;A first metal wire connecting the other side of the circuit pattern of the redistribution board and the electrode terminal of the printed circuit board; 상기 리드프레임의 인너리드와 인쇄회로기판의 전극단자 간을 전기적으로 연결하는 제2금속와이어; 및A second metal wire electrically connecting an inner lead of the lead frame to an electrode terminal of a printed circuit board; And 상기 스택된 반도체칩, 제1 및 제2금속와이어 및 재배선용 기판과 리드프레임의 다이 패들 및 인너리드를 포함한 공간적 영역을 밀봉하는 봉지제;An encapsulant for sealing the spatial region including the stacked semiconductor chip, the first and second metal wires, the redistribution substrate, and the die paddle and inner lead of the lead frame; 를 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 센터패드형 반도체칩은 중앙부에 본딩패드가 2열로 배열된 것을 특징으로 하는 스택 패키지.The center pad-type semiconductor chip is a stack package, characterized in that the bonding pads are arranged in two rows in the center. 제 1 항에 있어서,The method of claim 1, 상기 인쇄회로기판은 각 반도체칩과 WBL(wafer backside lamination) 테입을 매개로 하여 부착되는 것을 특징으로 하는 스택 패키지. The printed circuit board is a stack package, characterized in that attached to each semiconductor chip via a wafer backside lamination (WBL) tape. 제 1 항에 있어서,The method of claim 1, 상기 각 반도체칩은 각각 WBL(wafer backside lamination) 테입을 매개로 하여 부착되는 것을 특징으로 하는 스택 패키지.Each semiconductor chip is attached to each other via a wafer backside lamination (WBL) tape. 제 1 항에 있어서,The method of claim 1, 상기 재배선용 기판은 일면에 홈이 구비된 것을 특징으로 하는 스택 패키지.The redistribution substrate is a stack package, characterized in that the groove is provided on one side. 제 5 항에 있어서,The method of claim 5, wherein 상기 홈 내에 삽입되어 상기 재배선용 기판을 반도체칩 상에 부착시키는 스페이서 테입을 더 포함하는 것을 특징으로 하는 스택 패키지.And a spacer tape inserted into the groove to attach the redistribution substrate to the semiconductor chip.
KR1020070014056A 2007-02-09 2007-02-09 Stack package KR20080074662A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101226809B1 (en) * 2012-07-23 2013-01-25 하나 마이크론(주) Stacked semiconductor Package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101226809B1 (en) * 2012-07-23 2013-01-25 하나 마이크론(주) Stacked semiconductor Package

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