KR20090011969A - Stack package - Google Patents

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Publication number
KR20090011969A
KR20090011969A KR1020070076042A KR20070076042A KR20090011969A KR 20090011969 A KR20090011969 A KR 20090011969A KR 1020070076042 A KR1020070076042 A KR 1020070076042A KR 20070076042 A KR20070076042 A KR 20070076042A KR 20090011969 A KR20090011969 A KR 20090011969A
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South Korea
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semiconductor chips
substrate
pair
stacked
cavity
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KR1020070076042A
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Korean (ko)
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배진호
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주식회사 하이닉스반도체
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Priority to KR1020070076042A priority Critical patent/KR20090011969A/en
Publication of KR20090011969A publication Critical patent/KR20090011969A/en

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A stacked package is provided to prevent the fault of the bonding wire in the stacked package formation and reduce the height of the total package. Two pairs of one-sided bonding pad type semiconductor chips(208a~208d) are integrated on a substrate(202) having a cavity(206). The semiconductor chips are cross-integrated in order to expose the bonding pad. One pair of semiconductor chips which is arranged at the lower part is arranged into the face-down type. One pair of semiconductor chips which is arranged at the lower part is electrically connected to the substrate by a bonding wire(210a) passing through the cavity of substrate. One pair of semiconductor chips which is arranged at the upper part is arranged into the face-up type. One pair of semiconductor chips which is arranged at the upper part is electrically connected to the substrate by a bonding wire(210b) passing through the cavity of substrate.

Description

스택 패키지{STACK PACKAGE}Stack Package {STACK PACKAGE}

본 발명은 스택 패키지에 관한 것으로, 보다 자세하게는, 원-사이드(One-Side) 본딩패드형의 반도체 칩들을 이용한 스택 패키지 형성시 본딩와이어의 불량을 방지함과 아울러, 전체 패키지의 높이를 감소시킨 스택 패키지에 관한 것이다.The present invention relates to a stack package, and more particularly, to prevent a defect of a bonding wire when forming a stack package using one-side bonding pad type semiconductor chips, and to reduce the height of the entire package. It's about a stack package.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨데, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. In addition, as miniaturization of electric and electronic products and high performance is required, various technologies for providing a high capacity semiconductor module have been researched and developed.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of a semiconductor chip.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(stack) 기술이 제안되었다. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

상기와 같은 스택기술은 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 2개의 단품의 패키지를 스택하는 방법이 있다. 그러나, 상기와 같이 2개의 단품의 패키지를 스택하는 방법은 전기·전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이의 한계가 있다.Such a stacking technique includes a method of embedding two stacked chips in one package and stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

따라서, 하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 적층 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근 들어 활발하게 진행되고 있다. Therefore, research on a stack package and a multi chip package in which two or three semiconductor chips of one package are mounted has been actively conducted in recent years.

여기서, 상기 멀티 칩 패키지는, 통상, 여러개의 반도체 칩들을 기판 상에 단순 나열하여 패키징하는 방법과 두 개 이상의 반도체 칩들을 적층 구조로 쌓아 올려 패키징하는 방법이 있다.Here, the multi-chip package generally includes a method of simply arranging and packaging a plurality of semiconductor chips on a substrate, and a method of packaging two or more semiconductor chips in a stacked structure.

이하에서는, 도 1을 참조하여 종래 기술에 따른 스택 패키지에 관해 간략하게 설명하도록 한다.Hereinafter, a stack package according to the related art will be briefly described with reference to FIG. 1.

도시된 바와 같이, 종래 기술에 따른 스택 패키지(100)는, 상면에 전극단자(118)를 구비한 기판(102) 상에 2열의 에지(Edge)형 본딩 패드(도시안됨)를 갖는 반도체 칩들(108a, 108b, 108c, 108d)이 적어도 두 개 이상 페이스-업(Face-Up) 타입으로 스택되어 봉지제로 밀봉된 구조를 갖는다.As shown in the drawing, the stack package 100 according to the related art includes semiconductor chips having two rows of edge bonding pads (not shown) on a substrate 102 having an electrode terminal 118 on an upper surface thereof. At least two 108a, 108b, 108c, and 108d are stacked in a face-up type and have a structure sealed with an encapsulant.

또한, 상기 반도체 칩들(108a, 108b, 108c, 108d)은 상기 기판(102)의 전극단자(118)와 적어도 하나 이상의 본딩와이어(110)를 매개로 전기적으로 연결되며, 이때, 상기 기판(102)과 반도체 칩들(108a, 108b, 108c, 108d) 간의 전기적 연결된 적어도 하나 이상의 본딩와이어(110)간의 쇼트가 발생하지 않도록 스택된 상기 반도체 칩들(108a, 108b, 108c, 108d) 사이에는 스페이서 물질(106)이 삽입 개재되어 형성된다.In addition, the semiconductor chips 108a, 108b, 108c, and 108d are electrically connected to the electrode terminal 118 of the substrate 102 through at least one bonding wire 110. In this case, the substrate 102 A spacer material 106 between the stacked semiconductor chips 108a, 108b, 108c, and 108d such that a short between the at least one bonding wire 110 electrically connected between the semiconductor chips 108a, 108b, 108c, and 108d does not occur. It is formed through insertion.

여기서, 미설명된 도면 부호 116은 외부 접속 단자를 나타낸다.Here, reference numeral 116, which is not described, denotes an external connection terminal.

그러나, 전술한 바와 같은 종래 기술에 따른 스택 패키지는, 상기와 같이 본딩와이어의 손상을 방지하기 위해 스택되는 반도체 칩들 사이에 개재된 스페이서 물질에 의해 스택 패키지의 층을 증가시킬수록, 즉, 스택되는 반도체 칩의 갯수를 증가시킬수록 패키지의 전체 높이가 증가되게 된다.However, the stack package according to the related art as described above is stacked as the layer of the stack package is increased by the spacer material interposed between the stacked semiconductor chips to prevent damage to the bonding wire as described above. As the number of semiconductor chips increases, the overall height of the package increases.

또한, 스택되는 반도체 칩들 간이 전부 페이스-업 타입으로 부착되기 때문에, 반도체 칩 간을 부착하여 스택할 때, 상부 반도체 칩에 의해 하부 반도체 칩의 와이어가 손상될 우려가 있다.In addition, since the stacked semiconductor chips are all attached in a face-up type, when the stacked semiconductor chips are attached and stacked, there is a possibility that the wires of the lower semiconductor chips are damaged by the upper semiconductor chips.

게다가, 상기와 같이 한 쪽 방향으로 여러 개의 와이어를 본딩하면, 에폭시와 같은 봉지제로 패키지 밀봉시 상기 봉지제에 의해 와이어 스위핑(Sweeping)이 발생하여 와이어 간의 단락이 발생하게 된다.In addition, when a plurality of wires are bonded in one direction as described above, when the package is sealed with an encapsulant such as epoxy, wire sweeping occurs by the encapsulant to cause a short circuit between the wires.

아울러, 전술한 바와 같은 에지형의 본딩 패드를 갖는 반도체 칩을 사용하여 스택 패키지를 형성하는 경우 이외의, 반도체 칩이 센터형의 본딩패드를 갖는 반도체 칩을 사용하여 스택 패키지를 형성할 경우에는, 페이스-업 및 페이스-다운 방식으로 스택하여도 2개 이상 스택하기 어렵기 때문에, 2개 이상 스택하고자 할 경우, RDL(Redistribution Layer)와 같은 추가적인 공정이 요구되게 된다.In addition, when the semiconductor chip forms a stack package using a semiconductor chip having a center bonding pad, except that the stack package is formed using a semiconductor chip having an edge-type bonding pad as described above, Since two or more stacks are difficult to stack in the face-up and face-down methods, an additional process such as a redistribution layer (RDL) is required when stacking two or more stacks.

본 발명은, 본딩와이어의 손상을 방지한 스택 패키지를 제공한다.The present invention provides a stack package which prevents damage to the bonding wires.

또한, 본 발명은 패키지의 전체 높이를 감소시킨 스택 패키지를 제공한다.The present invention also provides a stack package with reduced overall height of the package.

본 발명에 따른 스택 패키지는, 캐버티를 갖는 기판; 상기 기판 상에 스택된 두 쌍의 원-사이드(One-Side) 본딩패드형 반도체 칩; 및 상기 스택된 반도체 칩과 상기 기판 간을 전기적으로 연결시키는 본딩와이어;를 포함하며, 상기 스택된 반도체 칩 들은 본딩패드가 노출되게 서로 엇갈려 스택되며, 하부에 배치된 한 쌍의 반도체 칩은 페이스-다운(Face-Down) 타입으로 배치되어 상기 기판의 캐버티를 관통하는 본딩와이어에 의해 상기 기판과 전기적으로 연결되고, 상부에 배치된 한 쌍의 반도체 칩은 페이스-업(Face-Up) 타입으로 배치되어 상기 기판과 전기적으로 연결된다.A stack package according to the present invention includes a substrate having a cavity; Two pairs of one-side bonding pad type semiconductor chips stacked on the substrate; And bonding wires electrically connecting the stacked semiconductor chips to the substrate, wherein the stacked semiconductor chips are stacked alternately with each other to expose a bonding pad, and a pair of semiconductor chips disposed below the face- A pair of semiconductor chips disposed in a face-down type and electrically connected to the substrate by a bonding wire penetrating through the cavity of the substrate, and a pair of semiconductor chips disposed thereon are face-up type. And is electrically connected to the substrate.

상기 기판은 캐버티에 인접한 하면 및 상면에 각각 형성된 제1 및 제2전극단자를 더 포함한다.The substrate further includes first and second electrode terminals respectively formed on a lower surface and an upper surface adjacent to the cavity.

상기 하부에 배치된 한 쌍의 반도체 칩은 상기 기판 하면의 제1전극단자와 본딩와이어에 의해 전기적으로 연결된다.The pair of semiconductor chips disposed on the lower portion of the semiconductor chip may be electrically connected to the first electrode terminal on the lower surface of the substrate by a bonding wire.

상기 상부에 배치된 한 쌍의 반도체 칩은 상기 기판 상면의 제2전극단자와 본딩와이어에 의해 전기적으로 연결된다.The pair of semiconductor chips disposed on the upper portion are electrically connected to the second electrode terminal on the upper surface of the substrate by a bonding wire.

상기 두 쌍의 반도체 칩과 본딩와이어를 포함하는 기판의 상면과 상기 본딩 와이어를 포함한 캐버티 부분을 포함한 기판 하면의 일부분을 밀봉하는 봉지제를 더 포함한다.An encapsulant for sealing an upper surface of the substrate including the two pairs of semiconductor chips and bonding wires and a portion of the lower surface of the substrate including the cavity portion including the bonding wires.

상기 기판은 하면에 형성된 외부접속단자를 더 포함한다.The substrate further includes an external connection terminal formed on the bottom surface.

본 발명은 원-사이드(One-Side)의 본딩패드를 갖는 두 쌍의 반도체 칩을 스택하여 스택 패키지 형성시, 상기 각 쌍의 반도체 칩을 지그재그로 상기 본딩패드가 노출되도록 스택하여 형성한다. 이때, 하부에 배치된 한 쌍의 반도체 칩은 페이스-다운(Face-Down) 타입으로 배치시키고, 상부에 배치된 한 쌍의 반도체 칩은 페이스-업(Face-Up) 타입으로 배치시킨다.The present invention stacks two pairs of semiconductor chips having one-side bonding pads to form a stack package, and stacks the pair of semiconductor chips in a zigzag manner to expose the bonding pads. In this case, the pair of semiconductor chips disposed below is disposed in a face-down type, and the pair of semiconductor chips disposed above are disposed in a face-up type.

이렇게 하면, 본딩와이어의 손상을 방지하기 위해 스택되는 반도체 칩들 사이에 스페이서 물질을 개재시켜 스택 패키지를 형성하는 종래의 스택 패키지와 달리, 각 쌍의 반도체 칩을 지그재그로 상기 본딩패드가 노출되도록 스택하여 형성함으로써, 반도체 칩 간을 부착하여 스택할 때 상부 반도체 칩에 의해 하부 반도체 칩의 와이어의 손상을 방지할 수 있다.In this case, unlike a conventional stack package which forms a stack package by interposing spacer materials between stacked semiconductor chips to prevent damage to the bonding wire, each pair of semiconductor chips are stacked in a zigzag manner so that the bonding pads are exposed. By forming it, it is possible to prevent damage to the wires of the lower semiconductor chip by the upper semiconductor chip when the semiconductor chips are attached and stacked.

또한, 하부 한 쌍의 반도체 칩 및 상부 한 쌍의 반도체 칩을 각각 페이스-다운 및 페이스-업 타입으로 스택함으로써, 종래의 한 쪽 방향으로만 여러 개의 와이어를 본딩함에 따라 에폭시와 같은 봉지제로 패키지 밀봉시 상기 봉지제에 의해 와이어 스위핑(Sweeping)이 발생함에 따른 와이어 간의 단락을 방지할 수 있다.In addition, by stacking the lower pair of semiconductor chips and the upper pair of semiconductor chips into face-down and face-up types, respectively, the package is sealed with an epoxy-like encapsulant by bonding several wires only in one conventional direction. When the wire sweeping (Sweeping) is generated by the encapsulation agent can prevent a short circuit between the wires.

따라서, 상기와 같이 스택되는 반도체 칩들 간의 본딩되는 각각의 와이어들의 손상을 방지함과 아울러 패키지의 전체 높이를 종래보다 감소시킬 수 있다.Therefore, it is possible to prevent damage to respective wires bonded between the semiconductor chips stacked as described above, and to reduce the overall height of the package.

게다가, 원-사이드(One-Side) 본딩패드를 갖는 반도체 칩을 사용하여 스택 패키지를 형성함으로써, 반도체 칩을 적어도 2개 이상 스택하여 스택 패키지를 형성할 경우에도, RDL(Redistribution Layer)와 같은 추가적인 공정이 요구되지 않아도 된다.In addition, by forming a stack package using a semiconductor chip having a one-side bonding pad, even when stacking at least two or more semiconductor chips to form a stack package, an additional layer such as a redistribution layer (RDL) may be used. No process is required.

자세하게, 도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, Figure 2 is a cross-sectional view showing a stack package according to an embodiment of the present invention, as follows.

도시된 바와 같이, 본 발명의 실시예에 따른 스택 패키지(200)는 캐버티(206)를 갖는 기판(202) 상에 두 쌍의 반도체 칩(208a, 208b, 208c, 208d)이, 하부 한 쌍의 반도체 칩(208a, 208b)은 페이스-다운 타입으로 배치되고, 상부 한 쌍의 반도체 칩(208c, 208d)은 페이스-업 타입으로 배치되어 스택된 구조를 갖는다.As shown, the stack package 200 according to the embodiment of the present invention includes two pairs of semiconductor chips 208a, 208b, 208c, and 208d on a substrate 202 having a cavity 206. The semiconductor chips 208a and 208b are arranged in a face-down type, and the upper pair of semiconductor chips 208c and 208d are arranged in a face-up type to have a stacked structure.

여기서, 상기 상부 및 하부에 배치된 각각의 반도체 칩(208a, 208b, 208c, 208d)들은 원-사이드(One-Side) 본딩패드(도시안됨)를 가지며, 상기 원-사이드(One-Side) 본딩패드가 서로 노출되도록 지그재그형으로 스택되며, 이때, 상기 각 반도체 칩(208a, 208b, 208c, 208d)들 간은 추가적인 스페이서 물질 없이 접착제(204)만을 매개로 하여 부착된다.Here, each of the semiconductor chips 208a, 208b, 208c, and 208d disposed on the upper and lower portions has a one-side bonding pad (not shown), and the one-side bonding. The pads are stacked in a zigzag pattern so as to be exposed to each other, wherein the semiconductor chips 208a, 208b, 208c, and 208d are attached to each other only through the adhesive 204 without additional spacer material.

상기 하부에 배치된 한 쌍의 반도체 칩(208a, 208b)은 페이스-다운 타입으로 배치되어, 상기 하부 한 쌍의 반도체 칩(208a, 208b)과 상기 기판(202) 하면에 형성된 제1전극단자(218a) 간이 상기 기판(202)의 캐버티(206)를 관통하도록 하여 제1본딩와이어(210a)를 매개로 전기적으로 연결된다.The pair of semiconductor chips 208a and 208b disposed on the lower portion are disposed in a face-down type, and include a first electrode terminal formed on the lower pair of semiconductor chips 208a and 208b and on a lower surface of the substrate 202. 218a may be electrically connected to each other through the first bonding wire 210a by allowing the cavity 206 to pass through the cavity 206 of the substrate 202.

상기 상부에 배치된 한 쌍의 반도체 칩(208c, 208d)는 페이스-업 타입으로 배치되어, 상기 상부 한 쌍의 반도체 칩(208c,208d)과 상기 기판(202) 상면에 형성된 제2전극단자(218b) 간이 제2본딩와이어(210b)를 매개로 하여 전기적으로 연결된다.The pair of semiconductor chips 208c and 208d disposed on the upper portion are arranged in a face-up type so that the pair of semiconductor chips 208c and 208d and the second electrode terminal formed on the upper surface of the substrate 202 are formed. 218b) The simple connecting wires 210b are electrically connected to each other.

상기 하부 및 상부의 두 쌍의 반도체 칩(208a, 208b, 208c, 208d)과 제2본딩와이어(210b)를 포함하는 기판(202)의 상면과, 제1본딩와이어(210a)를 포함하는 캐버티(206) 부분을 포함하는 기판(202) 하면의 일부분이 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy Molding Compound)와 같은 봉지제(214)로 밀봉된다.A cavity including an upper surface of the substrate 202 including the lower and upper two pairs of semiconductor chips 208a, 208b, 208c, and 208d and the second bonding wire 210b, and a first bonding wire 210a. A portion of the bottom surface of the substrate 202 including the portion 206 is sealed with an encapsulant 214 such as an epoxy molding compound (EMC) to protect it from external stress.

상기 기판(202)의 하면에는 솔더 볼과 같은 외부 접속 단자(216)가 형성된다.An external connection terminal 216 such as solder balls is formed on the bottom surface of the substrate 202.

전술한 바와 같이, 본 발명은 원-사이드(One-Side) 본딩패드를 두 쌍의 반도체 칩을 스택하여 스택 패키지 형성시, 각 쌍의 반도체 칩을 지그재그로 상기 본딩패드가 노출되도록 스택하여 형성함으로써, 반도체 칩 간을 부착하여 스택할 때 상부 반도체 칩에 의해 하부 반도체 칩의 와이어의 손상을 방지할 수 있다.As described above, the present invention is to form a one-side bonding pad by stacking two pairs of semiconductor chips to form a stack package, by stacking each pair of semiconductor chips in a zigzag to expose the bonding pads When the semiconductor chips are attached and stacked, the wires of the lower semiconductor chips may be prevented from being damaged by the upper semiconductor chips.

또한, 하부 한 쌍의 반도체 칩 및 상부 한 쌍의 반도체 칩을 각각 페이스-다운 및 페이스-업 타입으로 스택함으로써, 종래의 한 쪽 방향으로만 여러 개의 와이어를 본딩함에 따라, 에폭시와 같은 봉지제로 패키지 밀봉시 상기 봉지제에 의한 와이어 스위핑(Sweeping)이 발생함에 따른, 본딩되는 와이어 간의 단락을 방지할 수 있다.In addition, by stacking the lower pair of semiconductor chips and the upper pair of semiconductor chips into face-down and face-up types, respectively, by bonding several wires only in one conventional direction, the package is encapsulated with an epoxy-like encapsulant. As the wire sweeping by the encapsulant occurs during sealing, a short circuit between the wires to be bonded may be prevented.

결과적으로, 본딩되는 각각의 와이어들의 손상을 방지함과 아울러 패키지의 전체 높이를 종래보다 감소시킬 수 있다.As a result, it is possible to reduce the overall height of the package as compared to the prior art while preventing damage to each wire to be bonded.

게다가, 원-사이드(One-Side) 본딩패드를 갖는 반도체 칩을 사용하여 스택 패키지를 형성함으로써, 반도체 칩을 적어도 2개 이상 스택하여 스택 패키지를 형성할 경우에도, RDL(Redistribution Layer)과 같은 공정이 추가시키지 않아도 된다.In addition, by forming a stack package using a semiconductor chip having a one-side bonding pad, a process such as a redistribution layer (RDL) may be used even when stacking at least two or more semiconductor chips to form a stack package. You do not have to add this.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 종래기술에 따른 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a stack package according to the prior art.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도.2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

Claims (6)

캐버티를 갖는 기판;A substrate having a cavity; 상기 기판 상에 스택된 두 쌍의 원-사이드(One-Side) 본딩패드형 반도체 칩; 및Two pairs of one-side bonding pad type semiconductor chips stacked on the substrate; And 상기 스택된 반도체 칩과 상기 기판 간을 전기적으로 연결시키는 본딩와이어;Bonding wires electrically connecting the stacked semiconductor chips to the substrate; 를 포함하며, Including; 상기 스택된 반도체 칩 들은 본딩패드가 노출되게 서로 엇갈려 스택되며, The stacked semiconductor chips are stacked alternately with each other to expose a bonding pad, 하부에 배치된 한 쌍의 반도체 칩은 페이스-다운(Face-Down) 타입으로 배치되어 상기 기판의 캐버티를 관통하는 본딩와이어에 의해 상기 기판과 전기적으로 연결되고,The pair of semiconductor chips disposed below is face-down type and is electrically connected to the substrate by a bonding wire penetrating through the cavity of the substrate. 상부에 배치된 한 쌍의 반도체 칩은 페이스-업(Face-Up) 타입으로 배치되어 상기 기판과 전기적으로 연결되는 것을 특징으로 하는 스택 패키지.And a pair of semiconductor chips disposed at an upper portion thereof are arranged in a face-up type to be electrically connected to the substrate. 제 1 항에 있어서,The method of claim 1, 상기 기판은 캐버티에 인접한 하면 및 상면에 각각 형성된 제1 및 제2전극단자를 더 포함하는 것을 특징으로 하는 스택 패키지.The substrate further comprises a first and second electrode terminal formed on the lower surface and the upper surface adjacent to the cavity, respectively. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 하부에 배치된 한 쌍의 반도체 칩은 상기 기판 하면의 제1전극단자와 본딩와이어에 의해 전기적으로 연결된 것을 특징으로 하는 스택 패키지.The pair of semiconductor chips disposed below the stack package is electrically connected to the first electrode terminal on the lower surface of the substrate by a bonding wire. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 상부에 배치된 한 쌍의 반도체 칩은 상기 기판 상면의 제2전극단자와 본딩와이어에 의해 전기적으로 연결된 것을 특징으로 하는 스택 패키지.The pair of semiconductor chips disposed on the upper portion of the stack package, characterized in that the electrically connected by the second electrode terminal and the bonding wires on the upper surface of the substrate. 제 1 항에 있어서,The method of claim 1, 상기 두 쌍의 반도체 칩과 본딩와이어를 포함하는 기판의 상면과 상기 본딩와이어를 포함한 캐버티 부분을 포함한 기판 하면의 일부분을 밀봉하는 봉지제를 더 포함하는 것을 특징으로 하는 스택 패키지.And an encapsulant sealing an upper surface of the substrate including the two pairs of semiconductor chips and the bonding wires and a portion of the lower surface of the substrate including the cavity portion including the bonding wires. 제 1 항에 있어서,The method of claim 1, 상기 기판은 하면에 형성된 외부접속단자를 더 포함하는 것을 특징으로 하는 스택 패키지.The substrate package stack, characterized in that further comprising an external connection terminal formed on the lower surface.
KR1020070076042A 2007-07-27 2007-07-27 Stack package KR20090011969A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101219484B1 (en) * 2011-01-24 2013-01-11 에스케이하이닉스 주식회사 Semiconductor chip module and semiconductor package having the same and package module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101219484B1 (en) * 2011-01-24 2013-01-11 에스케이하이닉스 주식회사 Semiconductor chip module and semiconductor package having the same and package module
US8736075B2 (en) 2011-01-24 2014-05-27 SK Hynix Inc. Semiconductor chip module, semiconductor package having the same and package module

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