KR20090026618A - Stack package - Google Patents

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KR20090026618A
KR20090026618A KR1020070091711A KR20070091711A KR20090026618A KR 20090026618 A KR20090026618 A KR 20090026618A KR 1020070091711 A KR1020070091711 A KR 1020070091711A KR 20070091711 A KR20070091711 A KR 20070091711A KR 20090026618 A KR20090026618 A KR 20090026618A
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South Korea
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package
semiconductor
substrate
stack
via pattern
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KR1020070091711A
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Korean (ko)
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정영희
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주식회사 하이닉스반도체
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Priority to KR1020070091711A priority Critical patent/KR20090026618A/en
Publication of KR20090026618A publication Critical patent/KR20090026618A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

A stacked package is provided to increase integration of the drain semiconductor package by increasing an area of the entire package. A stacked package(100) is composed of semiconductor chips (107a,107b), a substrate having electrodes(111a,111b). The top of the substrate is enclosed by a sealant and a solder ball is installed at the bottom of the substrate. The electrode is electrically connected with the semiconductor chip by a bonding wire. A via pattern(105a,105b) connected with a terminal of the electrode is formed inside the sealant.

Description

스택 패키지{STACK PACKAGE}Stack Package {STACK PACKAGE}

본 발명은 스택 패키지에 관한 것으로, 보다 자세하게는, 봉지제 내부에 비아 패턴을 형성하여 반도체 패키지 간을 스택시킨 스택 패키지에 관한 것이다.The present invention relates to a stack package, and more particularly, to a stack package in which a via pattern is formed inside an encapsulant to stack semiconductor packages.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨데, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. In addition, as miniaturization of electric and electronic products and high performance is required, various technologies for providing a high capacity semiconductor module have been researched and developed.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of a semiconductor chip.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모 듈을 제공하기 위한 다른 방법으로서 스택(stack) 기술이 제안되었다. However, the high integration of such a memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

상기와 같은 스택기술은 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 2개의 단품의 패키지를 스택하는 방법이 있다. 그러나, 상기와 같이 2개의 단품의 패키지를 스택하는 방법은 전기·전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이의 한계가 있다.Such a stacking technique includes a method of embedding two stacked chips in one package and stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

따라서, 하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 적층 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근 들어 활발하게 진행되고 있다. Therefore, research on a stack package and a multi chip package in which two or three semiconductor chips of one package are mounted has been actively conducted in recent years.

여기서, 상기 멀티 칩 패키지는, 통상, 여러 개의 반도체 칩들을 기판 상에 단순 나열하여 패키징하는 방법과 두 개 이상의 반도체 칩들을 적층 구조로 쌓아 올려 패키징하는 방법이 있다. In this case, the multi-chip package generally includes a method of simply arranging and packaging a plurality of semiconductor chips on a substrate and a method of stacking two or more semiconductor chips in a stacked structure.

이하에서는, 종래의 POP(Package On Package) 타입의 스택 패키지에 관해 간략하게 설명하도록 한다.Hereinafter, a stack package of a conventional POP (Package On Package) type will be briefly described.

종래 기술에 따른 POP 타입의 스택 패키지는, 반도체 칩 및 상기 반도체 칩과 기판 간의 전기적인 연결을 시켜주는 본딩와이어가 형성되고, 상기 본딩와이어와 반도체 칩을 밀봉하는 봉지제가 기판 상면 중앙에 부분적으로 형성되어 밀봉된 하부 반도체 패키지와, 상기 하부 반도체 패키지와 유사한 구성을 갖는, 즉, 반도체 칩과 기판 간이 본딩와이어에 의해 전기적으로 연결되며, 상기 본딩와이어와 반도체 칩을 밀봉하는 봉지제가 형성된 상부 반도체 패키지가 상기 상부 반도체 패키지 기판 하면에 부착된 접속 단자에 의해 스택된 구조를 갖는다.In the POP type stack package according to the related art, a bonding chip for making an electrical connection between the semiconductor chip and the semiconductor chip and the substrate is formed, and an encapsulant for sealing the bonding wire and the semiconductor chip is partially formed in the center of the upper surface of the substrate. And the upper semiconductor package which is sealed and has a structure similar to that of the lower semiconductor package, that is, the semiconductor chip and the substrate are electrically connected by bonding wires, and an encapsulant for sealing the bonding wires and the semiconductor chips is formed. The structure has a stacked structure by connection terminals attached to a lower surface of the upper semiconductor package substrate.

그러나, 상기와 같은 종래의 스택 패키지는, 상기 스택 패키지를 형성하기 위해서 하부 반도체 패키지의 기판 상에 하부 반도체 패키지에의 반도체 칩을 부착하기 위한 공간 이외에 기판의 외곽 부분인 봉지제가 형성되지 않는 부분에 추가적인 상부 반도체 패키지와의 부착 공간 및 그에 따른 추가적인 부착 수단이 요구되고 있는 실정이다.However, the conventional stack package as described above may be formed in a portion in which an encapsulant, which is an outer portion of the substrate, is not formed on the substrate of the lower semiconductor package in order to form the stack package. There is a need for an additional attachment space with the upper semiconductor package and thus additional attachment means.

따라서, 전체 패키지의 면적을 증가시키게 되며, 이는, 반도체 패키지의 크기를 감소시킬 수 없음과 아울러, 현재 트렌드인 반도체 패키지의 고집적화에 부응하지 못하게 된다는 문제점이 있다.Therefore, the area of the entire package is increased, which may not reduce the size of the semiconductor package and may not meet the current trend of high integration of the semiconductor package.

본 발명은, 스택 패키지 형성시 스택을 위한 추가적인 부착 공간 및 부착 수단을 사용하지 않고 반도체 패키지 간을 스택시켜 반도체 패키지의 고집적화에 부응한 스택 패키지를 제공한다.The present invention provides a stack package that meets high integration of a semiconductor package by stacking the semiconductor packages without using additional attachment space and attachment means for stack formation in stack package formation.

본 발명에 따른 스택 패키지는, 반도체 칩 및 상기 반도체 칩과 본딩와이어에 의해 전기적 연결된 전극단자를 갖는 기판의 상면이 봉지부로 감싸지고, 상기 기판의 하면에 솔더 볼이 부착된 구조를 갖는 적어도 둘 이상의 반도체 패키지가 스택되어 구성된 스택 패키지에 있어서, 상기 스택된 각 반도체 패키지는, 상기 봉지부 내에 기판의 전극단자와 연결된 관통 비아 패턴을 구비하고, 상기 비아 패턴과 솔더 볼 간의 연결에 의해 스택된 패키지들간 전기적 연결이 이루어진 것을 특 징으로 한다.At least two or more stack packages according to the present invention have a structure in which a top surface of a substrate having a semiconductor chip and an electrode terminal electrically connected to the semiconductor chip and a bonding wire is wrapped in an encapsulation portion, and a solder ball is attached to a bottom surface of the substrate. A stack package in which semiconductor packages are stacked, wherein each stacked semiconductor package includes a through via pattern connected to an electrode terminal of a substrate in the encapsulation portion, and the stacked packages are connected between the via patterns and solder balls. The electrical connection is made.

상기 비아 패턴은 상부 패키지와의 전기적 연결을 위해 봉지부 상부에 형성된 볼 랜드를 더 포함한다.The via pattern further includes a ball land formed on the encapsulation portion for electrical connection with the upper package.

상기 볼 랜드와 비아 패턴은 일체형으로 형성된 것을 특징으로 한다.The ball land and the via pattern may be formed in one piece.

또한, 본 발명에 따른 스택 패키지는, 반도체 칩 및 상기 반도체 칩과 본딩와이어에 의해 전기적 연결된 전극단자를 갖는 기판의 상면이 봉지부로 감싸지고, 상기 기판의 하면에 솔더 볼이 부착된 구조를 갖는 적어도 둘 이상의 반도체 패키지가 스택되어 구성된 스택 패키지에 있어서, 상기 스택된 각 반도체 패키지는, 상부 반도체 패키지가 하부 반도체 패키지보다 작은 크기의 구조를 가지고, 상기 하부 반도체 패키지가 봉지부 내에 기판의 전극단자와 연결되도록 구비된 관통 비아 패턴이 상부 반도체 패키지의 솔더 볼까지 연장 형성되어, 상기 비아 패턴과 솔더 볼 간의 연결에 의해 스택된 패키지들간 전기적 연결이 이루어진 것을 특징으로 한다.In addition, the stack package according to the present invention includes at least a structure in which a top surface of a substrate having a semiconductor chip and an electrode terminal electrically connected to the semiconductor chip and a bonding wire is wrapped in an encapsulation portion, and a solder ball is attached to a bottom surface of the substrate. A stack package comprising two or more semiconductor packages stacked, wherein each stacked semiconductor package has a structure in which an upper semiconductor package is smaller than a lower semiconductor package, and the lower semiconductor package is connected to an electrode terminal of a substrate in an encapsulation part. The through via pattern provided to extend to the solder balls of the upper semiconductor package is characterized in that the electrical connection is made between the stacked packages by the connection between the via patterns and the solder balls.

상기 비아 패턴은 상부 패키지와의 전기적 연결을 위해 봉지부 상부에 형성된 재배선을 더 포함한다.The via pattern further includes a redistribution formed on the encapsulation portion for electrical connection with the upper package.

상기 제배선과 비아 패턴은 일체형으로 형성된 것을 특징으로 한다.The wiring line and the via pattern may be formed in one piece.

따라서, 본 발명은 스택 패키지 형성시 전체 패키지의 면적 증가를 방지할 수 있으므로, 스택 형 반도체 패키지의 크기를 종래 보다 감소시킬 수 있으며, 그 결과, 현재 트렌드인 반도체 패키지의 고집적화를 구현할 수 있다.Accordingly, the present invention can prevent the increase of the area of the entire package when forming the stack package, thereby reducing the size of the stack-type semiconductor package, and as a result, it is possible to implement high integration of the semiconductor package, which is the current trend.

먼저, 본 발명의 기술적인 원리를 간략하게 설명하면, 본 발명은 적어도 둘 이상의 반도체 패키지를 스택하여 구성한 스택 패키지에 있어서, 반도체 패키지의 봉지제 내부를 기판의 전극단자가 노출되도록 관통하여 비아 패턴을 형성하고, 상기 비아 패턴과 상부 반도체 패키지의 외부 접속 단자 간을 부착하여 전기적으로 연결한다.First, the technical principle of the present invention will be briefly described. According to the present invention, in a stack package formed by stacking at least two semiconductor packages, a via pattern is formed by penetrating the inside of the encapsulant of the semiconductor package so that the electrode terminals of the substrate are exposed. And via the via pattern and the external connection terminals of the upper semiconductor package to electrically connect the via patterns.

이렇게 하면, 스택 패키지를 형성하기 위해 반도체 칩을 부착하기 위한 공간 이외에 기판의 외곽 부분인 봉지제가 형성되지 않는 부분에 추가적인 공간 및 그에 따른 추가적인 부착 수단이 요구되는 종래의 스택 패키지와 달리, 상기와 같이 봉지제 내부에 비아 패턴을 형성하여 반도체 패키지 간을 스택 함으로써, 스택 패키지 형성시, 전체 패키지의 면적 증가를 방지할 수 있다.In this way, unlike the conventional stack package which requires an additional space and thus additional attachment means in a portion where the encapsulant, which is an outer portion of the substrate, is not formed in addition to the space for attaching the semiconductor chip to form the stack package, as described above. By forming a via pattern inside the encapsulant to stack the semiconductor packages, it is possible to prevent an increase in the area of the entire package during stack package formation.

따라서, 상기와 같이 전체 패키지의 면적 증가를 방지할 수 있으므로, 반도체 패키지의 크기를 종래 보다 감소시킬 수 있으며, 현재 트렌드인 반도체 패키지의 고집적화를 구현할 수 있다.Therefore, as described above, since the area of the entire package can be prevented from increasing, the size of the semiconductor package can be reduced compared to the conventional one, and high integration of the semiconductor package, which is a current trend, can be realized.

자세하게, 도 1은 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도로써, 이를 설명하면 다음과 같다.In detail, Figure 1 is a cross-sectional view showing a stack package according to an embodiment of the present invention, as follows.

도시된 바와 같이, 본 발명의 실시예에 따른 스택 패키지(100)는, 적어도 2개 이상의 반도체 패키지(101a, 101b)가 봉지제(106a, 106b) 내부에 형성된 비아 패턴(105a, 105b)을 매개로 하여 스택된 구조를 갖는다.As illustrated, the stack package 100 according to an embodiment of the present invention may be formed by via patterns 105a and 105b in which at least two semiconductor packages 101a and 101b are formed inside the encapsulants 106a and 106b. It has a stacked structure.

상기 각 반도체 패키지(101a, 101b)는, 기판(102a, 102b) 상에 접착제(104a, 104b)를 매개로 하여 반도체 칩(107a, 107b)이 부착되고, 상기 반도체 칩(107a, 107b)과 기판(102a, 102b) 간을 전기적으로 연결시키기 위해 본딩와이어(109a, 109b)가 형성된다.Each of the semiconductor packages 101a and 101b has semiconductor chips 107a and 107b attached to the substrates 102a and 102b via adhesives 104a and 104b, and the semiconductor chips 107a and 107b and the substrate. Bonding wires 109a and 109b are formed to electrically connect between 102a and 102b.

상기 본딩와이어(109a, 109b)와 반도체 칩(107a, 107b)을 포함하는 기판(102a, 102b)의 일면을 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy Molding Compound)와 같은 봉지제(106a, 106b)로 밀봉되며, 기판(102a, 102b)의 하면에는 실장 부재로서 솔더 볼과 같은 다수의 외부 접속 단자(110a, 110b)가 부착된다.Encapsulants 106a and 106b such as an epoxy molding compound (EMC) to protect one surface of the substrates 102a and 102b including the bonding wires 109a and 109b and the semiconductor chips 107a and 107b from external stress. And a plurality of external connection terminals 110a and 110b such as solder balls are attached to the lower surfaces of the substrates 102a and 102b as mounting members.

여기서, 상기 봉지제(106a, 106b)의 내부에는 봉지제(106a, 106b) 가장자리의 상부로부터 봉지제(106a, 106b) 내부의 기판(102a, 102b) 전극단자(111a, 111b)까지 비아 패턴(105a, 105b)이 형성되며, 이때, 상기 비아 패턴(105a, 105b)은 구리와 같은 물질로 형성된다.Herein, the via patterns are formed in the encapsulant 106a and 106b from the upper edges of the encapsulant 106a and 106b to the electrode terminals 111a and 111b of the substrates 102a and 102b in the encapsulant 106a and 106b. 105a and 105b are formed, wherein the via patterns 105a and 105b are formed of a material such as copper.

또한, 상기 비아 패턴(105a, 105b)은 봉지제(106a, 106b) 상부로 볼 랜드와 같은 형태로 노출시켜 형성되어 상부 반도체 패키지(101b)의 솔더 볼과 같은 외부 접속 단자(110b)와 부착되어 전기적 및 물리적으로 연결되며, 상기 외부 접속 단자(110b)는 하부 반도체 패키지(101a)의 비아 패턴(105a, 105b)과 전기적 및 물리적으로 연결된다.In addition, the via patterns 105a and 105b are formed by exposing the encapsulant 106a and 106b in the form of ball lands and attached to the external connection terminals 110b such as solder balls of the upper semiconductor package 101b. The external connection terminal 110b is electrically and physically connected to the via patterns 105a and 105b of the lower semiconductor package 101a.

전술한 바와 같이 본 발명은, 봉지제 내부에 비아 패턴을 형성하여 반도체 패키지 간을 스택 함으로써, 스택 패키지 형성시 전체 패키지의 면적 증가를 방지할 수 있으므로, 전체 패키지의 면적 증가를 방지할 수 있다.As described above, in the present invention, by forming a via pattern inside the encapsulant and stacking the semiconductor packages, the area of the entire package can be prevented when the stack package is formed, thereby preventing the area of the entire package from increasing.

따라서, 전체 반도체 패키지의 크기를 종래 보다 감소시킬 수 있으므로, 현 재 트렌드인 반도체 패키지의 고집적화를 구현할 수 있다.Therefore, since the size of the entire semiconductor package can be reduced than before, high integration of the current semiconductor package can be realized.

도 2는 본 발명의 다른 실시예에 따른 스택 패키지를 도시한 단면도로써, 이를 설명하면 다음과 같다.2 is a cross-sectional view showing a stack package according to another embodiment of the present invention.

도시된 바와 같이, 본 발명의 다른 실시예에 따른 스택 패키지(220)는, 전술한 본 발명의 실시예에서와 같이 적어도 2개 이상의 반도체 패키지(201a, 201b)가 스택된 구조를 갖는다.As shown, the stack package 220 according to another embodiment of the present invention has a structure in which at least two or more semiconductor packages 201a and 201b are stacked as in the above-described embodiment of the present invention.

상기 적어도 2개 이상의 각 반도체 패키지(201a, 201b)에서 하부 반도체 패키지(201a)는, 기판(202a) 상에 접착제(204a)를 매개로 하여 반도체 칩(207a)이 부착되고, 상기 반도체 칩(207a)과 기판(202a) 간을 전기적으로 연결시키기 위해 본딩와이어(209a)가 형성되며, 상기 본딩와이어(209a)와 반도체 칩(207a)을 포함하는 기판의 일면을 EMC와 같은 봉지제(206a)로 밀봉되고, 기판(202a)의 하면에는 다수의 외부 접속 단자(210a)가 부착된다.In the at least two semiconductor packages 201a and 201b, the lower semiconductor package 201a is attached with a semiconductor chip 207a on the substrate 202a via an adhesive 204a, and the semiconductor chip 207a. Bonding wire 209a is formed to electrically connect the substrate 202a to the substrate 202a, and one surface of the substrate including the bonding wire 209a and the semiconductor chip 207a is formed of an encapsulant 206a such as EMC. It is sealed, and a plurality of external connection terminals 210a are attached to the lower surface of the substrate 202a.

상기 봉지제(206a)의 내부에는 봉지제(206a) 가장자리의 상부로부터 봉지제(206a) 내부의 기판(202a) 전극단자(211a)까지 비아 패턴(205a)이 형성되며, 이때, 상기 비아 패턴(205a)은 봉지제(206a) 상부로 볼 랜드와 같은 형태로 노출시켜 형성되며, 상부 반도체 패키지(201b)와 전기적인 연결을 이루기 위해 봉지제(206a) 중심 방향으로 연장되도록 형성된다. 상기 비아 패턴(205a)은 구리와 같은 물질로 형성된다.The via pattern 205a is formed in the encapsulant 206a from an upper portion of the edge of the encapsulant 206a to the electrode terminal 211a of the substrate 202a in the encapsulant 206a. The 205a is formed by exposing the encapsulant 206a in the form of a ball land, and extends toward the center of the encapsulant 206a to form an electrical connection with the upper semiconductor package 201b. The via pattern 205a is formed of a material such as copper.

상기 적어도 2개 이상의 각 반도체 패키지(201a, 201b)에서 상부 반도체 패키지(201b)는, 하부 반도체 패키지(201a)에서의 반도체 칩(207a)보다 상대적으로 크기가 작은 컨트롤러 반도체 칩으로 이루어진 반도체 패키지이며, 봉지제(206b) 내부에 비아 패턴이 형성되지 않고, 상기 상부 반도체 패키지(201b)의 기판(202b) 하면에 부착된 외부 접속 단자(210b)와 하부 반도체 패키지(201a)에서의 연장된 비아 패턴(205a)과 부착되어 전기적 및 물리적으로 연결된다.In each of the at least two semiconductor packages 201a and 201b, the upper semiconductor package 201b is a semiconductor package including a controller semiconductor chip having a smaller size than the semiconductor chip 207a in the lower semiconductor package 201a. The via pattern is not formed in the encapsulant 206b, and the external via terminal 210b attached to the lower surface of the substrate 202b of the upper semiconductor package 201b and the extended via pattern in the lower semiconductor package 201a ( 205a) to be electrically and physically connected.

그 외의 구성요소는 전술한 하부 반도체 패키지(201a)와 동일한 구조를 가지며, 미설명된 도면 부호 202b, 204b, 207b 및 210b는 각각 기판, 접착제, 반도체 칩 및 외부 접속 단자를 나타낸다.The other components have the same structure as the lower semiconductor package 201a described above, and reference numerals 202b, 204b, 207b, and 210b, which are not described, indicate a substrate, an adhesive, a semiconductor chip, and an external connection terminal, respectively.

이 경우, 본 발명은 상기와 같이 하부 반도체 패키지의 봉지제 내부에 비아 패턴을 형성하여 반도체 패키지를 스택 함으로써, 스택 패키지 형성시 전체 패키지의 면적 증가를 방지할 수 있으므로, 전체 패키지의 면적 증가를 방지할 수 있고, 따라서, 전체 반도체 패키지의 크기를 종래 보다 감소시킬 수 있다.In this case, the present invention forms a via pattern inside the encapsulant of the lower semiconductor package as described above to stack the semiconductor packages, thereby preventing an increase in the area of the entire package when forming the stack package, thereby preventing an increase in the area of the entire package. Therefore, the size of the entire semiconductor package can be reduced than before.

또한, 하부 반도체 패키지의 비아 패턴을 봉지제 중심 방향으로 연장되도록 형성하여 상기 하부 반도체 패키지보다 상대적으로 크기가 작은 컨트롤러(Controller) 반도체 패키지를 스택함으로써, 상기 비아 패턴에 의해 이 종간의 반도체 패키지 간을 스택할 수 있다.In addition, the via pattern of the lower semiconductor package is formed to extend toward the center of the encapsulant, thereby stacking a controller semiconductor package having a smaller size than that of the lower semiconductor package. You can stack it.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a stack package according to an embodiment of the present invention.

도 2는 본 발명의 다른 실시예에 따른 스택 패키지를 도시한 단면도.2 is a cross-sectional view showing a stack package according to another embodiment of the present invention.

Claims (6)

반도체 칩 및 상기 반도체 칩과 본딩와이어에 의해 전기적 연결된 전극단자를 갖는 기판의 상면이 봉지부로 감싸지고, 상기 기판의 하면에 솔더 볼이 부착된 구조를 갖는 적어도 둘 이상의 반도체 패키지가 스택되어 구성된 스택 패키지에 있어서,A stack package in which a top surface of a semiconductor chip and a substrate having an electrode terminal electrically connected to the semiconductor chip and a bonding wire are wrapped with an encapsulation portion, and at least two semiconductor packages having a structure in which solder balls are attached to a bottom surface of the substrate are stacked. To 상기 스택된 각 반도체 패키지는, 상기 봉지부 내에 기판의 전극단자와 연결된 관통 비아 패턴을 구비하고, 상기 비아 패턴과 솔더 볼 간의 연결에 의해 스택된 패키지들간 전기적 연결이 이루어진 것을 특징으로 하는 스택 패키지.Each of the stacked semiconductor packages has a through-via pattern connected to an electrode terminal of a substrate in the encapsulation portion, and the stacked packages are electrically connected between the stacked packages by a connection between the via pattern and solder balls. 제 1 항에 있어서,The method of claim 1, 상기 비아 패턴은 상부 패키지와의 전기적 연결을 위해 봉지부 상부에 형성된 볼 랜드를 더 포함하는 것을 특징으로 하는 스택 패키지.The via pattern further includes a ball land formed on the encapsulation portion for electrical connection with the upper package. 제 2 항에 있어서,The method of claim 2, 상기 볼 랜드와 비아 패턴은 일체형으로 형성된 것을 특징으로 하는 스택 패키지.The ball land and the via pattern is a stack package, characterized in that formed in one piece. 반도체 칩 및 상기 반도체 칩과 본딩와이어에 의해 전기적 연결된 전극단자를 갖는 기판의 상면이 봉지부로 감싸지고, 상기 기판의 하면에 솔더 볼이 부착된 구조를 갖는 적어도 둘 이상의 반도체 패키지가 스택되어 구성된 스택 패키지에 있어서,A stack package in which a top surface of a semiconductor chip and a substrate having an electrode terminal electrically connected to the semiconductor chip and a bonding wire are wrapped with an encapsulation portion, and at least two semiconductor packages having a structure in which solder balls are attached to a bottom surface of the substrate are stacked. To 상기 스택된 각 반도체 패키지는, 상부 반도체 패키지가 하부 반도체 패키지보다 작은 크기의 구조를 가지고, 상기 하부 반도체 패키지가 봉지부 내에 기판의 전극단자와 연결되도록 구비된 관통 비아 패턴이 상부 반도체 패키지의 솔더 볼까지 연장 형성되어, 상기 비아 패턴과 솔더 볼 간의 연결에 의해 스택된 패키지들간 전기적 연결이 이루어진 것을 특징으로 하는 스택 패키지.Each of the stacked semiconductor packages has a structure in which an upper semiconductor package is smaller than a lower semiconductor package, and a through-via pattern in which the lower semiconductor package is connected to an electrode terminal of a substrate in an encapsulation part has solder balls of the upper semiconductor package. Extending to form a stack package, characterized in that the electrical connection is made between the stacked packages by the connection between the via pattern and the solder ball. 제 3 항에 있어서,The method of claim 3, wherein 상기 비아 패턴은 상부 패키지와의 전기적 연결을 위해 봉지부 상부에 형성된 재배선을 더 포함하는 것을 특징으로 하는 스택 패키지.The via pattern further comprises a redistribution formed on the encapsulation portion for electrical connection with the upper package. 제 4 항에 있어서,The method of claim 4, wherein 상기 제배선과 비아 패턴은 일체형으로 형성된 것을 특징으로 하는 스택 패키지.The stack line and the via pattern is a stack package, characterized in that formed in one piece.
KR1020070091711A 2007-09-10 2007-09-10 Stack package KR20090026618A (en)

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