KR20060104026A - Method for manufacturing a semiconductor device - Google Patents

Abstract

The present invention is to provide a method of manufacturing a semiconductor device that can improve the device characteristics by preventing the phenomenon that the threshold voltage of the device is changed according to the interface capture charge formed on the interface between the gate oxide film and the channel formed substrate, the present invention The method may further include providing a semiconductor substrate having a well region, implanting germanium and fluorine ions into a region in which the channel region is to be formed, and forming a gate insulating layer on the substrate on which the germanium and the fluorine ions are implanted. Forming a gate electrode on the substrate by forming a conductive layer, depositing a conductive layer on the gate insulating layer, etching the conductive layer and the gate insulating layer, and forming a gate electrode on both sides of the gate electrode. A method of manufacturing a semiconductor device comprising forming a source / drain region within to provide.

 MOSFET, channel, gate oxide, ion implantation.

Description

METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

110 semiconductor substrate 111 device isolation film

112: well ion implantation process 113: well region

114 GeF ₂ ion implantation process 115 gate insulating film

116: gate conductive film 117: gate electrode

118 impurity ion implantation process 119 LDD junction region

120: Halo junction region 121: low concentration junction region

122: first spacer 123: second spacer

124 source / drain ion implantation process 125 high concentration junction region

126 source / drain region 127 metal silicide layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a metal oxide semiconductor field effect transistor applying surface channel operation.

Currently, logic devices have been driving down driving voltages for high integration, reduced power consumption, and high performance. Accordingly, in order to lower the gate oxide film thickness and improve short channel effects, the present invention is changed from a buried channel operation to a surface channel operation. For reference, the buried channel refers to a channel formed by implanting ions through a separate ion implantation process. In addition, the surface channel refers to a channel formed through a voltage applied to the gate electrode rather than implanting ions through an ion implantation process.

Hereinafter, a method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET) for implementing a surface channel operation according to the prior art will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, the well region 13 is formed by performing a mask process and a well ion implantation process 12 on the semiconductor substrate 10 on which the device isolation film 11 is formed.

Subsequently, as shown in FIG. 1B, the gate electrode 16 is formed in a predetermined region on the well region 13. At this time, the gate electrode 16 includes a gate oxide film 14 and a polysilicon film 15.

Subsequently, the LDD (Lightly Doped Darin) ion implantation process and the Halo ion implantation process are performed in the low concentration impurity ion implantation process 17 using the gate electrode 16 as a mask and exposed to both sides of the gate electrode 16. The low concentration junction region 20 is formed in the well region 13. In this case, the low concentration junction region 20 is formed such that the halo junction region 19 surrounds the LDD junction region 18.

Subsequently, as shown in FIG. 1C, after forming the first spacer 21 made of an insulating film on both sidewalls of the gate electrode 16, the second spacer made of the insulating film is formed on both sidewalls of the first spacer 21. 22).

Subsequently, a high concentration source / drain ion implantation process 23 using the second spacer 22 as a mask is performed to provide a high concentration junction region 24 to the well region 13 exposed to both sides of the second spacer 22. Form. As a result, the source / drain regions 25 of the semiconductor element are formed.

Subsequently, as shown in FIG. 1D, a salicide (SALICIDE) process is performed to expose silicon (Si), that is, the source / drain region 25 and the gate electrode 16. The metal silicide layer 26 is formed on the substrate.

In general, in the case of a semiconductor device which applies a surface channel operation in which a channel is formed in a substrate under the gate oxide film when driving the device as in the related art, since the gate oxide film and the channel are in contact with each other, the device characteristics are greatly changed according to the state of the gate oxide film. In particular, the MOSFET according to the prior art has a problem in that when the interface trap charge is present at the interface between the substrate on which the channel is formed and the gate oxide film, the threshold voltage is changed when driving the device, thereby degrading device characteristics. In addition, as the device becomes smaller and smaller, the change in the threshold voltage according to the interface capture charge is observed. Therefore, a solution to this problem is urgent.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and improves device characteristics by preventing a phenomenon in which the threshold voltage of the device is changed according to the interface capture charge formed at the interface between the gate oxide film and the channel formed substrate. It is to provide a method for manufacturing a semiconductor device that can be made.

According to an aspect of the present invention, there is provided a semiconductor substrate including a well region, implanting germanium and fluorine ions into a region in which a channel region is to be formed; Forming a gate insulating film on the substrate implanted with germanium and the fluorine ions, depositing a conductive film on the gate insulating film, and etching the conductive film and the gate insulating film to form a gate electrode on the substrate And forming a source / drain region in the well region exposed to both sides of the gate electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Here, among the codes shown in FIGS. 2A to 2F, the same signs are the same elements that perform the same function.

First, as shown in FIG. 2A, the well region 113 is formed by performing a well ion implantation process 112 on the semiconductor substrate 110 on which the device isolation layer 111 is formed. In this case, the device isolation layer 111 may be formed by performing a shallow trench isolation (STI) or LOCOS (LOCal Oxidation of Silicon) process, which is formed by performing an STI process suitable for high integration of semiconductor devices.

Here, the well ion implantation process 112 is performed using a predetermined photoresist pattern (not shown) to form a CMOSFET (Complementary MOSFET). For example, in order to form a PMOSFET of a CMOSFET, a photoresist pattern is formed on a region where an NMOSFET is to be formed, and then, phosphorus or arsenic ions are implanted therethrough to form an N well. On the other hand, in order to form an NMOSFET of a CMOSFET, a photoresist pattern is formed on a region where the PMOSFET is to be formed, and then boron is injected to form a P well.

Subsequently, as illustrated in FIG. 2B, a GeF ₂ ion implantation process 114 is performed on the entire surface of the semiconductor substrate 110. In this case, the GeF ₂ ion implantation process 114 is performed only once by a molecular ion implantation process in which the ratio of fluorine ions to germanium is 1: 2. In addition, GeF ₂ ion implantation step 114 is performed by implanting GeF ₂ molecular ions of 1.0E12 to 5.0E14 atoms / cm 2 dose with an inclination angle of 0 to 60 ° with an energy of 30 to 200 KeV.

Here, germanium forms a Si-Ge bond with silicon of the semiconductor substrate 110 in the channel portion to be formed during driving of the device, thereby increasing the fluidity of carriers flowing in the channel, thereby increasing the current of the device. Make sure For reference, the fluidity of the carrier flowing in the channel depends on the change of the crystal lattice of the channel portion. Thus, improved device characteristics can be obtained.

In addition, the fluorine here pushes out the "H" of the "Si-H" bond formed in an incomplete form at the interface between the semiconductor substrate 110 and the gate insulating film 115 when forming the gate insulating film 115 (see FIG. 2C) By combining with oxygen or incompletely formed silicon dangling bond to form a "Si-F" bond, the threshold voltage is kept constant when driving the device. For reference, since the "Si-F" bond has a very strong bonding force, it does not affect the threshold voltage when driving the device, thereby improving device characteristics.

Subsequently, although not shown in the drawing, thermal processing is performed to heat-treat the semiconductor substrate 110 into which GeF ₂ is injected. At this time, the thermal process is performed in a chamber of 100% nitrogen atmosphere using Rapid Thermal Processing (RTP) or Furnace (Furnace) equipment.

Here, when using the RTP equipment is carried out for 10 to 30 seconds at a temperature of 800 to 1000 ℃, the temperature increase rate is 30 to 50 ℃ / sec. On the other hand, when using the furnace equipment, it is carried out for 2 to 24 hours at a temperature of 400 to 600 ℃, or 10 to 30 minutes at a temperature of 700 to 950 ℃.

Subsequently, as illustrated in FIG. 2C, the gate insulating layer 115 and the gate conductive layer 116 are formed on the well region 113, and an etching process is performed to form the gate electrode 117. In this case, the gate insulating film 115 is formed by performing an oxidation process with a gate oxide film, and the conductive film 116 is formed with a doped polysilicon film or an undoped polysilicon film. For example, the polysilicon film is formed by depositing a low presure chemical vapor deposition (LPCVD) method using SiH ₄ or SiH ₄ and PH ₃ .

Subsequently, as shown in FIG. 2D, a low concentration of impurity ion implantation process 118 using the gate electrode 117 as a mask, that is, an LDD ion implantation process and a halo ion implantation process, is performed to both sides of the gate electrode 117. The low concentration junction region 121 is formed in the exposed well region 113. In this case, the low concentration junction region 121 is formed in a structure in which the halo junction region 120 surrounds the LDD junction region 119.

Here, the reason for performing the LDD ion implantation step is to prevent the occurrence of hot carriers. The reason for performing the halo ion implantation process is to suppress a short channel effect in which the channel length is reduced due to the formation of the LDD junction region 119 and the threshold voltage is lowered.

Here, the impurity ion implantation process 118 is performed using a predetermined photoresist pattern (not shown) similarly to the well ion implantation process 112 to form a CMOSFET.

Subsequently, as illustrated in FIG. 2E, a first insulating layer (not shown) is deposited along a step of the entire structure where the gate electrode 117 is formed, and then a dry etching process is performed on both sidewalls of the gate electrode 117. The first spacer 122 is formed.

Subsequently, a second insulating layer (not shown) is deposited along the step of the upper portion of the entire structure where the first spacers 122 are formed, and then a dry etching process is performed to form the second spacers 123 on both sidewalls of the first spacers 122. To form.

Subsequently, a high concentration junction / drain region is formed in the well region 113 exposed to both sides of the second spacer 123 by performing a high concentration source / drain ion implantation process 124 and a thermal process using the second spacer 123 as a mask. 125). As a result, the source / drain regions 126 of the semiconductor device are formed. For reference, when the conductive film 116 constituting the gate electrode 117 is an undoped polysilicon film, impurities are simultaneously injected into the conductive film 116 during the source / drain ion implantation process 124.

Subsequently, as shown in FIG. 2F, a salicide process is performed to form a metal silicon layer 127 on the silicon exposed region, that is, on the source / drain region 126 and on the gate electrode 117. . Accordingly, contact resistance between the source / drain region 126 and the gate electrode 117 and the metal wiring to be formed through the subsequent process can be reduced.

Here, the salicide process consists of two thermal processes after the deposition of cobalt or titanium. For example, a first thermal process is performed to form a mono silicide layer (CoSi) on the source / drain regions 126 and the gate electrode 117, and a second thermal process is performed to finally form a CoSi ₂ layer. To form.

That is, according to the preferred embodiment of the present invention, germanium and fluorine ions are implanted simultaneously by performing a GeF ₂ ion implantation process on a semiconductor substrate on which a channel is to be formed before forming a gate oxide film.

Here, the implanted germanium forms a Si-Ge bond with the silicon of the semiconductor substrate in the channel region to be formed during device driving, thereby increasing the fluidity of carriers flowing in the channel, thereby increasing the current of the device. . In addition, the implanted fluorine forms a "Si-F" bond in the channel region, thereby preventing the phenomenon in which the threshold voltage of the device is changed in accordance with the interface capture charge formed at the interface between the gate oxide film and the substrate on which the channel is formed. Therefore, the device characteristics of the semiconductor device can be improved.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, before forming a gate oxide film, a GeF ₂ ion implantation process is performed on a semiconductor substrate on which a channel is to be formed to simultaneously inject germanium and fluorine ions. In this case, the current of the device may be increased by increasing the fluidity of carriers flowing in the channel to the injected germanium. In addition, it is possible to prevent the phenomenon that the threshold voltage of the device is changed due to the interface capture charges formed at the interface between the gate oxide film and the substrate on which the channel is formed by the injected fluorine. Therefore, the device characteristics of the semiconductor device can be improved.

Claims (10)

Providing a semiconductor substrate having well regions formed thereon; Implanting germanium and fluorine ions into a region in which the channel region is to be formed; Forming a gate insulating film on the substrate in which the germanium and the fluorine ions are implanted; Depositing a conductive film on the gate insulating film; Etching the conductive layer and the gate insulating layer to form a gate electrode on the substrate; And Forming a source / drain region in the well region exposed to both sides of the gate electrode; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The step of injecting the germanium and the fluorine ions is a manufacturing method of a semiconductor device performed by the ratio of the fluorine ion to the germanium 1: 2. The method according to claim 1 or 2, The step of injecting the germanium and the fluorine ions is carried out in a 1.0E12 to 5.0E14 atoms / ㎠ dose with energy of 30 to 200 KeV. The method of claim 4, wherein The process of implanting the germanium and the fluorine ions is carried out to have an inclination angle of 1 to 60 °. The method according to claim 1 or 2, In the step of injecting the germanium and the fluorine ions is implanted the germanium and the fluorine ions, and further heat treatment. The method of claim 5, The heat treatment is a method of manufacturing a semiconductor device performed in a chamber of nitrogen atmosphere using RTP or furnace equipment. The method according to claim 1 or 2, And the gate insulating film is formed into an oxide film by performing an oxidation process. The method according to claim 1 or 2, The source / drain region may include a low concentration junction region and a high concentration junction region. The method of claim 8, The low concentration junction region is formed by performing an LDD ion implantation process and a Halo ion implantation process. The method according to claim 1 or 2, After forming the source / drain regions, forming a metal silicide layer on the gate electrode and the source / drain regions.

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