KR20060077023A - Method for fabricating the gate oxide of semiconductor device - Google Patents
Method for fabricating the gate oxide of semiconductor device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 18
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 13
- 239000011737 fluorine Substances 0.000 claims abstract description 13
- 239000007858 starting material Substances 0.000 claims abstract description 13
- -1 fluorine ions Chemical class 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 abstract description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
본 발명은 반도체 소자의 게이트 산화막 제조 방법에 관한 것으로, 실리콘 기판 상에 불순물을 주입하여 웰을 형성하는 단계; 상기 웰 상에 게이트 LPCVD 방법을 사용하여 실리콘 스타터막을 형성하는 단계; 상기 실리콘 스타터막 상에 실리콘 게르마늄막을 형성하는 단계; 상기 실리콘 게르마늄막 상에 실리콘 캡막을 형성하는 단계; 플루오르 이온을 주입하는 단계; RTA 어닐링을 하는 단계 및 상기 형성된 실리콘 스타터막, 실리콘 게르마늄막 및 실리콘 캡막을 RIE로 식각하여 패터닝하는 단계로 이루어짐에 기술적 특징이 있고, 실리콘 게르마늄 게이트를 형성하고, 플루오르 이온을 주입한 후, 열처리 공정을 실시함으로써, 플루오르가 붕소의 침투를 억제하고, 단채널 효과를 향상하여 반도체 소자의 특성을 향상하는 효과가 있다.The present invention relates to a method of manufacturing a gate oxide film of a semiconductor device, comprising: forming a well by implanting impurities on a silicon substrate; Forming a silicon starter film on the well using a gate LPCVD method; Forming a silicon germanium film on the silicon starter film; Forming a silicon cap film on the silicon germanium film; Implanting fluorine ions; RTA annealing and etching and patterning the formed silicon starter film, silicon germanium film and silicon cap film by RIE, the silicon germanium gate is formed, and fluorine ions are implanted, followed by a heat treatment process By performing the above, fluorine has an effect of suppressing the penetration of boron, improving the short channel effect, and improving the characteristics of the semiconductor element.
게이트 산화막, 플루오르 이온Gate oxide, fluorine ion
Description
도 1a 및 도 1b는 종래의 폴리 실리콘 게이트 제조 방법을 나타내는 공정 단면도이다.1A and 1B are cross-sectional views illustrating a conventional polysilicon gate manufacturing method.
도 2a 내지 도 2c는 본 발명에 따른 게이트 산화막 제조 방법을 나타내는 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a gate oxide film according to the present invention.
본 발명은 반도체 소자의 게이트 산화막 제조 방법에 관한 것으로, 보다 자세하게는 플루오르 이온을 주입하여 붕소의 확산을 예방하는 실리콘 게르마늄 게이트 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a gate oxide film of a semiconductor device, and more particularly, to a method for manufacturing a silicon germanium gate for implanting fluorine ions to prevent the diffusion of boron.
일반적으로 모스형 반도체 소자는 금속-산화막-반도체의 콘덴서 구조를 사용하는 것으로, 금속 전극과 반도체 기판 사이에 인가된 바이어스에 의해서 반도체 기판 위의 산화막 바로 밑에 전류의 통로가 되어 야할 채널이 형성되고, 그것이 바 이어스의 값에 의해 제어되는 것이 기본 원리이다. 따라서, 금속 전극으로서 가장 기본적인 전극 재료인 알루미늄을 게이트 전극으로 사용해서 반도체 소자의 개발이 시도되었다.In general, the MOS type semiconductor device uses a capacitor structure of a metal-oxide film-semiconductor, and a channel to be a current path is formed directly under the oxide film on the semiconductor substrate by a bias applied between the metal electrode and the semiconductor substrate. The basic principle is that it is controlled by the value of the bias. Accordingly, development of a semiconductor device has been attempted using aluminum, which is the most basic electrode material, as a metal electrode as a gate electrode.
알루미늄 게이트의 경우에는 특히, 모스 트랜지스터의 소스/드레인 부분의 확산층을 형성한 다음 알루미늄 전극을 만들기 때문에, 알루미늄의 패턴을 접합하기 위한 글라스 마스크를 반도체 기판 상에 위치 조정할 때 오차분의 여유를 소스/드레인과 게이트 전극의 오버랩으로서 수취할 필요가 있다. In the case of an aluminum gate, in particular, since the diffusion layer of the source / drain portion of the MOS transistor is formed, and then an aluminum electrode is formed, a margin of error is provided when the glass mask for bonding the pattern of aluminum is positioned on the semiconductor substrate. It needs to be received as an overlap between the drain and the gate electrode.
상기 오버랩은 점유 패턴 면적을 증가시킴과 동시에 게이트 전극과 드레인 전극간의 궤환 용량을 증가시켜 회로의 스위칭 스피드에 중대한 영향을 미치며, 결과적으로 게이트 전극 자체의 면적이 증가되어 입력 용량을 증가시킴으로써 회로의 스위칭 스피드를 저하시킨다.The overlap increases the occupied pattern area and at the same time increases the feedback capacitance between the gate electrode and the drain electrode, which significantly affects the switching speed of the circuit. As a result, the area of the gate electrode itself is increased to increase the input capacitance, thereby switching the circuit. Decreases the speed
이에 대응하여 자기 정합 게이트 형성이 가능하도록 한 것이 실리콘 게이트 전극이다. 이것은 채널 부분의 마스킹은 게이트 전극 자체로부터 이루어지므로 마스크 정렬 오차를 고려할 필요가 전혀 없고, 게이트 전극과의 소스/드레인의 오버랩은 극히 적으며 확산층의 가로방향이 늘어난 것뿐이다. Correspondingly, the silicon gate electrode is capable of forming a self-matching gate. This masking of the channel portion is made from the gate electrode itself, so there is no need to consider the mask alignment error, the source / drain overlap with the gate electrode is extremely small and only the transverse direction of the diffusion layer is increased.
이 때문에 궤환 용량 및 게이트 용량 모두 대단히 적고, 회로의 스위칭 특성이 대폭적으로 향상된다. 그리고, 반도체 소자의 비트 라인(bit line) 등을 형성하기 위한 실리콘 게이트 기술은 게이트에 사용되고 있는 다결정 실리콘의 저항값을 저감하기 위해서 실리사이드를 형성하고 있다.For this reason, both the feedback capacitance and the gate capacitance are very small, and the switching characteristics of the circuit are greatly improved. The silicon gate technology for forming bit lines and the like of semiconductor devices forms silicides in order to reduce the resistance value of polycrystalline silicon used for the gate.
도 1a 및 도 1b는 종래의 폴리 실리콘 게이트 제조 방법을 나타내는 공정 단 면도이다. 먼저, 도 1a에 도시한 바와 같이, 실리콘 기판(1)를 열산화하여 게이트 영역의 유전체 역할을 하는 게이트 산화막(2)을 양질의 순수한 산화실리콘(SiO2)의 얇은 막으로 열 성장시킨다. 1A and 1B are process steps illustrating a conventional polysilicon gate manufacturing method. First, as shown in FIG. 1A, the silicon substrate 1 is thermally oxidized to thermally grow the
그리고, 열 성장된 게이트 산화막(2) 상부에 반도체 소자의 비트 라인 등과 같은 게이트를 형성하기 위하여, 폴리 실리콘막(3)을 화학 기상 증착법(chemical vapor deposition ; CVD)에 의해 증착시킨다. 이때, 폴리 실리콘막(3)을 형성하기 위한 화학 기상 증착은 가열로나 급속 열처리 공정(rapid thermal processing) 장비에서 사일엔(SiH4) 가스를 공급하여 결정(grain) 형태로 성장된 폴리 실리콘막이 되도록 한다. Then, in order to form a gate such as a bit line of a semiconductor element on the thermally grown
그리고, 이온 주입 공정에 의해 인(P)이나 비소(As) 등의 불순물을 주입하여 도핑 폴리 실리콘막(3)을 형성하고, 어닐링(annealing)하여 폴리 실리콘막(3)의 내부 저항을 감소시켜 폴리 실리콘 고유의 전기적 특성을 회복시킨다. 그 다음, 폴리 실리콘막(3)의 접촉 저항을 감소시키기 위하여, 폴리 실리콘막(3) 상부에 텅스텐막(4)을 증착하고, 어닐링하여 텅스텐 실리사이드(4)를 형성한다. 그 다음, 텅스텐 실리사이드(4) 상부에 포토레지스트(5)를 도포하고, 게이트 패턴의 마스크를 이용하여 포토레지스트(5)를 노광 현상함으로써, 게이트 형성을 위한 포토레지스트 패턴(5)을 형성한다.The
그 다음, 도 1b에 도시한 바와 같이, 포토레지스트 패턴(5)을 마스크로 텅스텐 실리사이드(4), 폴리 실리콘막(3), 게이트 산화막(2)을 연속하여 식각한 후, 포 토레지스트 패턴(5)을 제거하여 폴리 실리콘 게이트를 완성한다.1B, the
상기와 같은 종래 기술은 포토레지스트 마스크로 형성된 폴리 실리콘의 패턴에 따라 폴리 실리콘 게이트를 정의하는 것으로 소자가 집적화되면서 채널이 작아져 이때 포토 장비의 하드웨어의 스펙(Spec)에 의존하게 되는 문제점이 있었다.The prior art as described above defines a polysilicon gate according to a pattern of polysilicon formed by a photoresist mask, and as a device is integrated, a channel becomes smaller and there is a problem in that it depends on a specification of hardware of photo equipment.
따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 실리콘 게르마늄 게이트를 형성하고, 플루오르(F+) 이온을 주입한 후, 열처리 공정을 실시하여 붕소의 침투를 억제하고, 단채널 효과(Short Channel Effect)를 향상할 수 있는 반도체 소자의 게이트 산화막 제조 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, to form a silicon germanium gate, injecting fluorine (F +) ions, and then performing a heat treatment process to suppress the penetration of boron, SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a gate oxide film of a semiconductor device capable of improving short channel effects.
본 발명의 상기 목적은 실리콘 기판 상에 불순물을 주입하여 웰을 형성하는 단계; 상기 웰 상에 게이트 LPCVD 방법을 사용하여 실리콘 스타터막을 형성하는 단계; 상기 실리콘 스타터막 상에 실리콘 게르마늄막을 형성하는 단계; 상기 실리콘 게르마늄막 상에 실리콘 캡막을 형성하는 단계; 플루오르 이온을 주입하는 단계; RTA 어닐링을 하는 단계 및 상기 형성된 실리콘 스타터막, 실리콘 게르마늄막 및 실리콘 캡막을 RIE로 식각하여 패터닝하는 단계를 포함하여 이루어진 반도체 소자의 게이트 산화막 제조 방법에 의해 달성된다.The object of the present invention is to form a well by implanting impurities on a silicon substrate; Forming a silicon starter film on the well using a gate LPCVD method; Forming a silicon germanium film on the silicon starter film; Forming a silicon cap film on the silicon germanium film; Implanting fluorine ions; RTA annealing and etching and patterning the formed silicon starter film, silicon germanium film and silicon cap film by RIE to achieve a gate oxide film manufacturing method of a semiconductor device.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
도 2a 내지 도 2c는 본 발명에 따른 게이트 산화막 제조 방법을 나타내는 공정 단면도이다. 도 2a에 도시된 바와 같이, 실리콘 기판 상에 활성 영역에 p형 또는 n형 불순물을 주입하여 p형 또는 n형 웰(미도시)을 형성하고, STI(Shallow Trench Isolation) 방법을 이용하여 소자 분리막(미도시)을 형성한다.2A to 2C are cross-sectional views illustrating a method of manufacturing a gate oxide film according to the present invention. As shown in FIG. 2A, p-type or n-type wells are formed by implanting p-type or n-type impurities into an active region on a silicon substrate, and a device isolation layer is formed by using a shallow trench isolation (STI) method. (Not shown) is formed.
이후, 게이트 산화막을 형성하는데, 상기 게이트 산화막 제조 방법은 다음과 같다. LPCVD(Low Pressure Chemical Vapor Deposition) 방법을 사용하여 500℃~900℃의 온도로 실리콘 스타터막(110)(Silicon Starter Layer)을 형성한다. 상기 실리콘 스타터막(110)은 1000Å~2000Å의 두께로 형성한다. Thereafter, a gate oxide film is formed, and the method for manufacturing the gate oxide film is as follows. A
상기 실리콘 스타터막(110) 상에 실리콘 게르마늄막(120)(Si0.2Ge0.8 Layer)을 100Å~500Å의 두께로 형성하고, 그 상부에 실리콘 캡막(130)(Silicon Cap Layer)을 500Å~1000Å의 두께로 형성하여 실리콘 게르마늄 게이트(140)를 형성한다.A silicon germanium layer 120 (Si 0.2 Ge 0.8 Layer) is formed on the
도 2b에 도시된 바와 같이, 플루오르(F+) 이온으로 이온을 주입한다. 상기 플루오르 이온의 주입 에너지는 50keV~200keV이고, 주입량은 1E13~1E14 ions/cm2으로 한다.As shown in FIG. 2B, ions are implanted with fluorine (F +) ions. The implantation energy of the fluorine ions is 50 keV to 200 keV, and the implantation amount is 1E13 to 1E14 ions / cm 2 .
이후, RTA(Rapid Thermal Annealing)를 이용하여 어닐링을 실시한다. 상기 RTA 어닐링은 N2 분위기에서 공정온도는 1000℃이고, 시간은 30초로 한다.Thereafter, annealing is performed using RTA (Rapid Thermal Annealing). In the RTA annealing, the process temperature is 1000 ° C. and the time is 30 seconds in an N 2 atmosphere.
도 2c에 도시된 바와 같이, 상기 도 2a에 형성된 실리콘 게르마늄 게이트(140)를 RIE(Reactive Ion Etch) 식각 방법을 통해 식각하여 패터닝하면 실리콘 게르마늄 게이트(150)가 형성된다.As shown in FIG. 2C, when the silicon germanium gate 140 formed in FIG. 2A is etched and patterned through a reactive ion etching (RIE) etching method, the
본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.
따라서, 본 발명의 반도체 소자의 게이트 산화막 제조 방법은 실리콘 게르마늄 게이트를 형성하고, 플루오르 이온을 주입한 후, 열처리 공정을 실시함으로써, 플루오르가 붕소의 침투를 억제하고, 단채널 효과를 향상하여 반도체 소자의 특성을 향상하는 효과가 있다.Therefore, in the method of manufacturing a gate oxide film of the semiconductor device of the present invention, by forming a silicon germanium gate, implanting fluorine ions, and then performing a heat treatment process, fluorine suppresses the infiltration of boron and improves the short channel effect to improve the semiconductor device. It is effective to improve the characteristics of the.
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