KR20060061359A - 데이터 블록 전송 방법 및 장치 - Google Patents

데이터 블록 전송 방법 및 장치 Download PDF

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Publication number
KR20060061359A
KR20060061359A KR1020067003363A KR20067003363A KR20060061359A KR 20060061359 A KR20060061359 A KR 20060061359A KR 1020067003363 A KR1020067003363 A KR 1020067003363A KR 20067003363 A KR20067003363 A KR 20067003363A KR 20060061359 A KR20060061359 A KR 20060061359A
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KR
South Korea
Prior art keywords
signaling
bit
bits
electronic unit
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020067003363A
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English (en)
Korean (ko)
Inventor
존 마이클 보켄하겐
라우라 마리 줌브루넨
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR20060061359A publication Critical patent/KR20060061359A/ko
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Small-Scale Networks (AREA)
  • Dc Digital Transmission (AREA)
KR1020067003363A 2003-09-11 2004-09-10 데이터 블록 전송 방법 및 장치 Abandoned KR20060061359A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/660,217 US7392445B2 (en) 2003-09-11 2003-09-11 Autonomic bus reconfiguration for fault conditions
US10/660,217 2003-09-11

Publications (1)

Publication Number Publication Date
KR20060061359A true KR20060061359A (ko) 2006-06-07

Family

ID=34273623

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067003363A Abandoned KR20060061359A (ko) 2003-09-11 2004-09-10 데이터 블록 전송 방법 및 장치

Country Status (9)

Country Link
US (1) US7392445B2 (enExample)
EP (1) EP1683018B1 (enExample)
JP (1) JP4392025B2 (enExample)
KR (1) KR20060061359A (enExample)
CN (1) CN100419701C (enExample)
AT (1) ATE367606T1 (enExample)
DE (1) DE602004007681T2 (enExample)
TW (1) TWI300527B (enExample)
WO (1) WO2005024633A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010110562A3 (ko) * 2009-03-22 2010-12-23 엘지전자주식회사 무선 통신 시스템에서 참조 신호 전송 방법 및 장치

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070233930A1 (en) * 2006-03-14 2007-10-04 International Business Machines Corporation System and method of resizing PCI Express bus widths on-demand
US8953292B2 (en) * 2007-05-30 2015-02-10 Infineon Technologies Ag Bus interface and method for short-circuit detection
JP5099222B2 (ja) * 2008-05-30 2012-12-19 富士通株式会社 情報処理装置、転送回路及び情報処理装置のエラー制御方法
JP5163298B2 (ja) * 2008-06-04 2013-03-13 富士通株式会社 情報処理装置、データ伝送装置及びデータ伝送方法
WO2015006946A1 (en) * 2013-07-18 2015-01-22 Advanced Micro Devices, Inc. Partitionable data bus
US9454419B2 (en) 2013-07-18 2016-09-27 Advanced Micro Devices, Inc. Partitionable data bus
US10642951B1 (en) * 2018-03-07 2020-05-05 Xilinx, Inc. Register pull-out for sequential circuit blocks in circuit designs

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2473820A1 (fr) * 1980-01-11 1981-07-17 Telecommunications Sa Procede et systeme d'initialisation de la securisation d'une ligne d'une artere de transmission numerique
JP2825630B2 (ja) * 1990-09-07 1998-11-18 株式会社日立製作所 回線切替方式
JPH06259343A (ja) * 1993-03-10 1994-09-16 Hitachi Ltd 多重バス制御方式及びそれを用いたシステム
US5440538A (en) * 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5678065A (en) * 1994-09-19 1997-10-14 Advanced Micro Devices, Inc. Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency
US5875301A (en) * 1994-12-19 1999-02-23 Apple Computer, Inc. Method and apparatus for the addition and removal of nodes from a common interconnect
US5867645A (en) 1996-09-30 1999-02-02 Compaq Computer Corp. Extended-bus functionality in conjunction with non-extended-bus functionality in the same bus system
US6366557B1 (en) * 1997-10-31 2002-04-02 Nortel Networks Limited Method and apparatus for a Gigabit Ethernet MAC (GMAC)
US6018810A (en) * 1997-12-12 2000-01-25 Compaq Computer Corporation Fault-tolerant interconnection means in a computer system
JP3994360B2 (ja) * 1998-05-20 2007-10-17 ソニー株式会社 情報処理装置、情報処理方法、および記録媒体
US7100071B2 (en) * 1998-07-16 2006-08-29 Hewlett-Packard Development Company, L.P. System and method for allocating fail-over memory
US6466718B1 (en) * 1999-12-29 2002-10-15 Emc Corporation Method and apparatus for transmitting fiber-channel and non-fiber channel signals through common cable
US6574753B1 (en) * 2000-01-10 2003-06-03 Emc Corporation Peer link fault isolation
JP2003014819A (ja) * 2001-07-03 2003-01-15 Matsushita Electric Ind Co Ltd 半導体配線基板，半導体デバイス，半導体デバイスのテスト方法及びその実装方法
KR100448709B1 (ko) * 2001-11-29 2004-09-13 삼성전자주식회사 데이터 버스 시스템 및 그 제어방법
US6898730B1 (en) * 2001-11-30 2005-05-24 Western Digital Technologies, Inc. System and method for fail-over switching in a disk storage medium
JP4188602B2 (ja) * 2002-01-10 2008-11-26 株式会社日立製作所 クラスタ型ディスク制御装置及びその制御方法
US6918068B2 (en) * 2002-04-08 2005-07-12 Harris Corporation Fault-tolerant communications system and associated methods
US7362697B2 (en) * 2003-01-09 2008-04-22 International Business Machines Corporation Self-healing chip-to-chip interface
US7194581B2 (en) * 2003-06-03 2007-03-20 Intel Corporation Memory channel with hot add/remove

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010110562A3 (ko) * 2009-03-22 2010-12-23 엘지전자주식회사 무선 통신 시스템에서 참조 신호 전송 방법 및 장치
US8483165B2 (en) 2009-03-22 2013-07-09 Lg Electronics Inc. Method and apparatus for transmitting a reference signal in a wireless communication system

Also Published As

Publication number Publication date
US7392445B2 (en) 2008-06-24
DE602004007681T2 (de) 2008-04-30
DE602004007681D1 (de) 2007-08-30
JP2007505380A (ja) 2007-03-08
TWI300527B (en) 2008-09-01
ATE367606T1 (de) 2007-08-15
EP1683018A1 (en) 2006-07-26
WO2005024633A1 (en) 2005-03-17
TW200516402A (en) 2005-05-16
CN100419701C (zh) 2008-09-17
CN1849589A (zh) 2006-10-18
JP4392025B2 (ja) 2009-12-24
US20050058086A1 (en) 2005-03-17
EP1683018B1 (en) 2007-07-18

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