KR20050090913A - Manufacturing method for metal line on semiconductor device - Google Patents

Manufacturing method for metal line on semiconductor device Download PDF

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Publication number
KR20050090913A
KR20050090913A KR1020040016257A KR20040016257A KR20050090913A KR 20050090913 A KR20050090913 A KR 20050090913A KR 1020040016257 A KR1020040016257 A KR 1020040016257A KR 20040016257 A KR20040016257 A KR 20040016257A KR 20050090913 A KR20050090913 A KR 20050090913A
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South Korea
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forming
interlayer insulating
tungsten plug
insulating film
semiconductor device
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KR1020040016257A
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Korean (ko)
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송병수
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매그나칩 반도체 유한회사
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Priority to KR1020040016257A priority Critical patent/KR20050090913A/en
Publication of KR20050090913A publication Critical patent/KR20050090913A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

본 발명은 반도체 장치의 배선 형성방법에 관한 것으로, 반도체 장치가 형성된 기판의 상부에 층간절연막을 형성하고, 그 층간절연막에 콘택홀을 형성한 후, 그 콘택홀에 위치하는 텅스텐 플러그를 형성하는 단계와; 상기 층간절연막의 상부일부를 식각하여 텅스텐 플러그의 상부와 그 상부의 측면부 일부를 돌출시키는 단계와; 상기 돌출된 텅스텐 플러그의 상부에 도전성 버퍼층을 형성하는 단계와; 상기 구조의 상부전면에 층간절연막을 증착하고, 그 층간절연막에 콘택홀을 형성하여 상기 도전성 버퍼층을 노출시킨 후, 그 콘택홀 내에 금속배선을 형성하는 단계로 이루어진다. 이와 같은 구성에 의하여 본 발명은 텅스텐 플러그를 형성하고, 세정하는 과정에서 그 텅스텐 플러그의 상부에 존재할 수 있는 산화막을 제거하여 텅스텐 플러그와 금속배선의 접촉 저항 증가를 방지함과 아울러 누설 전류의 발생을 방지할 수 있는 효과가 있다.The present invention relates to a method for forming a wiring of a semiconductor device, the method comprising: forming an interlayer insulating film on top of a substrate on which the semiconductor device is formed, forming a contact hole in the interlayer insulating film, and then forming a tungsten plug located in the contact hole Wow; Etching a portion of the upper portion of the interlayer insulating layer to protrude an upper portion of the tungsten plug and a portion of a side portion thereof; Forming a conductive buffer layer on the protruding tungsten plug; Depositing an interlayer insulating film on the upper surface of the structure, forming a contact hole in the interlayer insulating film to expose the conductive buffer layer, and then forming metal wiring in the contact hole. In this way, the present invention forms a tungsten plug and, in the process of cleaning, removes an oxide film that may be present on the top of the tungsten plug, thereby preventing an increase in contact resistance between the tungsten plug and the metal wiring and preventing the occurrence of leakage current. There is an effect that can be prevented.

Description

반도체 장치의 배선 형성방법{manufacturing method for metal line on semiconductor device} Manufacturing method for metal line on semiconductor device

본 발명은 반도체 장치의 배선 형성방법에 관한 것으로, 특히 콘택과 금속배선의 접촉 저항의 증가와 누설전류의 발생을 방지할 수 있는 반도체 장치의 배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method of a semiconductor device, and more particularly, to a wiring forming method of a semiconductor device capable of preventing an increase in contact resistance between a contact and a metal wiring and generation of a leakage current.

도 1은 종래 반도체 장치의 배선 형성방법에 따라 금속배선을 형성한 반도체 장치의 단면도이다.1 is a cross-sectional view of a semiconductor device in which metal wirings are formed in accordance with a wiring forming method of a conventional semiconductor device.

이와 같은 구성의 반도체 장치는 다음의 공정에 의해 제조된다.The semiconductor device of such a structure is manufactured by the following process.

먼저, 기판(1)의 상부에 게이트(2)와 게이트 측벽(3)을 형성하고, 그 상부전면에 층간절연막(4)을 증착한 후, 그 층간절연막(4)에 콘택홀을 형성하여 그 게이트(2)를 노출시킨다.First, the gate 2 and the gate sidewall 3 are formed on the substrate 1, the interlayer insulating film 4 is deposited on the upper surface thereof, and then a contact hole is formed in the interlayer insulating film 4. The gate 2 is exposed.

그 다음, 상기 구조의 상부전면에 텅스텐의 증착과 평탄화 과정을 통해 상기 콘택홀 내에 플러그(5)를 형성한다.Next, the plug 5 is formed in the contact hole through the deposition and planarization of tungsten on the upper surface of the structure.

그 다음, 상기 구조의 상부에 다시 층간절연막(6)을 증착한 후, 그 층간절연막(6)에 콘택홀을 형성한 후, Cu를 매립하여 금속배선(10)을 형성한다.Then, after the interlayer insulating film 6 is deposited again on the structure, a contact hole is formed in the interlayer insulating film 6, and then Cu is embedded to form a metal wiring 10.

상기의 과정에서 상기 텅스텐 플러그(5)를 형성하고, 층간절연막(6)의 증착한 후, 텅스텐 플러그(5)의 상부를 노출시키고 세정공정을 수행하게 되며, 이때 텅스텐 플러그(5)의 상부 계면에는 산화막이 형성될 수 있으며, 이는 금속배선(10)과 플러그(5) 사이의 접촉저항을 증가시키고, 누설전류를 발생시키는 원인이 된다.In the above process, the tungsten plug 5 is formed, the interlayer insulating film 6 is deposited, the upper portion of the tungsten plug 5 is exposed and a cleaning process is performed. At this time, the upper interface of the tungsten plug 5 is performed. An oxide film may be formed in the film, which increases the contact resistance between the metal wire 10 and the plug 5 and causes a leakage current.

또한 상기 금속배선 형성과정에서 Cu가 플러그(5)의 측면으로 확산되어 소자의 특성을 열화시키는 문제점이 있었다. In addition, Cu is diffused to the side of the plug 5 in the process of forming the metal wiring, thereby deteriorating the characteristics of the device.

상기와 같은 문제점을 감안한 본 발명은 텅스텐 플러그의 상부가 산화되는 것을 방지함과 아울러 금속배선 형성과정에서 Cu가 확산되는 것을 방지할 수 있는 반도체 장치의 배선 형성방법을 제공함에 그 목적이 있다. In view of the above problems, an object of the present invention is to provide a wiring forming method of a semiconductor device which can prevent the upper portion of the tungsten plug from being oxidized and also prevent Cu from being diffused during the metal wiring forming process.

상기와 같은 목적을 달성하기 위한 본 발명은 반도체 장치가 형성된 기판의 상부에 층간절연막을 형성하고, 그 층간절연막에 콘택홀을 형성한 후, 그 콘택홀에 위치하는 텅스텐 플러그를 형성하는 단계와; 상기 층간절연막의 상부일부를 식각하여 텅스텐 플러그의 상부와 그 상부의 측면부 일부를 돌출시키는 단계와; 상기 돌출된 텅스텐 플러그의 상부에 도전성 버퍼층을 형성하는 단계와; 상기 구조의 상부전면에 층간절연막을 증착하고, 그 층간절연막에 콘택홀을 형성하여 상기 도전성 버퍼층을 노출시킨 후, 그 콘택홀 내에 금속배선을 형성하는 단계로 구성함에 그 특징이 있다. The present invention for achieving the above object comprises the steps of forming an interlayer insulating film on top of the substrate on which the semiconductor device is formed, forming a contact hole in the interlayer insulating film, and then forming a tungsten plug located in the contact hole; Etching a portion of the upper portion of the interlayer insulating layer to protrude an upper portion of the tungsten plug and a portion of a side portion thereof; Forming a conductive buffer layer on the protruding tungsten plug; And depositing an interlayer insulating film on the upper surface of the structure, forming a contact hole in the interlayer insulating film to expose the conductive buffer layer, and then forming a metal wiring in the contact hole.

상기와 같이 구성되는 본 발명의 실시 예를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다. An embodiment of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따르는 반도체 장치의 배선 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트(2)와 게이트 측벽(3)을 포함하는 반도체 소자를 제조한 후, 그 반도체 소자가 형성된 기판(1)의 상부전면에 층간절연막(4)을 증착하고, 그 층간절연막(4)에 콘택홀을 형성하여 반도체 소자의 특정 영역을 노출시키고, 그 콘택홀에 텅스텐 플러그(5)를 형성하는 단계(도 2a)와; 상기 층간절연막(4)의 상부일부를 식각하여 상기 텅스텐 플러그(5)의 상부일부를 돌출시키는 단계(도 2b)와; 상기 구조의 상부전면에 Ta막(7)과 TaN막(8)을 순차적으로 증착하는 단계(도 2c)와; 포토레지스트(PR) 패턴을 이용하는 선택적 식각공정으로 상기 증착된 Ta막(7)과 TaN막(8)을 패터닝하여 상기 플러그(5)의 상부와 측면의 노출을 방지하는 단계(도 2d)와; 상기 구조의 상부전면에 질화막(9)과 층간절연막(6)을 순차적으로 증착하는 단계(도 2e)와; 포토레지스트(PR)를 사용하는 식각공정으로 상기 층간절연막(6)과 질화막(9)에 콘택을 형성하여 그 하부의 TaN막(8)의 상부를 노출시키는 단계(도 2f)와; 상기 노출된 TaN막(8)의 상부에 금속배선(10)을 형성하는 단계(도 2g)로 구성된다.2A to 2G are cross-sectional views of a wiring manufacturing process of a semiconductor device according to the present invention. As shown therein, a semiconductor device including a gate 2 and a gate sidewall 3 is manufactured on an upper portion of a substrate 1. Thereafter, an interlayer insulating film 4 is deposited on the upper surface of the substrate 1 on which the semiconductor device is formed, and a contact hole is formed in the interlayer insulating film 4 to expose a specific region of the semiconductor device, and the tungsten in the contact hole Forming a plug 5 (FIG. 2A); Etching an upper portion of the interlayer insulating film 4 to protrude an upper portion of the tungsten plug 5 (FIG. 2B); Sequentially depositing a Ta film 7 and a TaN film 8 on the upper surface of the structure (FIG. 2C); Patterning the deposited Ta film 7 and the TaN film 8 by a selective etching process using a photoresist (PR) pattern to prevent exposure of the upper and side surfaces of the plug 5 (FIG. 2D); Sequentially depositing a nitride film (9) and an interlayer insulating film (6) on the upper surface of the structure (FIG. 2E); Forming an contact between the interlayer insulating film 6 and the nitride film 9 by an etching process using a photoresist PR to expose an upper portion of the TaN film 8 below (FIG. 2F); The metal wiring 10 is formed on the exposed TaN film 8 (FIG. 2G).

이하, 상기와 같이 구성된 본 발명 반도체 장치의 배선 형성방법을 좀 더 상세히 설명한다.Hereinafter, the wiring forming method of the semiconductor device of the present invention configured as described above will be described in more detail.

먼저, 도 2a에 도시한 바와 같이 기판(1)의 상부에 게이트(2)와 게이트 측벽(3)을 포함하는 반도체 소자를 제조한다.First, as shown in FIG. 2A, a semiconductor device including a gate 2 and a gate sidewall 3 is manufactured on the substrate 1.

그 다음, 상기 반도체 소자가 형성된 기판(1)의 상부전면에 층간절연막(4)을 증착하고, 사진식각공정을 통해 상기 층간절연막(4)에 콘택홀을 형성하여 반도체 소자의 특정 영역을 노출시킨다. Next, an interlayer insulating film 4 is deposited on the upper surface of the substrate 1 on which the semiconductor device is formed, and a contact hole is formed in the interlayer insulating film 4 through a photolithography process to expose a specific region of the semiconductor device. .

그 다음, 상기 구조의 상부전면에 텅스텐을 증착하고, 그 텅스텐을 평탄화하여 상기 콘택홀을 통해 노출된 반도체 장치의 특정영역에 접하는 텅스텐 플러그(5)를 형성한다.Next, tungsten is deposited on the upper surface of the structure, and the tungsten is planarized to form a tungsten plug 5 in contact with a specific region of the semiconductor device exposed through the contact hole.

이때 상기 텅스텐 플러그(5)의 상부는 평탄화과정과 세정과정 등에 의해 산화막이 위치할 수 있다.In this case, an oxide film may be positioned on the tungsten plug 5 by a planarization process and a cleaning process.

그 다음, 도 2b에 도시한 바와 같이 상기 층간절연막(4)의 상부일부를 식각하여 상기 텅스텐 플러그(5)의 상부일부를 돌출시킨다.Next, as shown in FIG. 2B, an upper portion of the interlayer insulating layer 4 is etched to protrude an upper portion of the tungsten plug 5.

이때의 식각공정으로 상기 텅스텐 플러그(5)의 상부에 위치하는 산화막도 모두 제거할 수 있게 된다.At this time, it is possible to remove all the oxide film located on the upper portion of the tungsten plug (5).

그 다음, 도 2c에 도시한 바와 같이 상기 구조의 상부전면에 Ta막(7)과 TaN막(8)을 순차적으로 증착한다.Then, as shown in FIG. 2C, a Ta film 7 and a TaN film 8 are sequentially deposited on the upper surface of the structure.

상기 TaN막(8)은 그 상부가 평탄하도록 형성한다.The TaN film 8 is formed so that its top is flat.

그 다음, 도 2d에 도시한 바와 같이 사진식각공정을 통해 상기 증착된 Ta막(7)과 TaN막(8)을 패터닝하여 상기 플러그(5)의 상부와 측면의 노출되는 것을 방지한다.Next, as illustrated in FIG. 2D, the deposited Ta film 7 and the TaN film 8 are patterned through a photolithography process to prevent exposure of the upper and side surfaces of the plug 5.

그 다음, 도 2e에 도시한 바와 같이 상기 구조의 상부전면에 질화막(9)과 층간절연막(6)을 순차적으로 증착한다.Next, as shown in FIG. 2E, a nitride film 9 and an interlayer insulating film 6 are sequentially deposited on the upper surface of the structure.

그 다음, 도 2f에 도시한 바와 같이 사진식각공정을 통해 상기 증착된 층간절연막(6)과 질화막(9)에 콘택홀을 형성하여, TaN막(8)의 상부를 노출시킨다.Next, as shown in FIG. 2F, a contact hole is formed in the deposited interlayer insulating film 6 and the nitride film 9 through a photolithography process to expose the upper portion of the TaN film 8.

그 다음, 도 2g에 도시한 바와 같이 상기 구조의 상부전면에 Cu를 증착하고, 평탄화하여 금속배선(10)을 형성한다.Next, as shown in FIG. 2G, Cu is deposited on the upper surface of the structure and planarized to form a metal wiring 10.

상기 금속배선(10)을 형성하는 과정에서 Cu는 Ta막(7)과 TaN막(8)이 버퍼로 작용하여 상기 Cu가 텅스텐 플러그(5)의 측면을 타고 확산되는 것을 방지할 수 있게 된다. In the process of forming the metal wiring 10, Cu can prevent the Cu from spreading along the side surface of the tungsten plug 5 by the Ta film 7 and the TaN film 8 serving as a buffer.

상기한 바와 같이 본 발명은 텅스텐 플러그를 형성하고, 세정하는 과정에서 그 텅스텐 플러그의 상부에 존재할 수 있는 산화막을 제거하여 텅스텐 플러그와 금속배선의 접촉 저항 증가를 방지함과 아울러 누설 전류의 발생을 방지할 수 있는 효과가 있다.As described above, the present invention forms a tungsten plug and, in the process of cleaning, removes an oxide film that may be present on the top of the tungsten plug to prevent an increase in contact resistance between the tungsten plug and the metal wiring and to prevent occurrence of leakage current. It can work.

또한 본 발명은 금속배선을 형성하기 이전에 텅스텐 플러그의 노출을 방지하는 버퍼층을 두어 그 금속배선 형성을 위한 금속이 텅스텐 플러그의 측면을 타고 확산되는 것을 방지하여, 반도체 장치의 특성 열화를 방지할 수 있는 효과가 있다.In addition, the present invention provides a buffer layer to prevent the exposure of the tungsten plug before forming the metal wiring to prevent the metal for forming the metal wiring to diffuse along the side of the tungsten plug, thereby preventing the deterioration of characteristics of the semiconductor device It has an effect.

도 1은 종래 반도체 장치의 배선 형성방법에 따라 제조한 반도체 장치의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a semiconductor device manufactured by a wiring forming method of a conventional semiconductor device.

도 2a 내지 도 2g는 본 발명에 따르는 반도체 장치의 배선 제조공정 수순단면도. 2A to 2G are cross-sectional views of wiring manufacturing processes of a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판 2:게이트1: Substrate 2: Gate

3:측벽 4,6:층간절연막3: side wall 4, 6: interlayer insulating film

5:플러그 7:Ta막5: Plug 7: Ta film

8:TaN막 9:질화막8: TaN film 9: nitride film

10:금속배선 10: metal wiring

Claims (2)

반도체 장치가 형성된 기판의 상부에 층간절연막을 형성하고, 그 층간절연막에 콘택홀을 형성한 후, 그 콘택홀에 위치하는 텅스텐 플러그를 형성하는 단계와;Forming an interlayer insulating film on the substrate on which the semiconductor device is formed, forming a contact hole in the interlayer insulating film, and then forming a tungsten plug located in the contact hole; 상기 층간절연막의 상부일부를 식각하여 텅스텐 플러그의 상부와 그 상부의 측면부 일부를 돌출시키는 단계와;Etching a portion of the upper portion of the interlayer insulating layer to protrude an upper portion of the tungsten plug and a portion of a side portion thereof; 상기 돌출된 텅스텐 플러그의 상부에 도전성 버퍼층을 형성하는 단계와;Forming a conductive buffer layer on the protruding tungsten plug; 상기 구조의 상부전면에 층간절연막을 증착하고, 그 층간절연막에 콘택홀을 형성하여 상기 도전성 버퍼층을 노출시킨 후, 그 콘택홀 내에 금속배선을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 장치의 배선 형성방법.Forming an interlayer insulating film on the upper surface of the structure, forming a contact hole in the interlayer insulating film to expose the conductive buffer layer, and then forming a metal wiring in the contact hole. Way. 제 1항에 있어서, 상기 도전성 버퍼층은 순차 적층된 Ta와 TaN막인 것을 특징으로 하는 반도체 장치의 배선 형성방법.The method of forming a semiconductor device according to claim 1, wherein the conductive buffer layer is a Ta and a TaN film sequentially stacked.
KR1020040016257A 2004-03-10 2004-03-10 Manufacturing method for metal line on semiconductor device KR20050090913A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706807B1 (en) * 2006-02-03 2007-04-12 삼성전자주식회사 A stacked transistor having a protruded impurity region and manufacturing method using the same
KR100850069B1 (en) * 2006-12-27 2008-08-04 동부일렉트로닉스 주식회사 Method for manufacturing metal line of semiconductor device
US11791261B2 (en) 2020-04-14 2023-10-17 Winbond Electronics Corp. Semiconductor structures and methods for forming the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706807B1 (en) * 2006-02-03 2007-04-12 삼성전자주식회사 A stacked transistor having a protruded impurity region and manufacturing method using the same
KR100850069B1 (en) * 2006-12-27 2008-08-04 동부일렉트로닉스 주식회사 Method for manufacturing metal line of semiconductor device
US11791261B2 (en) 2020-04-14 2023-10-17 Winbond Electronics Corp. Semiconductor structures and methods for forming the same

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