KR20070102007A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20070102007A
KR20070102007A KR1020060033589A KR20060033589A KR20070102007A KR 20070102007 A KR20070102007 A KR 20070102007A KR 1020060033589 A KR1020060033589 A KR 1020060033589A KR 20060033589 A KR20060033589 A KR 20060033589A KR 20070102007 A KR20070102007 A KR 20070102007A
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South Korea
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interlayer insulating
forming
insulating layer
lower metal
insulating film
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KR1020060033589A
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Korean (ko)
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KR100833417B1 (en
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이현우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to prevent short between neighboring metal lines or upper and lower metal lines by removing the edge parts of the metal lines. A method for fabricating a semiconductor device includes the steps of: forming a first interlayer insulating layer(21) on a semiconductor substrate(20); forming a contact hole on the first interlayer insulating layer; filling a conductive layer for forming a drain contact(22); forming a second interlayer insulating layer(25) on the first interlayer insulating layer including the drain contact; forming a trench exposing the drain contact by selectively etching the second interlayer insulating layer; cleaning the trench; depositing a metal layer on a whole surface including the trench; forming a lower metal line(26) by planarizing the metal line for exposing the second interlayer insulating layer; applying photoresist on the whole surface including the lower metal line; etching an edge of the second interlayer insulating layer and the lower metal line and removing the photoresist; forming a third interlayer insulating layer(27) on the whole surface including the lower metal line; forming the contact hole exposing the lower metal line on the third interlayer insulating layer; and forming an upper metal line(28) by filling the conductive layer in the contact hole.

Description

반도체 소자의 제조방법{Method for fabricating semiconductor device}Method for fabricating semiconductor device {Method for fabricating semiconductor device}

도 1 및 도 2는 종래 기술에 따른 반도체 소자의 불량 프로파일을 나타낸 도면1 and 2 illustrate a defect profile of a semiconductor device according to the prior art.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도3A to 3C are cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

20 : 반도체 기판 22 : 드레인 콘택20: semiconductor substrate 22: drain contact

26 : 하부 금속배선 28 : 상부 금속배선26: lower metal wiring 28: upper metal wiring

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 이웃하는 금속배선들간 단락 현상 및 연결을 원치 않는 상하부 금속배선들간 단락 현상을 방지하기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for preventing a short circuit between neighboring metal wires and an undesired short circuit between upper and lower metal wires.

도 1을 참조하면, 현재 70nm 낸드 플래쉬 메모리에서 하부 금속배선(16)은 반도체 기판(10)상에 형성된 제 1 층간절연막(11)에 드레인 콘택홀을 형성하고, 드레인 콘택홀에 도전막을 매립하여 드레인 콘택(12)을 형성하고, 그 위에 버퍼 산화막(13), 스탑퍼 질화막(14) 및 제 2 층간절연막(15)을 순차 형성하고, 다마신 공정으로 제 2 층간절연막(15), 스탑퍼 질화막(14) 및 버퍼 산화막(13)에 트렌치를 형성한 후, 트렌치내에 금속막을 매립하여 형성하고 있다. Referring to FIG. 1, in the current 70nm NAND flash memory, the lower metal wiring 16 forms a drain contact hole in the first interlayer insulating film 11 formed on the semiconductor substrate 10, and fills a conductive film in the drain contact hole. The drain contact 12 is formed, the buffer oxide film 13, the stopper nitride film 14, and the second interlayer insulating film 15 are sequentially formed thereon, and the second interlayer insulating film 15 and the stopper are formed by a damascene process. After the trench is formed in the nitride film 14 and the buffer oxide film 13, a metal film is embedded in the trench.

이 같은 공정에서 트렌치 형성을 위한 식각 공정시 제 2 층간절연막(15)이 오버 에치(over etch)되거나 트렌치내에 금속막을 매립하기 전에 실시하는 크리닝(cleaning) 공정이 과도하게 진행될 경우, A 부분에 나타낸 바와 같이 제 2 층간절연막(15)의 탑(top) 부분 프로파일(profile)이 좁아지게 되며 이에 따라 이웃하는 하부 금속배선(16)들이 서로 단락(short)되는 불량이 발생될 가능성이 커지게 된다.In this process, if the second interlayer insulating film 15 is over etched during the etching process for forming the trench or the cleaning process is performed excessively before the metal film is buried in the trench, As described above, the top portion profile of the second interlayer insulating layer 15 is narrowed, which increases the possibility of a short circuit between the adjacent lower metal wires 16 shortening.

그리고, 하부 금속배선(16)을 형성한 이후에 하부 금속배선(16)을 포함한 전면에 제 3 층간절연막(17)을 형성하고 제 3 층간절연막(17)에 하부 금속배선(16)의 일부를 노출하는 콘택홀을 형성한 후 콘택홀에 금속막을 매립하여 상부 금속배선(18)을 형성하는데, 상부 금속배선(18)이 하부 금속배선(16)상에 정(正) 얼라인(align)되지 않고 미스 얼라인(mis-align)되면 도 2의 B 부분에 나타낸 바와 같이 연결을 원치 않는 상부 금속배선(18)과 하부 금속배선(16)이 서로 단락(short)되는 불량이 발생될 가능성이 크다. After the lower metal wiring 16 is formed, a third interlayer insulating film 17 is formed on the entire surface including the lower metal wiring 16, and a part of the lower metal wiring 16 is formed on the third interlayer insulating film 17. After forming the exposed contact hole, the metal film is buried in the contact hole to form the upper metal wiring 18. The upper metal wiring 18 is not aligned on the lower metal wiring 16. If it is mis-aligned, as shown in part B of FIG. 2, there is a high possibility that a short circuit between the upper metal wiring 18 and the lower metal wiring 16 that is not connected is likely to occur. .

이러한 불량은 디자인 룰(design rule)이 감소함에 따라서 더욱 악화되게 되므로 소자 집적화에 많은 어려움이 있다.This defect is worsened as the design rule is reduced, so there are many difficulties in device integration.

본 발명은 전술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로써, 이웃하는 금속배선들간 단락 현상 및 연결을 원치 않는 상하부 금속배선들간 단락 현상을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-described problems of the prior art, and provides a method of manufacturing a semiconductor device capable of preventing a short circuit between neighboring metal wires and a short circuit between upper and lower metal wires that are not connected. There is a purpose.

본 발명에 따른 반도체 소자의 제조방법은 반도체 기판상에 층간절연막을 형성하고 층간절연막에 트렌치를 형성하는 단계와, 트렌치에 하부 금속배선을 형성하는 단계와, 하부 금속배선의 에지 부분을 일정 두께 식각하는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate, forming a trench in the interlayer insulating film, forming a lower metal wiring in the trench, and etching a predetermined thickness of an edge portion of the lower metal wiring. It includes a step.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허청구범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도이다.3A to 3C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a를 참조하면, 반도체 기판(20)상에 제 1 층간절연막(21)을 형성하고 제 1 층간절연막(21)에 콘택홀을 형성하고 콘택홀에 도전막 예를 들어, 폴리실리콘막 을 매립하여 드레인 콘택(22)을 형성한다. 그리고, 드레인 콘택(22)을 포함한 제 1 층간절연막(21)상에 제 2 층간절연막(25)을 형성한다. 이때, 제 2 층간절연막(25)을 형성하기 전에 버퍼 산화막(23)과 스탑퍼 질화막(24)을 더 형성함이 바람직하다.Referring to FIG. 3A, a first interlayer insulating film 21 is formed on a semiconductor substrate 20, a contact hole is formed in the first interlayer insulating film 21, and a conductive film, for example, a polysilicon film is buried in the contact hole. The drain contact 22 is formed. A second interlayer insulating film 25 is formed on the first interlayer insulating film 21 including the drain contact 22. At this time, it is preferable to further form the buffer oxide film 23 and the stopper nitride film 24 before the second interlayer insulating film 25 is formed.

차후에 형성하는 하부 금속배선 높이는 버퍼 산화막(23), 스탑퍼 질화막(24) 및 제 2 층간절연막(25)의 두께에 의해 정해지는데, 기존에 1800Å 정도였던 하부 금속배선의 높이가 2000~2300Å로 늘어나도록 버퍼 산화막(23), 스탑퍼 질화막(24) 및 제 2 층간절연막(25)의 두께를 적절히 조절한다.The lower metal wiring height to be formed later is determined by the thickness of the buffer oxide film 23, the stopper nitride film 24, and the second interlayer insulating film 25. The height of the lower metal wiring, which was about 1800Å, increases to 2000 to 2300Å. The thicknesses of the buffer oxide film 23, the stopper nitride film 24, and the second interlayer insulating film 25 are adjusted appropriately.

이어, 제 2 층간절연막(25), 스탑퍼 질화막(24) 및 버퍼 산화막(23)을 선택적으로 식각하여 드레인 콘택(22)을 노출하는 트렌치를 형성하고, 크리닝(cleaning) 공정한다. 그런 다음, 트렌치를 포함한 전면에 금속막을 증착하고 제 2 층간절연막(25)이 노출되도록 금속막에 대하여 평탄화 공정을 실시하여 하부 금속배선(26)을 형성한다.Subsequently, the second interlayer insulating film 25, the stopper nitride film 24, and the buffer oxide film 23 are selectively etched to form trenches that expose the drain contact 22, and a cleaning process is performed. Thereafter, a metal film is deposited on the entire surface including the trench, and the lower metal wiring 26 is formed by performing a planarization process on the metal film so that the second interlayer insulating film 25 is exposed.

트렌치 형성을 위한 식각 공정시 오버 에치(over etch)되거나, 크리닝(cleaning) 공정이 과도하게 진행되게 되면 제 2 층간절연막(25) 탑(top) 부분의 프로파일(profile)이 좁아지게 되어 이웃하는 하부 금속배선(26)들이 서로 단락(short)될 가능성이 커지게 된다.When the etching process for forming the trench is over etched or the cleaning process is excessively processed, the profile of the top portion of the second interlayer insulating layer 25 becomes narrow and the neighboring lower portion The possibility that the metal wires 26 are shorted with each other increases.

이에, 단락을 유발하는 하부 금속배선(26)의 에지 부분을 제거하기 위하여 하부 금속배선(26)을 포함한 전면에 포토레지스트(PR)를 도포하고 제 2 층간절연막(25)과 이에 인접한 하부 금속배선(26)의 에지 부분을 노출하는 포토레지스 트(PR)를 형성한다.Accordingly, in order to remove the edge portion of the lower metal wiring 26 causing a short circuit, a photoresist PR is coated on the entire surface including the lower metal wiring 26 and the second interlayer insulating film 25 and the lower metal wiring adjacent thereto are formed. A photoresist PR is formed to expose the edge portion of (26).

도 3b를 참조하면, 포토레지스트(PR)를 마스크로 노출된 제 2 층간절연막(25)과 하부 금속배선(26)의 에지 부분을 일정 두께 식각하고, 포토레지스트(PR)를 제거한다.Referring to FIG. 3B, the edge portions of the second interlayer insulating layer 25 and the lower metal interconnection 26 exposing the photoresist PR as a mask are etched to a predetermined thickness, and the photoresist PR is removed.

하부 금속배선(26)의 에지 부분이 식각됨에 따라서 하부 금속배선(26) 탑 부분의 면적이 감소되어 시트 저항(Rs)이 줄어들게 되는데, 하부 금속배선(26)의 높이를 기존보다 증가시켰으므로 하부 금속배선(26) 면적 감소에 따른 시트 저항 감소분은 보상되게 된다.As the edge portion of the lower metal line 26 is etched, the area of the top portion of the lower metal line 26 is reduced to decrease the sheet resistance Rs. Since the height of the lower metal line 26 is increased than before, The decrease in sheet resistance caused by the reduction in the area of the metal wiring 26 is compensated for.

도 3c를 참조하면, 하부 금속배선(26)을 포함한 전면에 제 3 층간절연막(27)을 형성하고 제 3 층간절연막(27)에 하부 금속배선(26)을 노출하는 콘택홀을 형성하고 콘택홀내에 도전막을 매립하여 상부 금속배선(28)을 형성한다.Referring to FIG. 3C, the third interlayer insulating layer 27 is formed on the entire surface including the lower metal interconnection 26, and the contact hole exposing the lower metal interconnection 26 is formed on the third interlayer insulating layer 27 and the contact hole is formed. A conductive film is embedded in the upper metal wiring 28 to form the upper portion.

이상으로, 본 발명에 따른 반도체 소자 제조를 완료한다.This completes the manufacture of the semiconductor device according to the present invention.

상술한 바와 같이, 본 발명은 단락 현상의 원인이 되는 금속배선의 에지 부분을 제거하여 이웃하는 금속배선들간 단락 현상을 방지할 수 있고 연결을 원치 않는 상하부 금속배선들간 단락 현상을 방지할 수 있다.As described above, the present invention can prevent the short circuit between neighboring metal wirings by eliminating the edge portion of the metal wiring which causes the short circuit and prevent the short circuit between the upper and lower metal wires which are not connected.

Claims (4)

반도체 기판상에 층간절연막을 형성하고 상기 층간절연막에 트렌치를 형성하는 단계; Forming an interlayer insulating film on the semiconductor substrate and forming a trench in the interlayer insulating film; 상기 트렌치에 금속배선을 형성하는 단계;Forming a metal wire in the trench; 상기 금속배선의 에지 부분을 일정 두께 식각하는 단계를 포함하는 반도체 소자의 제조방법.And etching the edge portion of the metal line by a predetermined thickness. 제 1항에 있어서,The method of claim 1, 상기 금속배선의 높이가 2000~2300Å인 반도체 소자의 제조방법.The method of manufacturing a semiconductor device having a height of the metal wiring is 2000 ~ 2300Å. 제 1항에 있어서,The method of claim 1, 상기 층간절연막과 상기 금속배선의 에지 부분을 일정 두께 식각하는 단계 이후에 상기 결과물상에 상부 층간절연막을 형성하는 단계;Forming an upper interlayer insulating film on the resultant after etching the edge portion of the interlayer insulating film and the metal wiring by a predetermined thickness; 상기 상부 층간절연막에 상기 금속배선을 노출하는 콘택홀을 형성하고 상기 콘택홀에 상부 금속배선을 형성하는 단계를 더 포함하는 반도체 소자의 제조방법.And forming a contact hole exposing the metal wiring in the upper interlayer insulating layer and forming an upper metal wiring in the contact hole. 제 1항에 있어서,The method of claim 1, 상기 층간절연막을 형성하기 전에 버퍼 산화막과 스탑퍼 질화막을 형성하는 단계를 더 포함하는 반도체 소자의 제조방법.And forming a buffer oxide film and a stopper nitride film before forming the interlayer insulating film.
KR1020060033589A 2006-04-13 2006-04-13 Method for fabricating semiconductor device KR100833417B1 (en)

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US9379118B2 (en) 2013-11-13 2016-06-28 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including interlayer wiring structures

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