KR20050064328A - Method for forming metal line of semiconductor device - Google Patents
Method for forming metal line of semiconductor device Download PDFInfo
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- KR20050064328A KR20050064328A KR1020030095686A KR20030095686A KR20050064328A KR 20050064328 A KR20050064328 A KR 20050064328A KR 1020030095686 A KR1020030095686 A KR 1020030095686A KR 20030095686 A KR20030095686 A KR 20030095686A KR 20050064328 A KR20050064328 A KR 20050064328A
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
본 발명은 반도체 소자의 금속 배선 형성방법을 개시한다. 개시된 본 발명의 방법은, 반도체 기판 상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 식각하여 제1크기의 콘택홀을 형성하는 단계와, 상기 제1크기의 콘택홀을 갖는 층간절연막을 열처리해서 콘택홀 상부 측벽 모서리 부분을 라운딩시켜 제1크기 보다 큰 제2크기의 콘택홀을 형성하는 단계와, 상기 제2크기의 콘택홀을 매립하도록 텅스텐막을 기판 및 층간절연막 상에 증착하는 단계와, 상기 층간절연막이 노출되도록 텅스텐막을 에치 백(etch-back)하여 텅스텐 플러그를 형성하는 단계와, 상기 텅스텐 플러그를 포함한 층간절연막 상에 금속막을 증착하는 단계와, 상기 금속막을 패터닝하는 단계를 포함한다. 본 발명에 따르면, 콘택홀이 형성된 층간절연막을 열처리하여 리플로우 공정을 진행함으로써, 콘택홀 하부의 폭을 줄이고 콘택홀 상부의 표면적을 확장함으로써, 콘택홀 매립시 스텝커버리지를 향상시켜 보이드 발생을 억제할 수 있고, 금속 배선과의 오버레이 마진(Overlay Margin)을 확보할 수 있다. The present invention discloses a method for forming metal wiring in a semiconductor device. The disclosed method includes forming an interlayer insulating film on a semiconductor substrate, etching the interlayer insulating film to form a first contact hole, and heat treating the interlayer insulating film having the first size contact hole. Forming a contact hole of a second size larger than the first size by rounding a corner portion of the upper sidewall edge of the contact hole; depositing a tungsten film on the substrate and the interlayer insulating film to fill the contact hole of the second size; Etching back the tungsten film to expose the interlayer insulating film, forming a tungsten plug, depositing a metal film on the interlayer insulating film including the tungsten plug, and patterning the metal film. According to the present invention, by performing a reflow process by heat-treating the interlayer insulating film on which the contact holes are formed, reducing the width of the lower contact hole and expanding the surface area of the upper contact hole, thereby improving step coverage when filling the contact hole, thereby suppressing void generation It is possible to secure an overlay margin with the metal wiring.
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 상세하게는, 플러그와 금속배선 간의 콘택 마진을 높힐 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것이다. The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to a method for forming a metal wiring of a semiconductor device that can increase the contact margin between the plug and the metal wiring.
최근 소자의 크기가 80nm 이하 급 소자가 연구됨에 따라 포토 및 식각 공정에 의한 패턴 형성에 어려움이 있다. 현재 대부분의 디램에 있어서 100nm 급 소자의 경우 포토리소그라피 공정은 KrF 광원을 기본으로 크리티갈 레이어(Critical layer)를 형성하고 있으며 대부분의 금속층의 경우 RIE를 기본으로 패턴을 형성하고 있으며, 이는 점점 한계에 도달하고 있다. Recently, as the size of devices having a size of 80 nm or less has been studied, it is difficult to form patterns by photo and etching processes. For most DRAMs, the photolithography process forms a critical layer based on the KrF light source in the case of 100nm class devices, and most of the metal layers form a pattern based on the RIE. Reaching.
따라서, 미세 패턴을 형성하기 위하여 제1선폭의 감광막 패턴을 형성하고, 이를 다시 리플로우 공정을 통해 원하는 제1선폭 보다 작은 미세 선폭을 구현하고 있다. Accordingly, a photoresist pattern having a first line width is formed in order to form a fine pattern, and a fine line width smaller than the desired first line width is realized through a reflow process.
종래의 금속 배선은 하부의 텅스텐 플러그와 연결되고 있으며, 전술한 바와 같이 소자의 미세 패턴화가 가속됨에 따라, 패터닝이 어려워지며, 이에 따른 콘택부분의 마진 확보가 중요한 이슈가 되고 있다. Conventional metal wiring is connected to the lower tungsten plug, and as described above, as the fine patterning of the device is accelerated, patterning becomes difficult, thereby securing a margin of the contact portion is an important issue.
이하, 종래의 기술에 따른 반도체 소자의 금속 배선 형성방법에 대해 간략히 설명하기로 한다. Hereinafter, a method for forming metal wirings of a semiconductor device according to the related art will be briefly described.
도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 공정별 단면도이다. 1A to 1C are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device according to the related art.
도 1a를 참고하면, 반도체 기판(11) 상에 층간절연막(12)을 증착하고, 그런다음, 상기 층간절연막을 패터닝하여 기판을 노출시키는 콘택홀(13)을 형성한다. Referring to FIG. 1A, an interlayer insulating layer 12 is deposited on a semiconductor substrate 11, and then, the interlayer insulating layer is patterned to form a contact hole 13 exposing the substrate.
도 1b를 참조하면, 상기 콘택홀(13)을 매립하도록 기판 및 층간절연막 상에 텅스텐막을 증착한다. 다음으로, 상기 텅스텐막을 층간절연막이 노출되도록 CMP하여 플러그(14)를 형성한다. Referring to FIG. 1B, a tungsten film is deposited on the substrate and the interlayer insulating film to fill the contact hole 13. Next, the tungsten film is CMP to expose the interlayer insulating film to form a plug 14.
도 1c를 참조하면, 상기 층간절연막 및 텅스텐 플러그 상에 금속막을 증착한다. 이어서, 상기 금속막 상에 금속배선이 형성될 영역을 한정하는 감광막 패턴을 형성한다. 그런다음, 상기 감광막 패턴을 식각 장벽으로 이용해서 금속막을 식각하여 금속 배선(15)을 형성한다. 이어서, 상기 감광막 패턴을 제거한다. Referring to FIG. 1C, a metal film is deposited on the interlayer insulating film and the tungsten plug. Subsequently, a photoresist pattern is formed on the metal film to define a region where the metal wiring is to be formed. Then, the metal film is etched using the photoresist pattern as an etch barrier to form the metal wiring 15. Next, the photoresist pattern is removed.
그러나, 전술한 바와 같은 종래의 기술에 따른 반도체 소자의 금속 배선 형성방법은 콘택홀의 상부가 기존의 습식 및 건식 식각 방법처럼 라운딩(Rounding) 되지 못하고 샤프(Sharp)하게 형성된다. However, in the metal wire forming method of the semiconductor device according to the related art as described above, the upper portion of the contact hole is sharply formed without being rounded like the conventional wet and dry etching methods.
상기한 콘택홀의 모양으로 플러그 형성을 위한 금속 증착시 매립이 불완전하게 이루어진다. 즉, 콘택의 스텝커버리지(stepcoverage) 악화로 금속이 콘택홀 바닥면까지 흘러 내려감에 따라 완벽하게 콘택홀을 매립하지 못하고 보이드(Void)가 형성된다. 이에따라, 수분등의 침투에 의한 메탈 부식등의 소자 특성에 악영향을 미치게 된다. 또한, 콘택홀의 크기가 작아짐에 따라 금속 배선과 콘택간에 얼라인 마진이 줄어들며, 이에따른 접촉 저항 증가 등의 문제점이 있다. In the form of the contact hole, the filling of the metal for the formation of the plug is made incompletely. That is, as the metal flows down to the bottom of the contact hole due to deterioration of the step coverage of the contact, voids are formed without filling the contact holes completely. This adversely affects device characteristics such as metal corrosion due to penetration of moisture and the like. In addition, as the size of the contact hole decreases, the alignment margin between the metal wiring and the contact decreases, and thus there is a problem such as an increase in contact resistance.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출된 것으로써, 금속배선 형성시 금속 배선 콘택에서 발생하는 보이드를 억제하고, 금속배선과 금속 배선 콘택과의 오버레이(Overlay) 및 얼라인(aligned) 마진을 확보할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, to suppress the voids generated in the metal wiring contact when forming the metal wiring, to overlay and align the metal wiring and the metal wiring contact It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can secure an (aligned) margin.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 반도체 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 제1크기의 콘택홀을 형성하는 단계; 상기 제1크기의 콘택홀을 갖는 층간절연막을 열처리해서 콘택홀 상부 측벽 모서리 부분을 라운딩시켜 제1크기 보다 큰 제2크기의 콘택홀을 형성하는 단계; 상기 제2크기의 콘택홀을 매립하도록 텅스텐막을 기판 및 층간절연막 상에 증착하는 단계; 상기 층간절연막이 노출되도록 텅스텐막을 에치 백(etch-back)하여 텅스텐 플러그를 형성하는 단계; 상기 텅스텐 플러그를 포함한 층간절연막 상에 금속막을 증착하는 단계; 및 상기 금속막을 패터닝하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법을 제공한다. In order to achieve the above object, the present invention, forming an interlayer insulating film on a semiconductor substrate; Etching the interlayer insulating layer to form a first contact hole; Heat-treating the interlayer insulating layer having the first-sized contact holes to round the corners of the upper sidewall edges of the contact holes to form a second-sized contact hole larger than the first size; Depositing a tungsten film on a substrate and an interlayer insulating film to fill the second sized contact hole; Forming a tungsten plug by etching back the tungsten film to expose the interlayer insulating film; Depositing a metal film on the interlayer insulating film including the tungsten plug; And it provides a method for forming a metal wiring of the semiconductor device comprising the step of patterning the metal film.
여기서, 상기 층간절연막은 BPSG를 이용하며, 열처리 공정시 라운딩 정도를 제어하도록 보론 또는 인의 농도를 조절하여 형성한다. Here, the interlayer insulating film is formed using BPSG, by adjusting the concentration of boron or phosphorus to control the degree of rounding during the heat treatment process.
(실시예)(Example)
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예에 대해서 상세히 설명하기로 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도이다. 2A through 2F are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(21) 상에 층간절연막(22)을 형성하고, 이를 식각하여 기판을 노출시키는 콘택홀(23)을 형성한다. Referring to FIG. 2A, an interlayer insulating layer 22 is formed on a semiconductor substrate 21, and a contact hole 23 exposing the substrate is formed by etching the interlayer insulating layer 22.
여기서, 상기 층간절연막(23)은 산화막 계열의 BPSG을 이용하여 형성한다. 또한, 후속의 열처리 리플로우 공정에서 원하는 선폭을 정의하기 위하여 BPSG의 붕소(Boron) 및 인(phosphorous)의 농도 비율을 조절한다. Here, the interlayer insulating film 23 is formed using an oxide film-based BPSG. In addition, in the subsequent heat treatment reflow process, the concentration ratio of boron and phosphorous of BPSG is adjusted to define the desired line width.
도 2b를 참조하면, 상기 콘택홀(23)이 형성된 층간절연막(22)을 열처리하는 리플로우 공정을 통해 콘택홀 상부를 라운딩시킨다. Referring to FIG. 2B, the upper portion of the contact hole is rounded through a reflow process of heat treating the interlayer insulating layer 22 having the contact hole 23 formed thereon.
통상의 포토리소그라피 공정에서 KrF(248nm) 광원을 사용하여 감광막 패턴을 형성할때, 소정 크기의 감광막 패턴을 형성하고, 이를 리플로우 공정을 통해 미세 패턴을 형성하였다. When a photoresist pattern was formed using a KrF (248 nm) light source in a conventional photolithography process, a photoresist pattern having a predetermined size was formed, and a fine pattern was formed through the reflow process.
여기서, 전술한 감광막 리플로우 공정을 응용하여 콘택홀(23)이 형성된 층간절연막(22)을 열처리함으로써 열처리에 의한 산화막이 형성되며, 이에따라, 선폭이 줄어들고 콘택홀 상부는 라운딩된다. Here, by applying the above-described photoresist film reflow process, the interlayer insulating film 22 having the contact holes 23 is heat-treated to form an oxide film by heat treatment. Accordingly, the line width is reduced and the upper portion of the contact hole is rounded.
도 2c를 참조하면, 상기 라운딩된 콘택홀(23)을 완전히 매립하도록 기판(21) 상에 텅스텐막을 증착하고, 이를 층간절연막(22)이 노출되도록 CMP 및 에치 백(etch-back)하여 플러그(24)를 형성한다. Referring to FIG. 2C, a tungsten film is deposited on the substrate 21 to completely fill the rounded contact hole 23, and the CMP and the etch back are exposed to expose the interlayer insulating film 22. 24).
도 2d를 참조하면, 상기 층간절연막(22) 및 플러그(24) 상에 금속막(25)을 형성한다. Referring to FIG. 2D, a metal film 25 is formed on the interlayer insulating film 22 and the plug 24.
도 2e를 참조하면, 상기 층간절연막(22) 상에 감광막을 도포하고, 이를 노광 및 현상하여 금속 배선이 형성될 영역을 한정하는 감광막 패턴(26)을 형성한다. Referring to FIG. 2E, a photosensitive film is coated on the interlayer insulating film 22, and the photosensitive film pattern 26 is exposed and developed to form a photosensitive film pattern 26 defining a region where a metal wiring is to be formed.
도 2f를 참조하면, 상기 감광막 패턴을 식각 장벽으로 금속막(25)을 식각하여 금속배선(25a)을 형성한다. 여기서, 상기 콘택홀(23)을 열처리를 통한 라운딩을 형성하여 콘택홀 상부의 표면적이 넓어져 금속배선(25a)의 오버레이 마진(Overlay Margin)을 확보할 수 있어, 접촉 저항을 감소시킬 수 있다. Referring to FIG. 2F, the metal layer 25 is etched using the photoresist pattern as an etch barrier to form the metal wiring 25a. In this case, the contact hole 23 may be rounded by heat treatment to increase the surface area of the upper contact hole, thereby securing an overlay margin of the metal wiring 25a, thereby reducing contact resistance.
이어서, 감광막 패턴을 스트립 공정을 통해 제거한다. The photoresist pattern is then removed via a strip process.
전술한 바와 같이, 층간절연막을 열처리를 통한 리플로우 공정으로 상부의 표면적을 넓히고 콘택홀 하부의 폭을 줄임으로써, 콘택홀 매립시 스텝커버리지가 향상되어 보이드를 없앨 수 있고, 금속 배선과의 얼라인 마진을 확보할 수 있다. As described above, by increasing the surface area of the upper portion and reducing the width of the lower portion of the contact hole by the reflow process through heat treatment of the interlayer insulating film, the step coverage is improved when the contact hole is buried, and voids are aligned with the metal wiring. Margin can be secured.
이상에서와 같이, 본 발명에 따르면, 콘택홀이 형성된 층간절연막을 열처리하여 리플로우 공정을 진행함으로써, 콘택홀 하부의 폭을 줄이고 콘택홀 상부의 표면적을 확장함으로써, 콘택홀 매립시 스텝커버리지를 향상시켜 보이드 발생을 억제할 수 있고, 금속 배선과의 오버레이 마진(Overlay Margin)을 확보할 수 있다. As described above, according to the present invention, by performing a reflow process by heat-treating the interlayer insulating film on which the contact hole is formed, by reducing the width of the lower contact hole and expanding the surface area of the upper contact hole, the step coverage when filling the contact hole is improved It is possible to suppress the generation of voids and to secure an overlay margin with the metal wiring.
이상에서는 본 발명을 특정의 바람직한 실시예에 대하여 도시하고 설명하였으나, 본 발명은 상기한 실시예에 한정되지 아니하며, 특허 청구의 범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형이 가능할 것이다.While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not limited to the embodiments described above, but in the field to which the invention pertains without departing from the spirit of the invention as claimed in the claims. Any person with ordinary knowledge will be able to make various modifications.
도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 공정별 단면도. 1A to 1C are cross-sectional views for each process for explaining a method for forming metal wirings of a semiconductor device according to the related art.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도. 2A through 2F are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 설명* * Description of the main parts of the drawings *
21: 반도체 기판 22: 층간절연막 21: semiconductor substrate 22: interlayer insulating film
23: 콘택홀 24: 플러그23: contact hole 24: plug
25: 금속막 25a: 금속 배선25: metal film 25a: metal wiring
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| KR1020030095686A KR20050064328A (en) | 2003-12-23 | 2003-12-23 | Method for forming metal line of semiconductor device |
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| KR1020030095686A KR20050064328A (en) | 2003-12-23 | 2003-12-23 | Method for forming metal line of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100762233B1 (en) * | 2005-11-25 | 2007-10-01 | 주식회사 하이닉스반도체 | Method for fabricating interlayer of dielectric in semiconductor device |
| KR100833423B1 (en) | 2006-04-06 | 2008-05-29 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100833417B1 (en) | 2006-04-13 | 2008-05-29 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| CN102376639A (en) * | 2010-08-10 | 2012-03-14 | 海力士半导体有限公司 | Method of forming metal lines of semiconductor device |
-
2003
- 2003-12-23 KR KR1020030095686A patent/KR20050064328A/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100762233B1 (en) * | 2005-11-25 | 2007-10-01 | 주식회사 하이닉스반도체 | Method for fabricating interlayer of dielectric in semiconductor device |
| KR100833423B1 (en) | 2006-04-06 | 2008-05-29 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US7572729B2 (en) | 2006-04-06 | 2009-08-11 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| KR100833417B1 (en) | 2006-04-13 | 2008-05-29 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| CN102376639A (en) * | 2010-08-10 | 2012-03-14 | 海力士半导体有限公司 | Method of forming metal lines of semiconductor device |
| KR101135766B1 (en) * | 2010-08-10 | 2012-04-16 | 에스케이하이닉스 주식회사 | Method of forming metal line for semiconductor device |
| US8193088B2 (en) | 2010-08-10 | 2012-06-05 | Hynix Semiconductor Inc. | Method of forming metal lines of semiconductor device |
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