KR20100078340A - Method for fabricating metal layer - Google Patents

Method for fabricating metal layer Download PDF

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Publication number
KR20100078340A
KR20100078340A KR1020080136574A KR20080136574A KR20100078340A KR 20100078340 A KR20100078340 A KR 20100078340A KR 1020080136574 A KR1020080136574 A KR 1020080136574A KR 20080136574 A KR20080136574 A KR 20080136574A KR 20100078340 A KR20100078340 A KR 20100078340A
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KR
South Korea
Prior art keywords
metal
film
plug
wiring
forming
Prior art date
Application number
KR1020080136574A
Other languages
Korean (ko)
Inventor
김준환
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080136574A priority Critical patent/KR20100078340A/en
Publication of KR20100078340A publication Critical patent/KR20100078340A/en

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    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: A method for fabricating a metal wiring is provided to improve the reliability of a semiconductor device by successively forming metal films for a metal wiring, a barrier, and a metal plug and subsequently forming the metal plug and the metal wiring through one etching process. CONSTITUTION: Metal films for a metal wiring, a barrier, and a metal plug are successively formed on a semiconductor substrate. A first hard mask is formed to define the metal wiring on the upper side of the metal film for the metal plug. A second hard mask is formed to define the metal plug on the upper side of the first hard mask. An etching process is performed using the first and the second hard masks as an etching mask, and the metal plug, a patterned barrier(204a) and the metal wiring(202a) are formed. An interlayer insulating film(212) is formed to fill the metal plug.

Description

METHOD FOR FABRICATING METAL LAYER}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring forming method capable of forming a metal plug and a metal wiring through one deposition process and an etching process.

As design rules decrease due to high integration of semiconductor devices, the aspect ratio of contact holes (or via holes) is gradually increasing, thereby increasing the difficulty and importance of the process of forming via and contact holes for metal wiring.

In general, aluminum has been most widely used as a metal via via material because the resistivity is low and the process is relatively easy when the design rule is cut, although aluminum does not have excellent via hole filling characteristics.

However, as design rules have been reduced, contact holes can not be filled with aluminum alone. Therefore, metal wiring forming technology employing tungsten plugs with aluminum wiring, which have a higher specific resistance than via aluminum but have excellent via hole filling characteristics, are used.

1A to 1C are views illustrating a method of manufacturing metal wirings of a semiconductor device according to the related art.

As shown in FIG. 1A, the lower metal interconnection 102 is formed on the silicon substrate 100, and the interlayer insulating layer 104 is formed on the lower metal interconnection 102, as shown in FIG. 1B. The interlayer insulating layer 104 is etched to form a via hole 106.

Subsequently, as shown in FIG. 1C, tungsten, which is a metal material, is embedded in the via hole 106 through tungsten film deposition and etchback in the via hole 106 to form a tungsten plug 108. The upper metal wiring 110, that is, the aluminum wiring is formed on the 108.

Here, the process of forming the via hole 106 by etching the interlayer insulating film 104 and the process of forming the tungsten plug 108 are performed in different processes.

As described above, the interlayer insulating layer may not be etched to the lower metal wiring due to a foreign material such as a polymer or an etching non-setting error generated in the process of forming the via hole during the metal plug forming process, so that the lower metal wiring may not be opened. As a result, the tungsten plug does not come into contact with the lower metal wires, thereby lowering the reliability of the semiconductor device.

In addition, the conventional metal wire forming method may cause alignment defects in which the metal material flows laterally when the metal material is filled in the via hole due to an overlay miss during the photo process for forming the via hole.

The present invention sequentially forms the metal film for the metal wiring, the barrier metal film, and the metal plug metal film, and then forms the metal plug and the metal wiring through one front etching process.

A metal wiring forming method according to the present invention comprises the steps of sequentially forming a metal wiring metal film, a barrier metal film and a metal plug metal film on a semiconductor substrate, and a metal wiring for defining a metal wiring on the upper part of the metal plug metal film. Forming a hard mask, forming a second hard mask for defining a metal plug on the first hard mask, and using an entire surface etching process using the first and second hard masks as an etch mask. Etching the metal plug metal film, the barrier metal film, and the metal wiring metal film to form a metal plug, a patterned barrier metal film, and a metal wiring, and forming an interlayer insulating film to completely fill the metal plug. .

The present invention can improve the reliability of the semiconductor device by sequentially forming the metal wiring metal film, the barrier metal film and the metal plug metal film, and then forming the metal plug and the metal wiring through one front etching process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

An embodiment of the present invention describes a metal wiring formation method that can form a metal plug and a metal wiring through one front etching process after sequentially forming a metal wiring metal film, a barrier metal film and a metal plug metal film. .

2A to 2E are cross-sectional views illustrating a process of forming a metal wiring according to an embodiment of the present invention.

As shown in FIG. 2A, the metal wiring metal film 202, the barrier metal film 204, and the metal plug metal film 206 are sequentially formed on the semiconductor substrate 200. Although not shown, the lower metal wire and the metal plug may be formed on the semiconductor substrate 200.

In addition, the metal wiring metal film 202 may be formed using aluminum, copper, or the like, and the metal plug metal film 206 may be formed using aluminum, tungsten, or the like. The barrier metal film 204 is formed between the wiring metal film 202 and the metal plug metal film 206 for EM (EletronMigration) and SM (StressMigration) characteristics of the metal wiring, and forms Ti / TiN and Ta / TaN. It can be formed using.

The barrier metal film 204 in the present invention is used as an etch stop film in the process described later. For this purpose, a recipe for maintaining the metal material and the selectivity of the metal plug 206 for at least 4: 1 level is required. For this purpose, the amount of N2 gas needs to be increased during the etching process.

Then, as shown in FIG. 2B, the first hard mask 208 for defining the metal wiring is formed on the metal film 206 for the metal plug, and then the metal is formed on the first hard mask 208. A second hard mask 210 is formed to define the plug.

The first and second hard masks 208 may be a photoresist pattern formed by applying a photoresist and then photographing and developing processes or an insulating layer pattern formed by depositing and etching an insulating film.

Then, as shown in FIGS. 2C and 2D, a front surface etching process using the first and second hard masks 208 and 210 as an etching mask is performed to form the metal plug 206a and the metal wiring 202a. That is, for the metal plug exposed by the first hard mask 208 by performing full-side etching using the barrier metal film 204 as the etch stop film and the first and second hard masks 208 and 210 as the etching mask. By etching the metal film 206 and etching the first hard mask 208 exposed on the second hard mask 210, the patterned metal plug metal film 206a and the patterned first hard mask 208a are etched. To form.

The patterned metal plug metal film 206a is etched by etching the patterned metal plug metal film 206a patterned by the first hard mask 208a patterned through the continuous etching process, and the metal film for patterned metal plug ( By etching the barrier metal film 202 and the metal wiring metal film 202 exposed by the 206a, the barrier metal film 204a patterned with the metal wiring 202a is formed.

As described above, according to the present invention, through one deposition process, that is, a deposition process for forming the metal wiring metal film 202, the barrier metal film 204, and the metal plug metal film 206, and one front etching process. The metal plug 206b and the metal wiring 202a can be formed.

Then, as shown in FIG. 2E, the interlayer insulating film 212 is formed so that the metal plug 206b is completely embedded, thereby completing the process of forming the metal wiring 202a and the metal plug 206b. That is, the interlayer insulating film 212 is deposited so that the metal plug 206b is completely embedded, and then the planarization process such as chemical mechanical polishing (CMP: CMP) is performed to expose the upper portion of the metal plug 206b. Flatten 212.

It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1A through 1C are cross-sectional views illustrating a conventional metal wire forming process.

2A to 2E are cross-sectional views illustrating a process of forming a metal wiring according to an embodiment of the present invention.

Description of the Related Art

200: semiconductor substrate 202: metal film for metal wiring

204: barrier metal film 206: metal film for metal plug

208: first hard mask 210: second hard mask

212: interlayer insulating film

Claims (7)

Sequentially forming a metal film for metal wiring, a barrier metal film, and a metal plug metal film on a semiconductor substrate; Forming a first hard mask to define a metal wiring on the metal film for the metal plug; Forming a second hard mask on top of the first hard mask to define a metal plug; Etching the metal plug metal film, the barrier metal film, and the metal wiring metal film through a front etching process using the first and second hard masks as an etching mask to form a metal plug, a patterned barrier metal film, and a metal wire; , Forming an interlayer insulating film to completely fill the metal plug Metal wiring forming method comprising a. The method of claim 1, Forming the metal wires, Patterning the first hard mask and patterning the metal plug metal film by performing a front surface etching process using the barrier metal film as an etch stop and using the first and second hard masks as an etch mask; Etching the patterned metal plug metal film exposed by the patterned first hard mask to form a metal plug, and forming the barrier metal film and the metal wiring metal film exposed by the patterned metal plug metal film. Etching to form metal lines Metal wiring forming method comprising a. The method of claim 1, The barrier metal film is a Ti / TiN film or a Ta / TaN film. The method of claim 1, The first hard mask is formed using a photoresist or an insulating film. The method of claim 1, The second hard mask is formed using a photoresist or an insulating film. The method of claim 1, The metal wiring metal film is formed using copper or aluminum. The method of claim 1, The metal plug metal film is formed using aluminum or tungsten.
KR1020080136574A 2008-12-30 2008-12-30 Method for fabricating metal layer KR20100078340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080136574A KR20100078340A (en) 2008-12-30 2008-12-30 Method for fabricating metal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080136574A KR20100078340A (en) 2008-12-30 2008-12-30 Method for fabricating metal layer

Publications (1)

Publication Number Publication Date
KR20100078340A true KR20100078340A (en) 2010-07-08

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8564002B2 (en) 2011-01-05 2013-10-22 Samsung Display Co., Ltd. Organic light emitting display device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8564002B2 (en) 2011-01-05 2013-10-22 Samsung Display Co., Ltd. Organic light emitting display device and method for manufacturing the same

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