KR20050050875A - 반도체 소자 및 그 제조 방법 - Google Patents
반도체 소자 및 그 제조 방법 Download PDFInfo
- Publication number
- KR20050050875A KR20050050875A KR1020030084525A KR20030084525A KR20050050875A KR 20050050875 A KR20050050875 A KR 20050050875A KR 1020030084525 A KR1020030084525 A KR 1020030084525A KR 20030084525 A KR20030084525 A KR 20030084525A KR 20050050875 A KR20050050875 A KR 20050050875A
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- South Korea
- Prior art keywords
- fsg
- blocking
- blocking film
- forming
- semiconductor device
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 230000000903 blocking effect Effects 0.000 claims abstract description 99
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 11
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 45
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000011737 fluorine Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (9)
- 반도체 기판 위에 금속 배선을 형성하는 단계,상기 반도체 기판 및 금속 배선 위에 제1 차단막을 형성하는 단계,상기 제1 차단막 위에 제1 FSG를 형성하는 단계,상기 제1 FSG 위에 제2 차단막을 형성하는 단계,상기 제2 차단막 위에 제2 FSG를 형성하는 단계,상기 제2 FSG 위에 보호막을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.
- 제1항에서,상기 제1 차단막, 제1 FSG, 제2 차단막 및 제2 FSG는 동일한 장비에서 형성하는 반도체 소자의 제조 방법.
- 제2항에서,상기 제1 차단막 및 제2 차단막은 USG인 반도체 소자의 제조 방법.
- 제1항 내지 제3항 중 어느 한 항에서,상기 제1 차단막 및 제2 차단막의 두께는 30 내지 2000Å인 반도체 소자의 제조 방법.
- 제1항 내지 제3항 중 어느 한 항에서,상기 보호막을 평탄화하는 단계,평탄화 된 상기 보호막, 제2 FSG, 제2 차단막, 제1 FSG 및 제1 차단막을 관통하는 접촉 구멍을 형성하는 단계,상기 보호막 위에 형성되며, 상기 접촉 구멍을 통해 상기 금속 배선과 연결되는 배선층을 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.
- 제1항 내지 제3항 중 어느 한 항에서,상기 제2 FSG 위에 보호막을 형성하기 전에 상기 제2 FSG 위에 제3 차단막을 형성하는 단계,상기 제3 차단막 위에 제3 FSG를 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.
- 반도체 기판,상기 반도체 기판 위에 형성되어 있는 금속 배선,상기 반도체 기판 및 금속 배선 위에 형성되어 있는 제1 차단막,상기 제1 차단막 위에 형성되어 있는 제1 FSG,상기 제1 FSG 위에 형성되어 있는 제2 차단막,상기 제2 차단막 위에 형성되어 있는 제2 FSG,상기 제2 FSG 위에 형성되어 있는 보호막를 포함하고,상기 제1 차단막 및 제2 차단막은 USG인 반도체 소자.
- 제7항에서,상기 제1 차단막 및 제2 차단막의 두께는 30 내지 2000Å인 반도체 소자.
- 제7항에서,상기 제2 FSG 위에 형성되어 있는 제3 차단막,상기 제3 차단막 위에 형성되어 있는 제3 FSG를 더 포함하는 반도체 소자.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0084525A KR100521436B1 (ko) | 2003-11-26 | 2003-11-26 | 반도체 소자 및 그 제조 방법 |
US10/998,221 US7183209B2 (en) | 2003-11-26 | 2004-11-26 | Semiconductor device and manufacturing method thereof |
US11/654,275 US20070117387A1 (en) | 2003-11-26 | 2007-01-16 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0084525A KR100521436B1 (ko) | 2003-11-26 | 2003-11-26 | 반도체 소자 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050050875A true KR20050050875A (ko) | 2005-06-01 |
KR100521436B1 KR100521436B1 (ko) | 2005-10-13 |
Family
ID=34588086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2003-0084525A KR100521436B1 (ko) | 2003-11-26 | 2003-11-26 | 반도체 소자 및 그 제조 방법 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7183209B2 (ko) |
KR (1) | KR100521436B1 (ko) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100850137B1 (ko) * | 2006-10-23 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 층간 절연막 제조방법 |
KR100861840B1 (ko) * | 2006-12-28 | 2008-10-07 | 동부일렉트로닉스 주식회사 | 반도체 소자의 패드 구조 및 그 형성 방법 |
KR100929732B1 (ko) * | 2007-12-24 | 2009-12-03 | 주식회사 동부하이텍 | 반도체 소자의 배선 제조방법 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100591185B1 (ko) * | 2004-12-23 | 2006-06-19 | 동부일렉트로닉스 주식회사 | 반도체 소자에서 금속배선의 형성방법 및 그 반도체 소자 |
CN110556295B (zh) * | 2019-09-26 | 2021-08-20 | 上海华虹宏力半导体制造有限公司 | 一种半导体器件以及形成方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6284677B1 (en) | 1997-04-18 | 2001-09-04 | United Semiconductor Corp. | Method of forming fluorosilicate glass (FSG) layers with moisture-resistant capability |
US5937323A (en) | 1997-06-03 | 1999-08-10 | Applied Materials, Inc. | Sequencing of the recipe steps for the optimal low-k HDP-CVD processing |
US6303523B2 (en) * | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6635583B2 (en) * | 1998-10-01 | 2003-10-21 | Applied Materials, Inc. | Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating |
US6218284B1 (en) | 1999-02-01 | 2001-04-17 | United Microelectronics, Corp. | Method for forming an inter-metal dielectric layer |
TW442903B (en) * | 2000-02-14 | 2001-06-23 | United Microelectronics Corp | Method for increasing the filling trench capability of dielectric layer |
US6376360B1 (en) | 2000-08-18 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacers |
US20040048468A1 (en) * | 2002-09-10 | 2004-03-11 | Chartered Semiconductor Manufacturing Ltd. | Barrier metal cap structure on copper lines and vias |
US6756321B2 (en) * | 2002-10-05 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant |
US7129162B2 (en) * | 2002-12-30 | 2006-10-31 | Texas Instruments Incorporated | Dual cap layer in damascene interconnection processes |
-
2003
- 2003-11-26 KR KR10-2003-0084525A patent/KR100521436B1/ko active IP Right Grant
-
2004
- 2004-11-26 US US10/998,221 patent/US7183209B2/en not_active Expired - Fee Related
-
2007
- 2007-01-16 US US11/654,275 patent/US20070117387A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100850137B1 (ko) * | 2006-10-23 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 층간 절연막 제조방법 |
KR100861840B1 (ko) * | 2006-12-28 | 2008-10-07 | 동부일렉트로닉스 주식회사 | 반도체 소자의 패드 구조 및 그 형성 방법 |
KR100929732B1 (ko) * | 2007-12-24 | 2009-12-03 | 주식회사 동부하이텍 | 반도체 소자의 배선 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR100521436B1 (ko) | 2005-10-13 |
US20050112867A1 (en) | 2005-05-26 |
US7183209B2 (en) | 2007-02-27 |
US20070117387A1 (en) | 2007-05-24 |
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