KR20050045674A - 반도체 소자의 저항 제조 방법 - Google Patents
반도체 소자의 저항 제조 방법 Download PDFInfo
- Publication number
- KR20050045674A KR20050045674A KR1020030079834A KR20030079834A KR20050045674A KR 20050045674 A KR20050045674 A KR 20050045674A KR 1020030079834 A KR1020030079834 A KR 1020030079834A KR 20030079834 A KR20030079834 A KR 20030079834A KR 20050045674 A KR20050045674 A KR 20050045674A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- resistance
- dopant
- film
- manufacturing
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 91
- 229920005591 polysilicon Polymers 0.000 claims abstract description 91
- 239000002019 doping agent Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002245 particle Substances 0.000 claims abstract description 3
- 230000008021 deposition Effects 0.000 claims description 12
- 238000010926 purge Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 239000010419 fine particle Substances 0.000 abstract description 5
- 238000009827 uniform distribution Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (6)
- 폴리실리콘으로 이루어진 저항막의 제조 방법에 있어서,반도체 기판 상부에 700℃∼1000℃ 온도에서 폴리실리콘을 증착하여 미립자 그레인 구조를 형성하는 단계;상기 폴리실리콘에 도펀트를 도핑하고 열처리하는 단계; 및상기 폴리실리콘을 패터닝하여 저항 패턴을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 저항 제조 방법.
- 제 1항에 있어서, 상기 도펀트 도핑 공정은 E13/㎠∼E14/㎠의 농도 범위와 20keV∼60keV의 에너지 크기로 진행하는 것을 특징으로 하는 반도체 소자의 저항 제조 방법.
- 폴리실리콘으로 이루어진 저항막의 제조 방법에 있어서,반도체 기판 상부에 폴리실리콘을 증착하되, 제 1높이로 폴리실리콘을 증착한 후에 퍼지하고 다시 제 2높이로 폴리실리콘을 증착한 후에 퍼지하여 이종 핵이 생성된 폴리실리콘막을 형성하는 단계;상기 폴리실리콘에 도펀트를 도핑하고 열처리하는 단계; 및상기 폴리실리콘을 패터닝하여 저항 패턴을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 저항 제조 방법.
- 제 3항에 있어서, 상기 도펀트 도핑 공정은 E13/㎠∼E14/㎠의 농도 범위와 20keV∼60keV의 에너지 크기로 진행하는 것을 특징으로 하는 반도체 소자의 저항 제조 방법.
- 제 3항에 있어서, 상기 폴리실리콘의 제 1 및 제 2높이는 각각 100℃∼500℃인 것을 특징으로 하는 반도체 소자의 저항 제조 방법.
- 제 3항에 있어서 증착 온도(200~600℃)가 낮아도 입자의 크기를 작게 할 수 있으며, 일반적인 CVD 이외에 저온 ALD, plasma를 이용한 증착법 등을 이용할 수 있다.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030079834A KR100593958B1 (ko) | 2003-11-12 | 2003-11-12 | 반도체 소자의 저항 제조 방법 |
JP2004326930A JP2005150726A (ja) | 2003-11-12 | 2004-11-10 | 半導体素子における抵抗の製造方法 |
US10/988,008 US20050130384A1 (en) | 2003-11-12 | 2004-11-12 | Method for manufacturing resistor of a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030079834A KR100593958B1 (ko) | 2003-11-12 | 2003-11-12 | 반도체 소자의 저항 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050045674A true KR20050045674A (ko) | 2005-05-17 |
KR100593958B1 KR100593958B1 (ko) | 2006-06-30 |
Family
ID=34651259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020030079834A KR100593958B1 (ko) | 2003-11-12 | 2003-11-12 | 반도체 소자의 저항 제조 방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20050130384A1 (ko) |
JP (1) | JP2005150726A (ko) |
KR (1) | KR100593958B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102010001397A1 (de) * | 2010-01-29 | 2011-08-04 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 | Halbleiterwiderstände, die in einem Halbleiterbauelement mit Metallgatestrukturen durch Verringern der Leitfähigleit eines metallenthaltenden Deckmaterials hergestellt sind |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5407851A (en) * | 1981-02-23 | 1995-04-18 | Unisys Corporation | Method of fabricating an electrically alterable resistive component on an insulating layer above a semiconductor substrate |
US4742020A (en) * | 1985-02-01 | 1988-05-03 | American Telephone And Telegraph Company, At&T Bell Laboratories | Multilayering process for stress accommodation in deposited polysilicon |
JPH0697683B2 (ja) * | 1989-11-10 | 1994-11-30 | 株式会社東芝 | 半導体装置の製造方法 |
JPH06188385A (ja) * | 1992-10-22 | 1994-07-08 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5489547A (en) * | 1994-05-23 | 1996-02-06 | Texas Instruments Incorporated | Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient |
US5618749A (en) * | 1995-03-31 | 1997-04-08 | Yamaha Corporation | Method of forming a semiconductor device having a capacitor and a resistor |
US5721166A (en) * | 1996-12-27 | 1998-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to increase the resistance of a polysilicon load resistor, in an SRAM cell |
US6114744A (en) * | 1997-03-14 | 2000-09-05 | Sanyo Electric Company | Semiconductor integration device and fabrication method of the same |
US6069398A (en) * | 1997-08-01 | 2000-05-30 | Advanced Micro Devices, Inc. | Thin film resistor and fabrication method thereof |
US5981352A (en) * | 1997-09-08 | 1999-11-09 | Lsi Logic Corporation | Consistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layer |
US6156602A (en) * | 1999-08-06 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Self-aligned precise high sheet RHO register for mixed-signal application |
US6670263B2 (en) * | 2001-03-10 | 2003-12-30 | International Business Machines Corporation | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size |
-
2003
- 2003-11-12 KR KR1020030079834A patent/KR100593958B1/ko active IP Right Grant
-
2004
- 2004-11-10 JP JP2004326930A patent/JP2005150726A/ja active Pending
- 2004-11-12 US US10/988,008 patent/US20050130384A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2005150726A (ja) | 2005-06-09 |
US20050130384A1 (en) | 2005-06-16 |
KR100593958B1 (ko) | 2006-06-30 |
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