KR20030076627A - Ｓｏｉ 재료의 제조 방법 - Google Patents

Ｓｏｉ 재료의 제조 방법 Download PDF

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Publication number
KR20030076627A
KR20030076627A KR10-2003-7009765A KR20037009765A KR20030076627A KR 20030076627 A KR20030076627 A KR 20030076627A KR 20037009765 A KR20037009765 A KR 20037009765A KR 20030076627 A KR20030076627 A KR 20030076627A
Authority
KR
South Korea
Prior art keywords
substrate
layer
silicon
insulating layer
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR10-2003-7009765A
Other languages
English (en)
Korean (ko)
Inventor
지웨이 팡
Original Assignee
베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. filed Critical 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크.
Publication of KR20030076627A publication Critical patent/KR20030076627A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1912—Preparing SOI wafers using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
KR10-2003-7009765A 2001-01-23 2002-01-10 Ｓｏｉ 재료의 제조 방법 Withdrawn KR20030076627A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/767,787 2001-01-23
US09/767,787 US20020098664A1 (en) 2001-01-23 2001-01-23 Method of producing SOI materials
PCT/US2002/000802 WO2002059946A2 (en) 2001-01-23 2002-01-10 Method of producing soi materials

Publications (1)

Publication Number Publication Date
KR20030076627A true KR20030076627A (ko) 2003-09-26

Family

ID=25080577

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-7009765A Withdrawn KR20030076627A (ko) 2001-01-23 2002-01-10 Ｓｏｉ 재료의 제조 방법

Country Status (6)

Country Link
US (1) US20020098664A1 (https=)
EP (1) EP1354339A2 (https=)
JP (1) JP2004528707A (https=)
KR (1) KR20030076627A (https=)
CN (1) CN1528010A (https=)
WO (1) WO2002059946A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101509267B1 (ko) * 2007-04-20 2015-04-06 코닝 인코포레이티드 유리계 기판을 제조하는 방법 및 이를 채용한 장치

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005333052A (ja) * 2004-05-21 2005-12-02 Sony Corp Ｓｉｍｏｘ基板及びその製造方法及びｓｉｍｏｘ基板を用いた半導体装置及びｓｉｍｏｘ基板を用いた電気光学表示装置の製造方法
CN100454483C (zh) * 2007-04-20 2009-01-21 中国电子科技集团公司第四十八研究所 一种离子注入厚膜soi晶片材料的制备方法
CN102386123B (zh) * 2011-07-29 2013-11-13 上海新傲科技股份有限公司 制备具有均匀厚度器件层的衬底的方法
US8575694B2 (en) 2012-02-13 2013-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Insulated gate bipolar transistor structure having low substrate leakage
JP2016224045A (ja) * 2015-05-29 2016-12-28 セイコーエプソン株式会社 抵抗素子の製造方法、圧力センサー素子の製造方法、圧力センサー素子、圧力センサー、高度計、電子機器および移動体

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661043A (en) * 1994-07-25 1997-08-26 Rissman; Paul Forming a buried insulator layer using plasma source ion implantation
US5710057A (en) * 1996-07-12 1998-01-20 Kenney; Donald M. SOI fabrication method
JPH11307455A (ja) * 1998-04-20 1999-11-05 Sony Corp 基板およびその製造方法
JP2000294513A (ja) * 1999-04-06 2000-10-20 Nec Corp Ｓｉ基板の酸化膜形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101509267B1 (ko) * 2007-04-20 2015-04-06 코닝 인코포레이티드 유리계 기판을 제조하는 방법 및 이를 채용한 장치

Also Published As

Publication number Publication date
WO2002059946A2 (en) 2002-08-01
JP2004528707A (ja) 2004-09-16
EP1354339A2 (en) 2003-10-22
WO2002059946A8 (en) 2003-10-09
US20020098664A1 (en) 2002-07-25
CN1528010A (zh) 2004-09-08
WO2002059946A3 (en) 2003-02-20

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E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000