KR20030067123A - A method for manufacturing of ball grid array package - Google Patents
A method for manufacturing of ball grid array package Download PDFInfo
- Publication number
- KR20030067123A KR20030067123A KR1020020006979A KR20020006979A KR20030067123A KR 20030067123 A KR20030067123 A KR 20030067123A KR 1020020006979 A KR1020020006979 A KR 1020020006979A KR 20020006979 A KR20020006979 A KR 20020006979A KR 20030067123 A KR20030067123 A KR 20030067123A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- wiring board
- bga package
- bonding
- manufacturing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 볼 그리드 어레이 패키지 제조방법에 관한 것으로 특히. 비용을절감시키고 특성을 향상시킬 수 있는 볼 그리드 어레이 패키지 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a ball grid array package, in particular. A method of manufacturing a ball grid array package that can reduce cost and improve characteristics.
반도체 산업에서 패키지 소자란 미세 회로가 설계된 반도체 칩을 실제 전자기기에 실장하여 사용할 수 있도록 플라스틱 수지나 세라믹으로 밀봉한 형태를 말한다. 따라서, 패키지 소자의 제조공정은 최종 제품화 공정이라 할 수 있다. 패키지 소자는 반도체 칩의 고집적화, 고속화 추세에 따라 그 중요성이 점점 커지고 있으며, 새로운 유형의 패키지 소자들이 속속 개발되고 있다.In the semiconductor industry, a package element refers to a form in which a semiconductor chip designed with a fine circuit is sealed with a plastic resin or ceramic so that the semiconductor chip can be mounted on an actual electronic device. Therefore, the manufacturing process of the package element may be referred to as the final productization process. Package devices are becoming increasingly important as semiconductor chips are becoming more integrated and faster, and new types of package devices are being developed.
그중 특히, 볼 그리드 어레이 패키지(이하, BGA 패키지 칭함)는 볼 형태의 외부 접속 단자가 패키지 일면 상에 배열되어 있는 구조를 갖는 것으로서, 일반적으로 많이 알려져 있는 쿼드 플랫 패키지(Quad Flat Package:QFP)에 비해 전기적 특성이 우수하고 다핀화에도 쉽게 대응이 가능하다는 이점이 있어서 현재 널리 이용되고 있다.Among them, a ball grid array package (hereinafter referred to as a BGA package) has a structure in which external connection terminals having a ball shape are arranged on one surface of a package, and are commonly used in a quad flat package (QFP), which is generally known. Compared with the advantages of excellent electrical characteristics and easy coping with multi-pinning, it is now widely used.
이러한 BGA 패키지 구현에 있어서 반도체 칩을 인쇄 회로 기판(Printed Circuit Board : PCB)에 실장할 때 대표적으로 사용되는 상호 접속 방법으로 와이어 본딩(wire bonding) 방법과 플립 칩 본딩(Filp Chip Bonding) 방법이 있다.In the BGA package implementation, there are a wire bonding method and a flip chip bonding method, which are representatively used when mounting a semiconductor chip on a printed circuit board (PCB). .
이하, 첨부된 도면을 참조하여 종래의 BGA 패키지에 대하여 설명하기로 한다.Hereinafter, a conventional BGA package will be described with reference to the accompanying drawings.
도 1은 종래의 센터 패드형 BGA 패키지를 나타낸 단면도이다.1 is a cross-sectional view showing a conventional center pad type BGA package.
도 1에 도시한 바와 같이 웨이퍼 상면에 집적회로를 형성하는 FAB(Fabrication) 공정이 끝난 상태에서 웨이퍼에 형성된 반도체 칩(20)을 개별적으로 분리하기 위한 소잉(sawing)공정을 실시한다.As shown in FIG. 1, a sawing process is performed to individually separate the semiconductor chips 20 formed on the wafer after the FAB (Fabrication) process of forming the integrated circuit on the upper surface of the wafer.
이어, 내부에 배선이 형성된 배선기판(10)이 공정에 투입됨에 따라 상기 배선기판(10) 상면에 접착제(11)를 도포하여 분리된 반도체 칩(20)을 접착시킨 후, 상기 반도체 칩(20)에 형성된 본딩패드(21)와 상기 배선기판(10)상의 소정의 배선 사이를 금속세선 즉, 와이어(60)를 이용하여 서로 전기적으로 연결시키는 와이어 본딩(wire bonding) 공정을 실시한다. 이때, 센터 패드형 패키지는 상기 반도체 칩(20)에 형성된 본딩패드(21)가 상기 반도체 칩(20) 중앙부에 위치한다. 따라서, 상기 배선기판(10)은 둘로 나뉘어지며, 상기 배선기판(10) 사이의 홀(12)을 통해 노출된 본딩패드(21)에 와이어(60)가 접합된다.Subsequently, as the wiring board 10 having wiring formed therein is introduced into the process, an adhesive 11 is applied to the upper surface of the wiring board 10 to bond the separated semiconductor chip 20, and then the semiconductor chip 20. A wire bonding process is performed to electrically connect the bonding pads 21 formed on the circuit board 10 and predetermined wires on the wiring board 10 to each other using metal thin wires, that is, wires 60. In this case, in the center pad type package, a bonding pad 21 formed on the semiconductor chip 20 is positioned at the center of the semiconductor chip 20. Therefore, the wiring board 10 is divided into two, and the wire 60 is bonded to the bonding pad 21 exposed through the hole 12 between the wiring board 10.
그리고 상기 반도체 칩(20)과 와이어(60)를 보호하기 위해 각각 EMC(Epoxy Molding Compound)로 몰딩(50a)(50b)하는 몰딩공정을 실시한 후, 스크린 프린팅(Screen Printing)을 통해 상기 배선기판(10) 저면에 형성된 볼 패드(Ball Pad)(41)상에 일정 패턴의 솔더 페이스트를 전사하여 플럭스 코팅(Flux Coating) 공정을 실시한다.In order to protect the semiconductor chip 20 and the wire 60, a molding process of molding 50a and 50b with EMC (Epoxy Molding Compound), respectively, is performed, and then the wiring board (Screen Printing) is used. 10) A flux coating process is performed by transferring a solder paste having a predetermined pattern onto the ball pad 41 formed on the bottom surface.
이어, 상기 배선기판(10) 저면에 일정 패턴으로 코팅된 플럭스(13)에 솔더 볼(40)을 부착시킨 후, 납의 열접합 공정인 리플로우(Reflow)를 수행하여 솔더 볼(40)을 배선기판(10)에 견고히 고정시킨다.Subsequently, after attaching the solder ball 40 to the flux 13 coated on the bottom surface of the wiring board 10 in a predetermined pattern, the solder ball 40 is wired by performing a reflow process, which is a thermal bonding process of lead. It is firmly fixed to the substrate 10.
그리고 클리닝 및 마킹 공정을 거쳐 완제품인 BGA 패키지를 출하하게 된다.After the cleaning and marking process, the finished BGA package will be shipped.
그러나 상기와 같은 종래의 센터 패드형 BGA 패키지에 있어서는 다음과 같은문제점이 있었다.However, the above-described conventional center pad type BGA package has the following problems.
반도체 칩에 형성된 본딩패드와 상기 배선기판상의 소정의 배선 사이를 금속세선을 이용하여 서로 전기적으로 연결시키는 와이어 본딩 공정시 금속세선의 길이에 따라 칩의 전기적 특성 저하를 일으킬 수 있다.In the wire bonding process in which a bonding pad formed on a semiconductor chip and predetermined wirings on the wiring board are electrically connected to each other by using metal thin wires, the electrical characteristics of the chip may be reduced depending on the length of the metal thin wires.
또한, 금속세선을 보호하기 위한 몰딩 공정은 패키지 사이즈가 변하거나 디바이스가 변할 때마다 신규제작을 해야하므로 제조비용이 상승한다.In addition, the molding process for protecting the fine metal wires requires a new manufacturing every time the package size or device changes, the manufacturing cost increases.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 금속세선을 사용하지 않고 반도체 칩의 본딩패드와 배선기판의 배선을 연결시키므로 제조비용을 절감하고, 디바이스 특성을 향상시킬 수 있는 BGA 패키지 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. BGA package manufacturing method which can reduce the manufacturing cost and improve the device characteristics by connecting the bonding pad of the semiconductor chip and the wiring of the wiring board without using the metal thin wire. The purpose is to provide.
도 1은 종래의 센터 패드형 BGA 패키지를 나타낸 단면도1 is a cross-sectional view showing a conventional center pad type BGA package.
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 센터 패드형 BGA 패키지 제조방법을 나타낸 공정 단면도2A to 2C are cross-sectional views illustrating a method for manufacturing a center pad type BGA package according to an embodiment of the present invention.
도 3은 본 발명의 다른 실시예에 따른 에지 패드형 BGA 패키지를 나타낸 단면도3 is a cross-sectional view showing an edge pad type BGA package according to another embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 배선기판 101 : 홀100: wiring board 101: hole
103 : 코팅된 플럭스 120 : 반도체 칩103: coated flux 120: semiconductor chip
121 : 본딩패드 130 : 전도성 와이어121: bonding pad 130: conductive wire
140 : 몰딩 150 : 솔더 볼140: molding 150: solder ball
300 : PCB 기판 301 : 볼 패드300: PCB substrate 301: ball pad
상기와 같은 목적을 달성하기 위한 본 발명은 BGA 패키지 제조방법은 내부에 배선이 형성된 배선기판과, 본딩패드가 형성된 반도체 칩을 구비한 센터 패드형 BGA 패키지에 있어서, 상기 배선기판을 선택적으로 식각하여 상기 본딩패드와 동일한 위치에 홀을 형성하는 단계와, 상기 배선기판 상면에 상기 반도체 칩을 접착하는 단계와, 상기 홀에 전도성 물질을 삽입하여 상기 반도체 칩에 형성된 본딩패드와 상기 배선기판내의 배선을 서로 전기적으로 연결시키는 단계와, 상기 반도체 칩을 보호하기 위해 몰딩 공정을 실시하는 단계와, 상기 배선기판 저면에 선택적으로 플럭스 코팅 공정을 실시하는 단계와, 상기 코팅된 플럭스에 솔더 볼을 부착시키는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a method for manufacturing a BGA package in a center pad type BGA package having a wiring board with a wiring formed therein, and a semiconductor chip formed with a bonding pad, by selectively etching the wiring board Forming a hole at the same position as the bonding pad, adhering the semiconductor chip to an upper surface of the wiring board, and inserting a conductive material into the hole to bond the bonding pad formed in the semiconductor chip with the wiring in the wiring board. Electrically connecting each other, performing a molding process to protect the semiconductor chip, selectively performing a flux coating process on the bottom surface of the wiring board, and attaching solder balls to the coated flux Characterized in that it comprises a.
또한, 상기 배선기판을 선택적으로 식각하여 홀 형성시 에지 패드 BGA 패키지인 경우, 상기 에지 패드와 동일한 위치에 홀을 형성하는 것이 바람직하다.In the case of forming the hole by selectively etching the wiring board, it is preferable to form the hole at the same position as the edge pad.
또한, 상기 홀의 크기는 15∼100㎛인 것이 바람직하다.In addition, the size of the hole is preferably 15 to 100㎛.
또한, 상기 전도성 물질은 전기적 도통을 위해 와이어 재질의 골드 및 전기적 도통이 가능한 물질인 것이 바람직하다.In addition, the conductive material is preferably a material capable of electrical conduction and gold of the wire material for electrical conduction.
또한, 상기 솔더 볼은 Sn을 기본으로 하고 선택적으로 Pb, Ag, Au, Zn, Cu, Sb을 추가하며, 그 지름은 150∼700㎛인 것이 바람직하다.In addition, the solder ball is based on Sn and optionally Pb, Ag, Au, Zn, Cu, Sb is added, the diameter is preferably 150 ~ 700㎛.
이하, 첨부된 도면을 참조하여 본 발명의 BGA 패키지 제조방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a BGA package manufacturing method of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 센터 패드형 BGA 패키지 제조방법을 나타낸 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method for manufacturing a center pad type BGA package according to an embodiment of the present invention.
도 2a에 도시한 바와 같이 도면에는 도시하지 않았지만 웨이퍼 상면에 집적회로를 형성하는 FAB 공정이 끝난 상태에서 웨이퍼에 형성된 반도체 칩을 개별적으로 분리하기 위한 소잉공정을 실시한다. 이때, 상기 반도체 칩에 형성된 본딩패드는 상기 반도체 칩의 중앙부에 위치한다.Although not shown in the drawing, as shown in FIG. 2A, a sawing process is performed to individually separate the semiconductor chips formed on the wafer after the FAB process of forming the integrated circuit on the upper surface of the wafer is completed. In this case, a bonding pad formed on the semiconductor chip is located at the center of the semiconductor chip.
그리고 내부에 배선이 형성된 배선기판(100)을 상기 반도체 칩에 형성된 본딩패드와 동일한 위치를 선택적으로 식각하여 홀(101)을 형성한다. 이때, 상기 홀(101)의 크기는 15∼100㎛이다.A hole 101 is formed by selectively etching the wiring substrate 100 having wiring formed therein at the same position as the bonding pad formed on the semiconductor chip. At this time, the size of the hole 101 is 15 ~ 100㎛.
도 2b에 도시한 바와 같이 상기 홀(101)을 갖는 배선기판(100) 상면에 접착제(102)를 도포하여 상기 분리된 반도체 칩(120)을 접착하고, 상기 홀(101)에 전도성 와이어(130)를 삽입하여 상기 반도체 칩(120)에 형성된 본딩패드(121)와 상기 배선기판(100)내의 배선을 서로 전기적으로 연결시킨다. 이때, 상기 전도성 와이어(130)는 전기적 도통을 위해 와이어 재질의 골드 및 전기적 도통이 가능한 물질이다.As shown in FIG. 2B, an adhesive 102 is applied to the upper surface of the wiring board 100 having the holes 101 to bond the separated semiconductor chip 120, and the conductive wires 130 are formed in the holes 101. ) To electrically connect the bonding pads 121 formed on the semiconductor chip 120 and the wirings in the wiring board 100 to each other. At this time, the conductive wire 130 is a gold material of the wire material and the electrically conductive material for the electrical conduction.
도 2c에 도시한 바와 같이 상기 반도체 칩(120)을 보호하기 위한 몰딩(140) 공정을 실시한 후, 스크린 프린팅을 통해 상기 배선기판(100) 저면에 형성된 볼 패드(301)상에 일정패턴의 솔더 페이스트를 전사하여 플럭스 코팅 공정을 실시한다.After the molding 140 process for protecting the semiconductor chip 120 is performed as shown in FIG. 2C, solder of a predetermined pattern is formed on the ball pad 301 formed on the bottom surface of the wiring substrate 100 through screen printing. The paste is transferred to carry out a flux coating process.
그리고 상기 배선기판(100) 저면에 일정패턴으로 코팅된 플럭스(103)에 솔더 볼(150)을 부착시킨 후, 납의 열접합 공정인 리플로우를 수행하여 솔더 볼(150)을 상기 배선기판(100)에 고정한다.Then, after attaching the solder ball 150 to the flux 103 coated on the bottom surface of the wiring board 100 in a predetermined pattern, the solder ball 150 is transferred to the wiring board 100 by performing reflow, which is a thermal bonding process of lead. ).
이어, 클리닝 및 마킹 공정을 실시하여 완제품인 BGA 패키지를 출하한다.Then, the cleaning and marking process is performed to ship the finished BGA package.
이어서, BGA 패키지를 PCB 기판(300)에 실장한다.Subsequently, the BGA package is mounted on the PCB substrate 300.
이때, 상기 솔더 볼(150)은 Sn을 기본으로 하고 선택적으로 Pb, Ag, Au, Zn, Cu, Sb 등을 추가하며, 그 지름은 150∼700㎛이고, 크기는 최소 100㎛에서 최대 1mm이다.At this time, the solder ball 150 is based on Sn and optionally Pb, Ag, Au, Zn, Cu, Sb, etc., the diameter is 150 ~ 700㎛, the size is at least 100㎛ at most 1mm. .
한편, 도 3은 본 발명의 다른 실시예에 따른 에지 패드형 BGA 패키지를 나타낸 단면도이다.3 is a cross-sectional view illustrating an edge pad type BGA package according to another embodiment of the present invention.
도 3에 도시한 바와 같이 에지 패드형 BGA 패키지는 반도체 칩(120)의 본딩패드(121)가 반도체 칩(120)의 에지부분에 형성되므로, 내부 배선을 갖는 배선기판(100)은 상기 본딩패드(121)와 동일한 위치에 홀(101)을 형성한다.As shown in FIG. 3, in the edge pad type BGA package, since the bonding pad 121 of the semiconductor chip 120 is formed at the edge portion of the semiconductor chip 120, the wiring board 100 having the internal wiring is connected to the bonding pad. The hole 101 is formed in the same position as 121.
이어, 소잉공정이 완료된 반도체 칩(120)을 접착제(102)를 이용하여 상기 배선기판(100)에 부착한 후, 상기 홀(101)에 전도성 와이어(130)를 삽입하여 상기 반도체 칩(100)의 본딩패드(121)와 상기 배선기판(100) 내부의 배선과 전기적으로 도통시킨다.Subsequently, after the sawing process is completed, the semiconductor chip 120 is attached to the wiring board 100 using an adhesive 102, and then the conductive wire 130 is inserted into the hole 101 to insert the semiconductor chip 100. Electrical connection with the bonding pads 121 and the wirings in the wiring board 100.
그리고 상기 반도체 칩(120)을 보호하기 위한 몰딩(140) 공정을 실시하고, 상기 배선기판(100)에 솔더 볼(150)을 부착시킨 후, 고정시킨다.In addition, a molding 140 process for protecting the semiconductor chip 120 is performed, and the solder ball 150 is attached to the wiring board 100 and then fixed.
이상에서 설명한 바와 같이 본 발명의 BGA 패키지 제조방법에 의하면, BGA 패키지 저면에 몰딩공정을 실시하지 않으므로 패키지 변경 또는 다른 디바이스를 개발할 때마다 신규로 제작할 필요가 없어 제작비용을 절감할 수 있는 효과가 있다.As described above, according to the BGA package manufacturing method of the present invention, since the molding process is not performed on the bottom of the BGA package, there is no need to newly produce each time a package change or other device is developed, thereby reducing the manufacturing cost. .
또한, 와이어를 홀에 삽입하여 본딩패드와 금속배선을 전기적으로 도통시키므로 전기 통로 길이가 줄어들어 디바이스의 특성을 향상시킬 수 있다.In addition, since the wire is inserted into the hole to electrically connect the bonding pad and the metal wiring, the length of the electric passage can be reduced, thereby improving the characteristics of the device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020006979A KR100818078B1 (en) | 2002-02-07 | 2002-02-07 | A method for manufacturing of ball grid array package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020006979A KR100818078B1 (en) | 2002-02-07 | 2002-02-07 | A method for manufacturing of ball grid array package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030067123A true KR20030067123A (en) | 2003-08-14 |
| KR100818078B1 KR100818078B1 (en) | 2008-03-31 |
Family
ID=32220846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020006979A KR100818078B1 (en) | 2002-02-07 | 2002-02-07 | A method for manufacturing of ball grid array package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100818078B1 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000002808A (en) * | 1998-06-23 | 2000-01-15 | 김영환 | Ball grid array package and manufacturing method thereof |
| KR20010008664A (en) * | 1999-07-02 | 2001-02-05 | 윤종용 | Wire bonding type chip scale package using beam lead and manufacturing method thereof |
| KR100608608B1 (en) * | 2000-06-23 | 2006-08-09 | 삼성전자주식회사 | Semiconductor chip package having bonding pad structure of mixing type and manufacturing method thereof |
-
2002
- 2002-02-07 KR KR1020020006979A patent/KR100818078B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100818078B1 (en) | 2008-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5367124A (en) | Compliant lead for surface mounting a chip package to a substrate | |
| US8072770B2 (en) | Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame | |
| US9130064B2 (en) | Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier | |
| KR0169820B1 (en) | Chip scale package with metal wiring substrate | |
| KR101119708B1 (en) | Land grid array packaged device and method of forming same | |
| KR100818078B1 (en) | A method for manufacturing of ball grid array package | |
| JP3397725B2 (en) | Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor device mounting tape | |
| KR200169583Y1 (en) | Ball grid array package | |
| KR100351920B1 (en) | semiconductor device and method for fabricating the same | |
| KR100230921B1 (en) | A structure of csp and manufacturing method thereof | |
| KR100818079B1 (en) | A method for manufacturing of ball grid array package | |
| KR100351926B1 (en) | Ball Grid Array package | |
| KR100369397B1 (en) | Ball grid array semiconductor package using flexible circuit board | |
| KR100444175B1 (en) | ball grid array of stack chip package | |
| KR100419950B1 (en) | manufacturing method of ball grid array semiconductor package using a flexible circuit board | |
| KR100308116B1 (en) | chip scale package and method for fabricating the same | |
| KR100230751B1 (en) | Semiconductor package manufacturing method | |
| KR100226106B1 (en) | Bga semiconductor package using lead frame and its manufacturing method | |
| KR100639210B1 (en) | ball grid array package | |
| KR20030025481A (en) | flip-chip semiconductor package and method of manufacturing thereof | |
| KR20010001774A (en) | chip scale package and method for fabricating the same | |
| KR20020049821A (en) | chip scale semiconductor package in wafer level and method for fabricating the same | |
| KR20020056283A (en) | Structure of stack type muli chip semiconductor package and manufacture method the same | |
| KR20040060535A (en) | Ball grid array semiconductor package | |
| KR19980073903A (en) | B.A.A package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110222 Year of fee payment: 4 |
|
| LAPS | Lapse due to unpaid annual fee |