KR20030049586A - Method of making metal wiring in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a metal wiring in a semiconductor device is provided to prevent line edge shrinkage and misalignment, to reduce RC delay and to prevent corrosion of a tungsten plug by decreasing the thickness of a lower metal wiring and photoresist. CONSTITUTION: The first low-permittivity oxide layer(12) is formed on a lower metal wiring(11). A via hole is formed by selectively etching the first oxide layer(12). After forming a glue layer/diffusion barrier layer(15) on the via hole, a tungsten plug(16) is filled into the via hole. The first metal pattern(17) of triple structure including a glue layer/diffusion barrier layer(17a), a conductive layer(17b) and a glue layer/diffusion barrier layer(17c), is formed on the tungsten plug(16). The second low-permittivity oxide layer(19) is formed between the first metal patterns(17). Then, the second metal pattern(20) of triple structure including a glue layer/diffusion barrier layer(20a), a conductive layer(20b) and a glue layer/diffusion barrier layer(20c), is formed on the first metal pattern.

Description

METHODS OF MAKING METAL WIRING IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In particular, the contact area between the lower metal wiring and the tungsten plug is reduced by depositing the metal wiring in two stages up and down and using the lower metal wiring and the photosensitive material in half. It can reduce the RC delay, prevent misalignment between the lower metal wiring and the tungsten plug and line end shortening of the lower metal wiring, and also prevent corrosion of the tungsten plug during the cleaning process. A metal wiring formation method of a semiconductor element.

1A to 1F are cross-sectional views of a manufacturing process for explaining a metal wiring forming method according to the prior art.

First, in the process illustrated in FIG. 1A, a low-k oxide 2 is coated on the lower metal wiring 1 by a spin coating method.

Here, when the rotary coating method is applied, the coating is applied differently according to the width or density of the metal wirings without applying the same thickness on the lower metal wirings because of the adhesion of the low dielectric constant oxide 2. In general, when the area of the metal wiring is large, it is applied thicker than when the area of the metal wiring is small, and the area where the density of the metal wiring is high is thicker than that of the low region.

Next, a chemical mechanical polishing (CMP) process is performed to planarize the upper portion of the oxide 2 and to planarize the thickness of the entire oxide (thickness of low dielectric constant oxide) present on the metal wiring.

Next, after the photoresist is applied, the via holes are patterned.

In the process shown in FIG. 1B, dry etching using plasma is performed to form via holes 4 in the oxide film 2. In other words, the via hole 4 is formed in the intermetal dielectric having a complex structure of the low dielectric constant oxide film 2 and the general oxide film.

In general, when making the via holes 4 by dry etching, a certain degree of excessive etching is performed to ensure that the via holes are completely penetrated regardless of the thickness variation of the interlayer dielectric layer in all portions of the wafer. Etch).

The process shown in FIG. 1C is characterized by plasma enhanced chemical vapor deposition (PECVD) of a glue layer / barrier layer 5 before the via hole 4 is filled with tungsten (W). E). In general, titanium (Ti) is used as the adhesive film, and titanium nitride (TiN) is used as the diffusion barrier.

Next, tungsten (W) 6 is filled in the via hole by plasma trigger chemical vapor deposition (PECVD).

At this time, when the tungsten (W) 6 is deposited sufficiently thick by chemical vapor deposition, the top of the tungsten (W) layer is flattened due to the characteristics of the deposition method.

The process shown in FIG. 1D is a step of removing tungsten (W) and titanium (Ti) / titanium nitride (TiN) present in a non-via hole region using a chemical mechanical polishing (CMP) process.

In this way, the tungsten 6 is filled only in the via hole. That is, a tungsten plug is formed.

The process shown in FIG. 1E is performed on the structure of FIG. 1D of titanium (Ti) / titanium nitride (TiN) 7a, aluminum (Al) (7b), titanium (Ti) / titanium nitride (TiN) (7c). The metal layer 7 is deposited in the structure.

Currently, in the silicon device manufacturing process, it is common to adopt a structure of titanium (Ti) / titanium nitride (TiN), aluminum (Al), titanium (Ti) / titanium nitride (TiN) as the metal layer 7. The titanium (Ti) layer under the aluminum (Al) layer 7b serves as a glue layer and the titanium nitride (TiN) layer serves as a diffusion barrier.

The aluminum (Al) layer 7b plays a role of a conduction layer that mainly transmits an electrical signal, and the upper titanium layer plays a role of an adhesive film as in the lower part. In addition, the titanium nitride (TiN) layer thereon serves as an anti-reflective coating (ARC) to reduce the reflection of light when the photosensitive material is patterned.

However, by design, although the patterned metal wire 7 completely covers the lower tungsten plug 6, in practice, the patterned metal wire 7 does not completely cover the lower tungsten plug 6. Happens frequently.

In other words, as the degree of integration of the metal wiring increases, the overlap margin between the metal wiring 7 and the tungsten plug 6 decreases. Thus, when the overlapping margin is insufficient, the patterning process for the photosensitive material occurs. Due to misalignment and line edge shrinkage, the metal wire 7 may not completely cover the lower tungsten plug 6.

The process shown in FIG. 1F is a step of performing dry etching using a plasma activated with Cl2 + BCl3 gas. In this case, the end of the metal wire 7 is partially reduced due to misalignment and line edge shrinkage occurring in the process of FIG. 1E.

Therefore, the contact area between the metal wiring 7 and the tungsten plug 6 becomes small, and as a result, the electrical contact between the metal wiring 7 and the tungsten plug 6 is not only weak, but also because high density plasma is used. These ions accumulate. As a result, the potential of tungsten (W) is increased so that tungsten corrosion occurs in the post-treatment cleaning process.

As such, the phenomenon in which tungsten is corroded by the accumulation of the tungsten (W) plug 6 does not occur in all the tungsten plugs 6, but is locally generated only in a pattern in which accumulating damage occurs easily. However, this occurrence causes a problem in that the yield is lowered because it greatly affects the device by bringing the Via Profile Open and the RC delay increase.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to deposit a metal wiring in two stages up and down and lower the thickness of the lower metal wiring and the photosensitive material by half, thereby using the lower metal wiring and the tungsten plug. The present invention provides a method of forming a metal wiring of a semiconductor device capable of preventing misalignment and line edge shrinkage.

In addition, another object of the present invention is to deposit the metal wiring in two stages up and down, and use the lower metal wiring and the photosensitive material in half the thickness, thereby widening the contact area between the lower metal wiring and the tungsten plug, thereby reducing the RC delay The present invention provides a method for forming a metal wiring of a semiconductor device that can be reduced.

In addition, another object of the present invention is to deposit the metal wiring in two stages up and down, and use the lower metal wiring and the photosensitive material in half the thickness, thereby widening the contact area between the lower metal wiring and the tungsten plug, resulting in RC delay The present invention provides a method for forming a metal wiring of a semiconductor device that can reduce charge accumulation in the tungsten plug and prevent corrosion of the tungsten plug during the post-treatment cleaning process.

1A to 1F are cross-sectional views of a manufacturing process for explaining a method for forming metal wirings of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views of a manufacturing process for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

11: lower metal wiring 12: oxide film or oxide

13, 21: photosensitive film 15: adhesive film / diffusion barrier film

16: tungsten or tungsten plug

17a, 17c: titanium / titanium nitride

17b: aluminum or aluminum layer 17: metal layer or first metal layer

19: oxide film or oxide

20a, 20c: titanium / titanium nitride

20b: aluminum or aluminum layer 20: metal layer or second metal layer

In order to achieve the above object, the semiconductor device manufacturing method according to the present invention,

Forming a first low dielectric constant oxide film on the lower metal wiring;

Forming a photoresist pattern after planarizing the first low dielectric constant oxide film by a chemical mechanical polishing (CMP) process;

Dry etching the first low dielectric constant oxide layer to form a via hole;

Forming an adhesive film / diffusion film on the structure to a predetermined thickness;

Depositing a thick tungsten (W) on the structure and filling the via hole to planarize the same;

Removing the tungsten (W) and the adhesive film / diffusion film in a region other than the via hole by a chemical mechanical polishing (CMP) process;

Forming a first metal layer having a triple structure of an adhesive film / antireflection film, a conductive layer, and an adhesive film / antireflection film on the structure;

Patterning the first metal layer by dry etching using plasma;

Forming a second low dielectric constant oxide film on the structure, and then planarizing it by a chemical mechanical polishing (CMP) process to partially etch the adhesive film / antireflection film of the first metal layer;

Forming a second metal layer having a triple structure of an adhesive film / antireflection film, a conductive layer, and an adhesive film / antireflection film on the structure;

And patterning the second metal layer by dry etching using a plasma.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2A to 2G are sectional views of the manufacturing process for explaining the metal wiring forming method according to the present invention.

First, in the process illustrated in FIG. 2A, a low-k oxide 12 is coated on the lower metal wiring 11 by a spin coating method.

In this case, when the rotary coating method is applied, due to the adhesion (Viscidity) of the low dielectric constant oxide (12) is not applied to the same thickness on each lower metal wiring, it is applied differently depending on the width or density of the metal wiring. In general, when the area of the metal wiring is large, it is applied thicker than when the area of the metal wiring is small, and the area where the density of the metal wiring is high is thicker than that of the low region.

Next, a chemical mechanical polishing (CMP) process is performed to planarize the top of the oxide 12 and to planarize the thickness of the entire oxide (thickness of the low dielectric constant oxide) present on the metal wiring.

Next, after the photoresist is applied, the via holes are patterned.

In the process illustrated in FIG. 2B, dry etching using plasma is performed to form via holes in the oxide layer 12. That is, via holes are formed in the intermetal dielectric 12 having a complex structure of a low dielectric constant oxide film and a general oxide film.

At this time, when the via hole is formed by dry etching, a certain degree of over etching is performed to ensure that the via hole is completely penetrated regardless of the thickness variation of the interlayer dielectric layer in all parts of the wafer. do.

Next, before filling the via hole with tungsten (W), the adhesive film / diffusion preventing film 15 is deposited by plasma trigger chemical vapor deposition (PECVD). In this case, titanium (Ti) is used as the adhesive film, and titanium nitride (TiN) is used as the diffusion barrier.

Next, tungsten (W) 16 is filled in the via hole by plasma trigger chemical vapor deposition (PECVD).

At this time, when the tungsten (W) 16 is sufficiently thick deposited using chemical vapor deposition, the top of the tungsten (W) layer is flattened due to the characteristics of the deposition method.

Next, tungsten (W) and titanium (Ti) / titanium nitride (TiN) present in a non-via hole region are removed using a chemical mechanical polishing (CMP) process.

In this way, the tungsten 16 is filled only in the via hole. That is, a tungsten plug is formed.

The process shown in FIG. 2C is based on the structure of FIG. 2B, including titanium (Ti) / titanium nitride (TiN) 17a, aluminum (Al) 17b, titanium (Ti) / titanium nitride (TiN) 17c. The metal layer 17 is deposited in the structure of.

At this time, the deposition process of the metal layer 17 is the same as the conventional silicon device manufacturing process, but the thickness of the aluminum layer 17b is formed by lowering to half (1/2). Therefore, the application of the photosensitive material to be formed later can be reduced by half.

The titanium (Ti) layer under the aluminum (Al) layer 7b serves as an adhesive film, and the titanium nitride (TiN) layer serves as a diffusion barrier.

The aluminum (Al) layer 7b plays a role of a conduction layer that mainly transmits an electrical signal, and a titanium layer of the upper part plays a role of an adhesive film like the lower part. In addition, the titanium nitride (TiN) layer thereon serves as an anti-reflection film (ARC) to reduce the reflection of light when the photosensitive material is patterned.

In the process illustrated in FIG. 2D, dry etching is performed by using a plasma activated with Cl 2 + BCl 3 gas. In this case, misalignment and line edge shrinkage occurring in the process of FIG. 2C are significantly reduced.

Therefore, the contact area between the metal wiring 17 and the tungsten plug 16 becomes wider, and as a result, the electrical contact between the metal wiring 17 and the tungsten plug 16 is not only improved, but also because high density plasma is used. Ions do not accumulate. Therefore, tungsten corrosion does not occur in the post-cleaning process, and a good via profile and a reduction in the RC delay are brought, thereby improving the yield in the semiconductor manufacturing process.

In the process shown in FIG. 2E, the oxide 19 is applied over the lower metal wiring 17 and the oxide film 12 in a spin coating or plasma enhanced manner.

As described above, when the rotary coating or the plasma triggering method is applied, the same oxide film is applied differently according to the width or density of the metal wirings without applying the same thickness on the lower part due to the adhesiveness of the oxide. In general, when the area of the metal wiring is large, it is applied thicker than when the area of the metal wiring is small, and the area where the density of the metal wiring is high is thicker than that of the low region.

Next, the chemical mechanical polishing (CMP) process was performed to planarize the upper portion of the oxide 19 and to planarize to a part of the titanium nitride (TiN) 17c, which is an antireflection film ARC on the metal wiring 17. Step.

The process illustrated in FIG. 2F is based on the structure of FIG. 2E, including titanium (Ti) / titanium nitride (TiN) 20a, aluminum (Al) 20b, titanium (Ti) / titanium nitride (TiN) 20c. The metal layer 20 is deposited in the structure of.

At this time, the deposition process of the metal layer 20 is the same as the conventional silicon device manufacturing process, but the thickness of the aluminum layer 20b is formed by lowering to half (1/2). Therefore, the application of the photosensitive material to be formed later can be reduced by half.

Similarly, the titanium (Ti) layer under the aluminum (Al) layer 20b serves as an adhesive film, and the titanium nitride (TiN) layer serves as a diffusion barrier.

The aluminum (Al) layer 20b plays a role of a conductive layer that mainly transmits an electrical signal, and a titanium layer of the upper part plays a role of an adhesive film as in the lower part. In addition, the titanium nitride (TiN) layer thereon serves as an anti-reflection film (ARC) to reduce the reflection of light when the photosensitive material is patterned.

The process shown in FIG. 2g is a step of performing dry etching using a plasma activated with Cl2 + BCl3 gas. At this time, since the formed metal wiring 20 is patterned on the lower metal wiring 17, it is irrespective of the tungsten plug 6. Therefore, tungsten corrosion does not occur in the post-treatment cleaning process, resulting in a good via profile and a reduction in RC delay, resulting in an improvement in yield in the semiconductor manufacturing process.

In addition, since the metal wiring is deposited in two stages, there is no change in resistance as in the conventional metal wiring.

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the metal wiring is deposited in two stages up and down, and the thickness of the lower metal wiring and the photosensitive material is lowered by half, thereby reducing the thickness of the lower metal wiring and the tungsten plug. This prevents warping and shrinking of the line edges of the lower metal lines. In addition, the bottom metallization completely covers the tungsten plug, thus widening the contact area and thereby reducing the RC delay.

In addition, there is no charge accumulation in the tungsten plug because the contact area between the lower metal wiring and the tungsten plug is large and the RC delay is small. Therefore, corrosion of tungsten due to charge accumulation in the post-treatment cleaning step can be prevented, and the yield of the device can be improved. In addition, the thickness of the lower metal interconnection is low, so that the application range of the bias power and the source power in the etching process may be extended.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (1)

Forming a first low dielectric constant oxide film on the lower metal wiring; Forming a photoresist pattern after planarizing the first low dielectric constant oxide film by a chemical mechanical polishing (CMP) process; Dry etching the first low dielectric constant oxide layer to form a via hole; Forming an adhesive film / diffusion film on the structure to a predetermined thickness; Depositing a thick tungsten (W) on the structure and filling the via hole to planarize the same; Removing the tungsten (W) and the adhesive film / diffusion film in a region other than the via hole by a chemical mechanical polishing (CMP) process; Forming a first metal layer having a triple structure of an adhesive film / antireflection film, a conductive layer, and an adhesive film / antireflection film on the structure; Patterning the first metal layer by dry etching using plasma; Forming a second low dielectric constant oxide film on the structure, and then planarizing it by a chemical mechanical polishing (CMP) process to partially etch the adhesive film / antireflection film of the first metal layer; Forming a second metal layer having a triple structure of an adhesive film / antireflection film, a conductive layer, and an adhesive film / antireflection film on the structure; And patterning the second metal layer by dry etching using a plasma.