CN112614810A - Method and device for flattening metal lamination - Google Patents

Method and device for flattening metal lamination Download PDF

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Publication number
CN112614810A
CN112614810A CN202011506746.1A CN202011506746A CN112614810A CN 112614810 A CN112614810 A CN 112614810A CN 202011506746 A CN202011506746 A CN 202011506746A CN 112614810 A CN112614810 A CN 112614810A
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CN
China
Prior art keywords
layer
metal
photoresist
photoresist layer
dielectric layer
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Pending
Application number
CN202011506746.1A
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Chinese (zh)
Inventor
李亦衡
王强
姚骏
吴敏
秦佳明
朱廷刚
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Corenergy Semiconductor Technology Co ltd
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Corenergy Semiconductor Technology Co ltd
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Priority to CN202011506746.1A priority Critical patent/CN112614810A/en
Publication of CN112614810A publication Critical patent/CN112614810A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a method for planarizing a metal stack, comprising depositing a dielectric layer on a metal underlayer, using a negative photoresist: forming a photoresist layer on the dielectric layer, forming a pattern on the photoresist layer by photoetching, etching off the dielectric layer at the part, enabling the opening angle theta of the photoresist layer to be larger than or equal to 90 degrees, depositing a metal layer, stripping the photoresist layer and the metal layer on the photoresist layer, and depositing a metal covering layer to enable the upper surface of the metal covering layer to be a plane. A device includes a structure formed by a method of planarizing a metal stack. The invention greatly improves the flatness of the metal layer, greatly simplifies the process flow and improves the performance of the device under the condition of not using CMP, tungsten plug (chemical mechanical polishing) and copper (double) embedding processes.

Description

Method and device for flattening metal lamination
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a method and device for planarizing a metal stack.
Background
In modern CMOS (complementary metal oxide semiconductor) device process flows, it is common practice to use a CMP (chemical mechanical polishing) process in various steps to achieve a planarized metallization stack within the via, together with a tungsten plug or a copper dual damascene (damascene) plug, as shown in fig. 1-1, 1-1a, 1-1 b.
Common methods of tungsten plug formation include: forming a through hole on the dielectric layer; depositing metal tungsten to cover all the through holes and the dielectric layer; and grinding the metal tungsten by adopting a CMP (chemical mechanical polishing) process until the metal tungsten in the through hole protrudes out of the surface of the dielectric layer.
Common methods for copper dual damascene plugs include: depositing a dielectric layer and etching by dry method to complete the pattern of the copper dual damascene structure, and depositing a diffusion barrier layer, generally TaN; performing metal deposition, such as PVD, CVD, or electroplating 6; and then CMP (chemical mechanical polishing) is performed.
In contrast, metallization design rules are relaxed for power MOSFET (metal-oxide semiconductor field effect transistor) devices. Thus, expensive CMP and/or tungsten/copper plug processes are not generally mandatory, and instead, aluminum-based metallization remains popular with device manufacturers. Aluminum is deposited by, for example, electron beam evaporation or sputtering, but its gap filling (hole filling) capability is poor, and even though the metal filling capability of aluminum can be improved to some extent by gradually narrowing the profile of the gap/hole at a slope of 45 ° or more, as shown in fig. 2-1, 2-2, some metal layer steps still exist due to the underlying topography.
Disclosure of Invention
It is an object of the present invention to provide a method for planarizing a metal stack that can greatly improve the planarity of the metal layer without using CMP, tungsten plug (chemical mechanical polishing), copper (dual) damascene processes.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method of planarizing a metal stack, comprising:
step 1:
a dielectric layer is deposited on the metal bottom layer,
step 2:
(1) using a negative photoresist: a photoresist layer is formed over the dielectric layer,
(2) forming a pattern on the photoresist layer by photolithography, etching away the dielectric in the portion, and making the opening angle theta of the photoresist layer equal to or larger than 90 deg.,
and step 3:
a metal layer is deposited and,
and 4, step 4:
stripping the photoresist layer and the metal layer on the photoresist layer,
and 5:
and depositing a metal covering layer to make the upper surface of the metal covering layer be a plane.
Preferably, the same metal is used to deposit the metal layer and the metal covering layer in step 3 and step 5.
Further preferably, the metal is aluminum.
Preferably, in step 2: the opening angle theta of the photoresist layer is more than 90 deg.
Preferably, in step 2: a double layer liftoff photoresist stack is used.
Preferably, in step 2: the metal layer is deposited by electron beam or sputtering.
Preferably, in step 3: the thickness of the metal layer deposited within the dielectric layer opening is close to the thickness of the dielectric layer.
Preferably, in step 4: and stripping the photoresist layer by using a Liftoff process.
Preferably, the dielectric layer is made of SiO2Or SiN.
It is another object of the invention to provide a device.
In order to achieve the purpose, the invention adopts the technical scheme that:
a device comprising a structure formed by the method of planarizing a metal stack.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
the invention greatly improves the flatness of the metal layer, greatly simplifies the process flow and improves the performance of the device under the condition of not using CMP, tungsten plug (chemical mechanical polishing) and copper (double) embedding processes.
Drawings
FIG. 1-1 is a diagram of a CMOS device metallization structure with CMP tungsten plugs;
FIGS. 1-1a, 1-1b are metallization structure diagrams of a CMOS device with CMP copper dual damascene plugs;
FIGS. 2-1, 2-2 are schematic illustrations of metal filled profiles with vertical or tapered gaps/holes;
fig. 3-1 to 3-5 are process flow diagrams of planarizing a metal stack in this embodiment.
In the above drawings:
1. a metal bottom layer; 2. a dielectric layer; 3. a metal layer; 30. a metal layer; 31. a metal cap layer; 4. and a photoresist layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A method of planarizing a metal stack, comprising:
step 1:
depositing a dielectric layer 2 on the metal bottom layer 1, the dielectric layer 2 being made of, for example, SiO2Or SiN as shown in fig. 3-1.
Step 2:
(1) using a negative photoresist: a photoresist layer 4 is formed on the dielectric layer 2, or a double layer liftoff photoresist stack is used,
(2) and forming a pattern on the photoresist layer 4 by a mark lithography technology, etching away the photoresist layer 4 and the dielectric medium at the part, forming an opening on the dielectric layer 2 and exposing the metal bottom layer 1, and enabling the opening angle theta of the photoresist layer 4 to be larger than or equal to 90 degrees, preferably, the opening angle theta of the photoresist layer 4 is larger than 90 degrees as shown in figure 3-2.
And step 3:
the metal layer 30 is deposited by electron beam or sputtering using aluminum metal, the metal layer 30 covers the photoresist layer 4, fills the opening of the dielectric layer 2, and the thickness of the metal layer 30 deposited in the opening of the dielectric layer 2 is close to the thickness of the dielectric layer 2, and the thickness of the metal layer 30 is slightly thicker than the thickness of the dielectric layer 2 and slightly protrudes from the dielectric layer as shown in fig. 3-3.
And 4, step 4:
the photoresist layer 4 and the metal layer 30 on the photoresist layer 4 are stripped, for example, by a Liftoff process, as shown in fig. 3-4.
And 5:
a metal cladding layer 31 is deposited by using metal aluminum by an electron beam or sputtering method, the metal cladding layer 31 covers the dielectric layer 2 and the metal layer 30, and the upper surface of the metal cladding layer 31 is a plane, thereby forming a metal laminated structure with a flat upper surface, as shown in fig. 3-5.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (10)

1. A method of planarizing a metal stack, comprising: the method comprises the following steps:
step 1:
a dielectric layer is deposited on the metal bottom layer,
step 2:
(1) using a negative photoresist: a photoresist layer is formed over the dielectric layer,
(2) forming a pattern on the photoresist layer by photolithography, etching away the dielectric in the portion, and making the opening angle theta of the photoresist layer equal to or larger than 90 deg.,
and step 3:
a metal layer is deposited and,
and 4, step 4:
stripping the photoresist layer and the metal layer on the photoresist layer,
and 5:
and depositing a metal covering layer to make the upper surface of the metal covering layer be a plane.
2. The method of claim 1, wherein: in step 3 and step 5, the same metal is used for depositing a metal layer and a metal covering layer.
3. The method of claim 2, wherein: the metal is aluminum.
4. The method of claim 1, wherein: in step 2: the opening angle theta of the photoresist layer is more than 90 deg.
5. The method of claim 1, wherein: in step 2: a double layer liftoff photoresist stack is used.
6. The method of claim 1, wherein: in step 2: the metal layer is deposited by electron beam or sputtering.
7. The method of claim 1, wherein: in step 3: the thickness of the metal layer deposited within the dielectric layer opening is close to the thickness of the dielectric layer.
8. The method of claim 1, wherein: in step 4: and stripping the photoresist layer by using a Liftoff process.
9. The method of claim 1, wherein: the dielectric layer is made of SiO2Or SiN.
10. A device, characterized by: comprising a structure formed by the method of any one of claims 1 to 9.
CN202011506746.1A 2020-12-18 2020-12-18 Method and device for flattening metal lamination Pending CN112614810A (en)

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CN202011506746.1A CN112614810A (en) 2020-12-18 2020-12-18 Method and device for flattening metal lamination

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030049586A (en) * 2001-12-15 2003-06-25 주식회사 하이닉스반도체 Method of making metal wiring in semiconductor device
CN101442029A (en) * 2008-12-18 2009-05-27 上海广电光电子有限公司 Method for manufacturing thin-film transistor array substrate
CN103456685A (en) * 2013-09-13 2013-12-18 华进半导体封装先导技术研发中心有限公司 Manufacturing method for TSV and first layer re-wiring layer needless of using CMP
WO2019219479A1 (en) * 2018-05-18 2019-11-21 Ams Ag Method for manufacturing an etch stop layer and mems sensor comprising an etch stop layer
US20200083436A1 (en) * 2018-09-11 2020-03-12 International Business Machines Corporation Contact via structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030049586A (en) * 2001-12-15 2003-06-25 주식회사 하이닉스반도체 Method of making metal wiring in semiconductor device
CN101442029A (en) * 2008-12-18 2009-05-27 上海广电光电子有限公司 Method for manufacturing thin-film transistor array substrate
CN103456685A (en) * 2013-09-13 2013-12-18 华进半导体封装先导技术研发中心有限公司 Manufacturing method for TSV and first layer re-wiring layer needless of using CMP
WO2019219479A1 (en) * 2018-05-18 2019-11-21 Ams Ag Method for manufacturing an etch stop layer and mems sensor comprising an etch stop layer
US20200083436A1 (en) * 2018-09-11 2020-03-12 International Business Machines Corporation Contact via structures

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