KR20030039286A - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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Publication number
KR20030039286A
KR20030039286A KR1020010070276A KR20010070276A KR20030039286A KR 20030039286 A KR20030039286 A KR 20030039286A KR 1020010070276 A KR1020010070276 A KR 1020010070276A KR 20010070276 A KR20010070276 A KR 20010070276A KR 20030039286 A KR20030039286 A KR 20030039286A
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South Korea
Prior art keywords
layer
oxide film
fluorine
semiconductor device
oxide layer
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KR1020010070276A
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Korean (ko)
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조경수
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아남반도체 주식회사
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Priority to KR1020010070276A priority Critical patent/KR20030039286A/en
Publication of KR20030039286A publication Critical patent/KR20030039286A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the delamination of a metal line due to the movement of fluorine elements by forming an oxide and nitride layer on the upper and lower surface of a fluorine containing oxide layer without directly connecting between the metal line and the fluorine containing oxide layer. CONSTITUTION: After sequentially forming a lower oxide layer(12) and a metal line layer, a metal line(13) is formed by patterning the metal line layer. The first silicon nitride layer(14) is formed on the entire surface of the resultant structure. Then, the first oxide layer(15) is formed on the first silicon nitride layer(14). After depositing an oxide layer(16) containing fluorine elements on the resultant structure at a predetermined thickness, the second oxide layer(17) and the second silicon nitride layer(18) are sequentially formed on the oxide layer(16). Then, an upper oxide layer(19) is formed on the second silicon nitride layer(18).

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device}Fabrication method of semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속 배선층 상부에 불소 함유 산화막을 사용하여 절연체층을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming an insulator layer by using a fluorine-containing oxide film on a metal wiring layer.

일반적으로 반도체 소자의 금속 배선층 상에는 절연체층이 적층되어 있으며, 내부가 도전성 물질로 충진된 컨택홀 또는 비아홀이 절연체층을 관통하여 금속 배선층과 연결되도록 형성되어 있다.In general, an insulator layer is stacked on a metal wiring layer of a semiconductor device, and a contact hole or a via hole filled with a conductive material therein is connected to the metal wiring layer through the insulator layer.

최근 금속 배선층 상에 형성하는 절연체층으로서 낮은 유전상수를 갖는 불소 함유 산화막을 선호하고 있다.Recently, a fluorine-containing oxide film having a low dielectric constant is preferred as an insulator layer formed on a metal wiring layer.

종래 방법에 따라 불소 함유 산화막을 금속 배선층 상부의 절연체층으로 사용하여 제조된 반도체 소자의 단면도가 도 1에 도시되어 있다.A cross-sectional view of a semiconductor device fabricated using a fluorine-containing oxide film as an insulator layer over a metal wiring layer according to a conventional method is shown in FIG.

도 1에 도시된 바와 같이, 반도체 기판(1) 상의 하부 산화막(2) 상에는 반도체 소자의 금속배선(3)이 형성되어 있고, 금속 배선을 포함하여 반도체 기판의 상부 전면에는 불소 함유 산화막(4)이 형성되어 있으며, 불소 함유 산화막 상에는 상부 산화막(5)이 형성되어 있다.As shown in FIG. 1, the metal wiring 3 of the semiconductor device is formed on the lower oxide film 2 on the semiconductor substrate 1, and the fluorine-containing oxide film 4 is formed on the entire upper surface of the semiconductor substrate including the metal wiring. Is formed, and the upper oxide film 5 is formed on the fluorine-containing oxide film.

이후에는 금속 배선의 상부에 위치하는 상부 산화막 및 불소 함유 산화막을 관통하도록 식각하여 콘택홀(미도시)을 형성하고, 콘택홀의 내부를 도전성 물질로 충진(미도시) 시킴으로써, 반도체 소자 제조를 완료한다.Thereafter, a contact hole (not shown) is formed by etching through the upper oxide film and the fluorine-containing oxide film located above the metal wiring, and the inside of the contact hole is filled with a conductive material (not shown) to complete the manufacturing of a semiconductor device. .

그러나, 상기한 바와 같은 종래 반도체 소자에서는, 불소가 상부 또는 하부로 이동하여 금속과 산화막 사이의 계면에 축적됨으로써 열공정 진행시 금속배선을 들뜨게 하는 현상인 디라미네이션(delamination)을 유발하는 문제점이 있었다.However, in the conventional semiconductor device as described above, fluorine moves to the upper or lower portion and accumulates at the interface between the metal and the oxide film, thereby causing delamination, which is a phenomenon of lifting the metal wiring during the thermal process. .

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속 배선이 들뜨는 현상인 디라미네이션을 방지하는 데 있다.The present invention has been made to solve the above problems, and an object thereof is to prevent delamination, which is a phenomenon in which metal wiring is lifted up.

도 1은 종래 방법에 따라 제조된 반도체 소자를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device manufactured according to a conventional method.

도 2는 본 발명에 따라 제조된 반도체 소자를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor device manufactured according to the present invention.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 금속 배선층 상에 불소 함유 산화막을 형성할 때, 불소 함유 산화막의 하부 및 상부에 산화막층 및 질화막층 중의 어느 한 층 이상을 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, when forming a fluorine-containing oxide film on the metal wiring layer, at least one of an oxide film layer and a nitride film layer is formed on the lower and upper portions of the fluorine-containing oxide film. .

이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail.

본 발명에서는 불소 함유 산화막으로부터 불소가 상부 또는 하부로 이동하여 금속과 산화막의 계면에 축적되는 것을 방지하기 위해, 불소 함유 산화막의 하부 및 상부에 산화막층 및 질화막층 중의 어느 한 층 이상을 형성하며, 이로써 불소의이동을 억제한다.In the present invention, in order to prevent fluorine from moving upward or downward from the fluorine-containing oxide film to accumulate at the interface between the metal and the oxide film, at least one of an oxide layer and a nitride layer is formed on the lower and upper portions of the fluorine-containing oxide film, This suppresses the movement of fluorine.

불소 함유 산화막의 하부 및 상부에는 산화막층 또는 질화막층만을 단독으로 형성할 수도 있고, 산화막층 및 질화막층을 이중층으로 형성할 수도 있다.Only the oxide film layer or the nitride film layer may be formed on the lower portion and the upper portion of the fluorine-containing oxide film alone, or the oxide film layer and the nitride film layer may be formed as a double layer.

이하, 실시예를 통해 본 발명을 더욱 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.

도 2는 본 발명에 따라 제조된 반도체 소자를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor device manufactured according to the present invention.

먼저, 실리콘 기판(11) 상의 하부 산화막(12) 상에 금속 배선층(13)을 형성한 후 패터닝한다.First, the metal wiring layer 13 is formed on the lower oxide film 12 on the silicon substrate 11 and then patterned.

다음, 금속 배선층(13)을 포함하여 기판(11)의 상부 전면에 제1실리콘질화막(14)을 형성하고, 제1실리콘질화막(14) 상에 제1산화막(15)을 형성한다.Next, the first silicon nitride film 14 is formed on the entire upper surface of the substrate 11 including the metal wiring layer 13, and the first oxide film 15 is formed on the first silicon nitride film 14.

다음, 불소 함유 산화막(16)을 적정두께 증착한 후, 불소 함유 산화막(16) 상에 제2산화막(17)을 형성하고, 제2산화막(17) 상에 제2실리콘질화막(18)을 형성한다.Next, after the fluorine-containing oxide film 16 is deposited to an appropriate thickness, a second oxide film 17 is formed on the fluorine-containing oxide film 16, and a second silicon nitride film 18 is formed on the second oxide film 17. do.

다음, 제2실리콘질화막(18) 상에 상부 산화막(19)을 두껍게 증착한다.Next, the upper oxide film 19 is thickly deposited on the second silicon nitride film 18.

이후에는, 기존의 일반적인 반도체 소자 제조방법에 따라 상부 산화막(19)을 화학기계적 연마한 후, 사진식각공정에 의해 금속 배선층의 상부에 비아홀을 형성하고 비아홀의 내부를 도전성 금속으로 충진시킨다.Thereafter, after the upper oxide film 19 is chemically mechanically polished according to a conventional method of manufacturing a semiconductor device, a via hole is formed on the metal wiring layer by a photolithography process, and the inside of the via hole is filled with a conductive metal.

상술한 바와 같이, 본 발명에서는 금속 배선층 상에 불소 함유 산화막을 형성할 때, 불소 함유 산화막의 하부 및 상부에 산화막층 및 질화막층 중의 어느 한층 이상을 형성하는데, 이로써, 불소의 이동을 억제하여 금속 배선의 들뜸현상인 디라미네이션을 방지하는 효과가 있다.As described above, in the present invention, when the fluorine-containing oxide film is formed on the metal wiring layer, at least one of an oxide film layer and a nitride film layer is formed on the lower and upper portions of the fluorine-containing oxide film. There is an effect of preventing the delamination which is a phenomenon of floating the wiring.

따라서, 디라미네이션에 기인한 소자의 불량발생률 감소를 방지하여 수율을 향상시키는 효과가 있다.Therefore, there is an effect of improving the yield by preventing the reduction of the defective rate of the device due to the delamination.

Claims (2)

금속 배선층 상에 불소 함유 산화막을 형성할 때, 상기 불소 함유 산화막의 하부 및 상부에 산화막층 및 질화막층 중의 어느 한 층 이상을 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.When forming a fluorine-containing oxide film on a metal wiring layer, the semiconductor device manufacturing method characterized by forming at least one layer of an oxide film layer and a nitride film layer below and on the said fluorine-containing oxide film. 제 1 항에 있어서,The method of claim 1, 상기 금속 배선층 상에 제1질화막 및 제1산화막을 형성한 다음, 상기 불소 함유 산화막을 형성하고;Forming a first nitride film and a first oxide film on the metal wiring layer, and then forming the fluorine-containing oxide film; 상기 불소 함유 산화막 상에 제2질화막 및 제2산화막을 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.A second nitride film and a second oxide film are formed on the fluorine-containing oxide film.
KR1020010070276A 2001-11-12 2001-11-12 Fabrication method of semiconductor device KR20030039286A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144793A (en) * 1996-11-08 1998-05-29 Internatl Business Mach Corp <Ibm> Method for enhancing resistance to metallic deterioration due to fluorine and integrated circuit device
KR19980035476A (en) * 1996-11-13 1998-08-05 김광호 Wiring Formation Method of Semiconductor Device
KR19980081721A (en) * 1997-04-25 1998-11-25 가네코히사시 Multi-layered wiring structure in semiconductor device and forming method thereof
KR19990023749A (en) * 1997-08-22 1999-03-25 가네꼬 히사시 Semiconductor device and manufacturing method
KR20020010852A (en) * 2000-07-31 2002-02-06 아끼구사 나오유끼 Semiconductor device and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144793A (en) * 1996-11-08 1998-05-29 Internatl Business Mach Corp <Ibm> Method for enhancing resistance to metallic deterioration due to fluorine and integrated circuit device
KR19980035476A (en) * 1996-11-13 1998-08-05 김광호 Wiring Formation Method of Semiconductor Device
KR19980081721A (en) * 1997-04-25 1998-11-25 가네코히사시 Multi-layered wiring structure in semiconductor device and forming method thereof
KR19990023749A (en) * 1997-08-22 1999-03-25 가네꼬 히사시 Semiconductor device and manufacturing method
KR20020010852A (en) * 2000-07-31 2002-02-06 아끼구사 나오유끼 Semiconductor device and method of manufacturing the same

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