KR100438160B1 - Device having inductor and capacitor and a fabrication method thereof - Google Patents

Device having inductor and capacitor and a fabrication method thereof Download PDF

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Publication number
KR100438160B1
KR100438160B1 KR10-2002-0011721A KR20020011721A KR100438160B1 KR 100438160 B1 KR100438160 B1 KR 100438160B1 KR 20020011721 A KR20020011721 A KR 20020011721A KR 100438160 B1 KR100438160 B1 KR 100438160B1
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inductor
support layer
capacitor
substrate
dielectric material
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KR10-2002-0011721A
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Korean (ko)
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KR20030072145A (en
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이문철
송인상
홍영택
정성혜
홍병유
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삼성전자주식회사
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Priority to KR10-2002-0011721A priority Critical patent/KR100438160B1/en
Priority to US10/373,735 priority patent/US7169684B2/en
Priority to EP03004397A priority patent/EP1343249A3/en
Priority to JP2003056947A priority patent/JP4034669B2/en
Publication of KR20030072145A publication Critical patent/KR20030072145A/en
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Publication of KR100438160B1 publication Critical patent/KR100438160B1/en
Priority to US11/655,915 priority patent/US7939909B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0078—Constructional details comprising spiral inductor on a substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/1006—Non-printed filter
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Abstract

LC 소자는 기판과, 기판상에 형성된 지지층과, 지지층에 상부 및 하부 중 어느 하나에 형성되는 인덕터 및 지지층의 다른 하나에 형성되는 캐패시터를 갖는다. 지지층은 저유전물질로 형성되며, 지지층에는 인덕터와 캐패시터를 연결하는 연결부가 마련된다. 따라서, 기판상의 저유전물질로 형성된 지지층의 상,하부에 인덕터와 캐패시터를 스택 구조의 형태로 배치함으로써, 기판상의 공간 활용을 최대한 활용할 수 있다. 또한, 인덕터와 캐패시터의 사이에 저유전물질의 지지층을 형성하여 지지함으로써 기판손실이 최소화되어 향상된 인덕터의 특성(Q값)에 의해 LC 소자의 특성을 향상시킬 수 있다.The LC element has a substrate, a support layer formed on the substrate, and an inductor formed in one of the upper and lower portions in the support layer, and a capacitor formed in the other of the support layer. The support layer is formed of a low dielectric material, and the support layer is provided with a connection portion connecting the inductor and the capacitor. Therefore, by placing the inductor and the capacitor in the form of a stack structure on the upper and lower portions of the support layer formed of the low dielectric material on the substrate, it is possible to maximize the utilization of space on the substrate. In addition, by forming and supporting a low dielectric material support layer between the inductor and the capacitor, the substrate loss is minimized, thereby improving the characteristics of the LC device by the improved inductor (Q value).

Description

인덕터와 캐패시터를 갖는 소자 및 그의 제작방법{Device having inductor and capacitor and a fabrication method thereof}Device having inductor and capacitor and a fabrication method

본 발명은 LC 소자 및 그의 제작방법에 관한 것으로서, 보다 상세하게는, 인턱터 소자의 특성을 향상시킬 수 있는 LC 소자 및 그의 제작방법에 관한 것이다.The present invention relates to an LC device and a method for manufacturing the same, and more particularly, to an LC device and a method for manufacturing the same that can improve the characteristics of the inductor device.

도 1a 및 도 1b는 일반적인 LC 소자 중 고역통과필터와 저역통과필터의 원리도를 나타낸 도이며, 이에 따른 고역통과필터와 저역통과필터의 단면도는 도 2 및 도 3에 도시된 바와 같다.1A and 1B are diagrams illustrating a principle diagram of a high pass filter and a low pass filter of a typical LC device, and sectional views of the high pass filter and the low pass filter are shown in FIGS. 2 and 3.

일반적인 고역/저역통과필터는 도 2 및 도 3에 도시된 바와 같이, 먼저, 기판(10)(20)상에 인덕터(L) 및 캐패시터(C)를 형성한다. 예를 들어, 먼저, 인덕터(11)(21)를 형성할 경우에는, 기판(10)(20)상에 금속물질을 증착하고 패턴하여 인덕터(L)를 형성한다. 형성된 인덕터(L)를 보호하기 위해 인턱터(L) 상부에 보호막(미도시)을 형성한 다음, 도시된 바와 같이, 캐패시터(C)를 형성한다. 캐패시터(C)의 제작공정은 기판(10)(20)상에 바닥전극층(12)(22)을 형성하고, 그 위에 고유전물질의 캐패시터물질(13)(23)을 형성한 후, 상극전극층(14)(24)을 순차적으로 형성하여 제작한다.A typical high / low pass filter, as shown in FIGS. 2 and 3, first forms an inductor L and a capacitor C on the substrate 10, 20. For example, first, when the inductors 11 and 21 are formed, a metal material is deposited and patterned on the substrates 10 and 20 to form the inductor L. A protective film (not shown) is formed on the inductor L to protect the formed inductor L, and then, as illustrated, a capacitor C is formed. In the manufacturing process of the capacitor C, the bottom electrode layers 12 and 22 are formed on the substrates 10 and 20, the capacitor materials 13 and 23 of the high dielectric material are formed thereon, and then the upper electrode layer is formed. (14) (24) is formed sequentially and produced.

이와 같이, 종래의 필터 구조는 기판(10)(20)상에 형성된 인덕터(L)의 면적이 상대적으로 캐패시터(C)의 면적 보다 크기 때문에 전체적인 LC 소자의 크기가 커진다.As described above, in the conventional filter structure, since the area of the inductor L formed on the substrates 10 and 20 is relatively larger than that of the capacitor C, the overall size of the LC element is increased.

또한, LC 소자의 동작 특성을 향상시키기 위해 공기 중에 소자를 구현하는 방법면에서 기판상의 한 층에 여러 소자를 구현함에 따른 공정상의 어려운 점이 있었다.In addition, in order to improve the operating characteristics of the LC device in the air in terms of how to implement the device there is a difficult process in accordance with the implementation of several devices in one layer on the substrate.

상기와 같은 문제점을 해결하기 위해 본 발명의 목적은, 제작상에서 공간효율을 최대로 하며, 또한, 성능을 향상시킬 수 있는 LC 소자 및 그의 제작방법을 제공하는 것이다.SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide an LC device and a method of manufacturing the same, which can maximize space efficiency in manufacturing and improve performance.

도 1a 및 도 1b는 일반적인 고역/저역통과필터의 원리도,1a and 1b is a principle diagram of a typical high pass filter, low pass filter,

도 2는 종래의 LC 소자인 고역통과필터의 단면도,2 is a cross-sectional view of a high pass filter which is a conventional LC element;

도 3은 종래의 LC 소자인 저역통과필터이 단면도,3 is a cross-sectional view of a low pass filter, which is a conventional LC element;

도 4a 및 도 4b는 본 발명에 따른 고역통과필터의 단면도,4A and 4B are cross-sectional views of the high pass filter according to the present invention;

도 5a 및 도 5b는 본 발명에 따른 저역통과필터의 단면도,5A and 5B are cross-sectional views of the low pass filter according to the present invention;

도 6a 내지 도 6i는 본 발명에 따른 일 실시예로 도 4a의 고역통과필터를 제작하는 공정을 순차적으로 도시한 도, 그리고6a to 6i sequentially illustrate the process of manufacturing the high pass filter of FIG. 4a as an embodiment according to the present invention; and

도 7a 내지 도 7i는 본 발명의 따른 다른 실시예로 도 4b의 고역통과필터를 제작하는 공정을 순차적으로 도시한 도이다.7A to 7I are diagrams sequentially illustrating a process of manufacturing the high pass filter of FIG. 4B according to another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 기판 110 : 인덕터(L)100: substrate 110: inductor (L)

120 : 지지층(저유전물질) 130 : 캐패시터(C)120: support layer (low dielectric material) 130: capacitor (C)

상기 목적을 달성하기 위한 본 발명에 따른 LC 소자는, 기판; 상기 기판상에 형성된 지지층; 상기 지지층의 상부 및 하부 중 어느 하나에 형성되는 인덕터; 및 상기 지지층의 상부 및 하부 중 다른 하나에 형성되는 캐패시터;를 포함하는 것을 특징으로 한다.An LC device according to the present invention for achieving the above object, the substrate; A support layer formed on the substrate; An inductor formed on any one of upper and lower portions of the support layer; And a capacitor formed on the other of the upper and lower portions of the support layer.

즉, 상기 지지층의 상부 및 하부에 형성되는 상기 인덕터 및 상기 캐패시터는 상호간에 스택 구조로 형성된다.That is, the inductor and the capacitor formed on the upper and lower portions of the support layer are formed in a stack structure with each other.

바람직하게는, 상기 지지층은 저유전물질로 형성되며, 그 하부에 형성되는 상기 인덕터 및 상기 캐패시터가 공기 중에 노출되도록 상기 기판에 의해 지지되도록 한다.Preferably, the support layer is formed of a low dielectric material and is supported by the substrate so that the inductor and the capacitor formed below the substrate are exposed to air.

또한, 상기 지지층을 관통하여 형성되며, 상기 지지층의 상부 및 하부에 형성되는 상기 인덕터 및 상기 캐패시터를 전기적으로 연결시키는 연결부가 마련된다.In addition, a connection part formed through the support layer and electrically connecting the inductor and the capacitor formed on the upper and lower portions of the support layer is provided.

한편, 본 발명에 따른 LC 소자의 제작방법은, 기판에 인덕터 및 캐패시터 중 어느 하나를 형성하는 단계; 상기 인덕터 및 상기 캐패시터 중 어느 하나가 형성된 상기 기판상에 지지층을 형성하는 단계; 및 상기 지지층 상부에 상기 인덕터 및 상기 캐패시터 중 다른 하나를 형성하는 단계;를 포함한다.On the other hand, the manufacturing method of the LC device according to the invention, forming one of the inductor and the capacitor on the substrate; Forming a support layer on the substrate on which one of the inductor and the capacitor is formed; And forming another one of the inductor and the capacitor on the support layer.

또한, 상기 지지층을 관통하여 연결부를 형성한다.In addition, the connection part is formed through the support layer.

바람직하게는, 상기 지지층은 저유전물질인 것을 특징으로 하며, 그의 하부의 기판인 상기 인덕터 및 상기 캐패시터가 형성된 상기 기판의 영역을 식각한다.Preferably, the support layer is a low dielectric material, and the region of the substrate on which the inductor and the capacitor, which are the lower substrate thereof, is etched.

따라서, 기판상의 저유전물질로 형성된 지지층의 상, 하부로 인덕터(L)와 캐패시터(C)를 배치하여 스택 구조의 LC소자를 제작함으로써, 기판상의 공간 활용을 최대화 할 수 있다.Therefore, by arranging the inductor (L) and the capacitor (C) on the upper and lower portions of the support layer formed of a low dielectric material on the substrate to manufacture a stack structure LC device, it is possible to maximize the utilization of space on the substrate.

또한, 인덕터와 캐패시터의 사이에 저유전물질의 지지층을 형성하여 지지함으로써 기판손실이 최소화하여 향상된 인덕터의 특성(Q값)에 의해 LC 소자의 특성을 향상시킬 수 있다.In addition, by forming and supporting a low dielectric material support layer between the inductor and the capacitor, the substrate loss can be minimized and the characteristics of the LC device can be improved by the improved inductor (Q value).

이하에서는 도면을 참조하여 본 발명에 의한 LC 소자의 실시예로서 고역통과필터에 대해 설명한다.Hereinafter, a high pass filter will be described as an embodiment of an LC device according to the present invention with reference to the drawings.

예컨데, 도 4a 및 도 4b에 도시된 바와 같이, 고역통과필터는 기판(100)과, 기판(100) 상에 형성된 지지층(120)과, 지지층(120)의 상부 및 하부 중 어느 하나에 형성되는 인덕터(L) 및 지지층(120)의 다른 하나에 형성되는 캐패시터(C)를 가지고 있다. 또한, 인덕터(L)와 캐패시터(C)를 전기적으로 연결하기 위해 연결부(121)가 지지층(120)에 마련된다.For example, as shown in FIGS. 4A and 4B, the high pass filter is formed on one of the substrate 100, the support layer 120 formed on the substrate 100, and the upper and lower portions of the support layer 120. It has a capacitor C formed on the other of the inductor L and the support layer 120. In addition, the connection part 121 is provided in the support layer 120 to electrically connect the inductor L and the capacitor C.

기판(100)은 반도체나 유전체인 실리콘(Si)로 제조된다.The substrate 100 is made of silicon (Si), which is a semiconductor or dielectric.

지지층(120)은 저유전(low-k)물질로 제조된다. 예컨데, 저유전물질로는 BCB(bicyclobutene), Polymer 계열의 물질 등이다.The support layer 120 is made of a low-k material. For example, low dielectric materials include BCB (bicyclobutene) and polymer-based materials.

즉, 저유전물질(120)을 기판(100) 위에 도포함으로써 기판(100)을 이루는 물질인 실리콘(Si)에 의해 인덕터(L)의 특성이 기판(100) 및 캐패시터(C)에 의해 저하되는 것을 막을 수 있다.That is, by applying the low dielectric material 120 on the substrate 100, the characteristics of the inductor L are degraded by the substrate 100 and the capacitor C by silicon (Si), which is a material forming the substrate 100. Can be prevented.

인덕터(L)와 캐패시터(C)는 금속물질, 예컨데, 구리(Cu) 등과 같은 물질로 제조되며, 지지층(120)의 상, 하부에 배치함으로써 인덕터(L)와 캐패시터(C)는 스택 구조로 배치된다. 이때, 지지층(120)의 하부의 기판(100)은 식각되어 지지층의 상,하부에 형성된 인덕터(110) 및 캐패시터(130)는 각각 공기 중에 배치된다.The inductor L and the capacitor C are made of a metal material, for example, copper (Cu), and the like. The inductor L and the capacitor C are arranged in a stack structure by being disposed above and below the support layer 120. Is placed. In this case, the substrate 100 under the support layer 120 is etched, and the inductor 110 and the capacitor 130 formed on the upper and lower portions of the support layer are disposed in air.

이상에서는 본 발명에 따른 LC 소자 중 고역통과필터의 구조를 예로서 설명하였으나, 도 5a, 5b에 도시된 바와 같이, 저역통과필터에서도 디자인은 다양하게 구성될 수 있으며, 또한, 그 외의 다른 LC 소자에 적용하여 다양하게 인덕터와 캐패시터를 디자인할 수 있음은 물론이다.Although the structure of the high pass filter among the LC elements according to the present invention has been described as an example, as shown in FIGS. 5A and 5B, the design of the low pass filter may be variously configured, and other LC elements may be used. Of course, the inductor and capacitor can be designed in various ways.

이하에서는 도 6a 내지 도 6i를 참조하여 본 발명에 따른 LC 소자의 일 실시예인 고역통과필터(도 4a)에 대한 제작공정을 상세하게 설명한다.Hereinafter, a manufacturing process of the high pass filter (FIG. 4A), which is an embodiment of the LC device according to the present invention, will be described in detail with reference to FIGS. 6A to 6I.

먼저, 도 6a에 도시된 바와 같이, 인덕터(110)를 형성하기 위해 인덕터(110)가 형성되는 영역의 기판(100)을 식각한다.First, as shown in FIG. 6A, the substrate 100 in the region where the inductor 110 is formed is etched to form the inductor 110.

도 6b에 도시된 바와 같이, 후술되는 지지층(120) 하부의 기판(100)을 식각하기 위해 마스크로 사용되는 산화막(oxide:101)를 증착한다. 다음, 인덕터(110)를 형성하기 위해 씨앗 금속층(seed layer:111)을 형성하고, 도금공정을 위해 패턴된 포토레지스트층(102)를 기판(100)상에 형성한다. 그 후, 금속물질(Cu)을 인덕터 형성을 위해 식각된 기판(100)에 채워 넣음으로써 인덕터(110)를 형성한다.As shown in FIG. 6B, an oxide film 101 used as a mask is etched to etch the substrate 100 under the support layer 120 to be described later. Next, a seed metal layer 111 is formed to form the inductor 110, and a patterned photoresist layer 102 is formed on the substrate 100 for the plating process. Thereafter, the inductor 110 is formed by filling the metal material Cu into the etched substrate 100 to form the inductor.

인턱터(110) 제작공정이 완료되면, 도 6c에 도시된 바와 같이, 포토레지스트층(102)을 제거하고 인덕터(110)가 형성된 기판(100)상에 저유전물질의 지지층(120)을 형성한다. 또한, 후술되는 캐패시터(130)와 전기적으로 연결하기 위한 연결홀(121)을 패턴한다. 예컨데, 저유전물질로는 BCB(bicyclobutene), Polymer 계열의 물질 등이 사용된다When the manufacturing process of the inductor 110 is completed, as shown in FIG. 6C, the photoresist layer 102 is removed and the support layer 120 of the low dielectric material is formed on the substrate 100 on which the inductor 110 is formed. . In addition, a connection hole 121 for electrically connecting the capacitor 130 to be described later is patterned. For example, BCB (bicyclobutene), a polymer-based material is used as the low dielectric material

이어, 도금공정에 의해 도 6d에 도시된 바와 같이 연결홀(121)에 금속물질을 채워 넣음으로써 연결부(121)를 형성한다.Subsequently, the connection part 121 is formed by filling a metal material into the connection hole 121 as shown in FIG. 6D by the plating process.

기판(100)에 형성된 인덕터(110)의 위치에 스택 구조로 캐패시터(130)가 배치되도록 하기 위해 도 6e에 도시된 바와 같이, 지지층(120) 하부에 형성된 인덕터(110)의 위치에 대응되는 지지층(120) 상부에 캐패시터(130)의 바닥전극층(131)을 형성한다. 이때, 바닥전극층(131)은 인덕터(110)와 연결되도록 금속물질(Pt)을 증착하여 패턴화함으로써 연결부(121)와 접촉시킨다.In order to arrange the capacitor 130 in a stack structure at a position of the inductor 110 formed on the substrate 100, as shown in FIG. 6E, a support layer corresponding to the position of the inductor 110 formed below the support layer 120 is formed. The bottom electrode layer 131 of the capacitor 130 is formed on the upper portion 120. In this case, the bottom electrode layer 131 contacts the connection part 121 by depositing and patterning a metal material Pt to be connected to the inductor 110.

그 후, 고유전물질, 예컨데, SiO2, SiN4, STO 등의 캐패시터물질(132)을 도 6f에 도시된 바와 같이, 바닥전극층(131) 위에 증착하여 패턴한 후, 그 위에 상극전극층(133)이 형성되도록 금속물질(Cu)을 증착하여 패턴한다.Thereafter, a capacitor material 132 such as SiO 2 , SiN 4 , STO, and the like is deposited on the bottom electrode layer 131 and patterned, as shown in FIG. 6F, and then the upper electrode layer 133 is formed thereon. The metal material (Cu) is deposited and patterned to form a).

인덕터(110)와 캐패시터(130)는 스택 구조로 배치되며, 저유전물질의 지지층(120)에 의해 지지된다.The inductor 110 and the capacitor 130 are arranged in a stack structure and are supported by the support layer 120 of the low dielectric material.

다음, 인덕터(110)가 형성된 지지층(120) 하부의 기판(100)을 식각하기 위해 도 6g에 도시된 바와 같이, 기판(100)의 상부 및 하부에 각각 보호막(140)을 형성하고, 식각되는 기판(100)의 영역에 대응하여 보호막(140)을 패턴한다.Next, in order to etch the substrate 100 under the support layer 120 on which the inductor 110 is formed, as shown in FIG. 6G, the protective layer 140 is formed on the upper and lower portions of the substrate 100, respectively, and then etched. The passivation layer 140 is patterned corresponding to the region of the substrate 100.

인덕터(110)가 형성된 지지층(120) 하부의 기판(100)을 도 6h에 도시된 바와 같이 식각하고, 기판(100)의 상부 및 하부에 형성된 보호막(140)을 제거함으로써, 도 6i에 도시된 바와 같은 고역통과필터를 제작한다.The substrate 100 under the support layer 120 on which the inductor 110 is formed is etched as shown in FIG. 6H, and the protective layers 140 formed on the upper and lower portions of the substrate 100 are removed to thereby remove the protective layer 140 shown in FIG. 6I. A high pass filter as described above is fabricated.

따라서, 인덕터(110)와 캐패시터(130)가 저유전물질의 지지층(120)에 대해 스택 구조로 배치되어 LC 소자의 공간활용을 최대화 할 수 있다. 또한, 기판 식각을 통해 인덕터(110)가 저유전물질에 지지되어 공기 중에 배치됨으로써 인덕터의 특성(Q값)이 향상된다.Therefore, the inductor 110 and the capacitor 130 are arranged in a stack structure with respect to the support layer 120 of the low dielectric material, thereby maximizing the space utilization of the LC device. In addition, the inductor 110 is supported by the low dielectric material through the substrate etching and disposed in the air, thereby improving the characteristic (Q value) of the inductor.

한편, 도 7a 내지 도 7i를 참조하여 본 발명에 따른 LC 소자인 고역통과필터(도 4b)의 다른 실시예에 대한 제작공정을 상세하게 설명하며, 앞에서 설명된 동일한 구성요소에 대한 도면번호는 동일하게 부여한다.On the other hand, with reference to Figure 7a to 7i will be described in detail the manufacturing process for another embodiment of the high pass filter (Fig. 4b) of the LC element according to the present invention, the same reference numerals for the same components described above To give.

먼저, 도 7a에 도시된 바와 같이, 캐패시터(130)를 형성하기 위해 캐패시터(130)가 형성되는 영역의 기판(100)을 식각한다. 도 7b에 도시된 바와 같이, 후술되는 기판(100)의 식각을 위해 마스크로 사용될 산화막(101)를 증착하며, 캐패시터(130)의 바닥전극층(131)을 형성하기 위해 금속물질(Pt)을 증착하여 패턴한다.First, as shown in FIG. 7A, the substrate 100 in the region where the capacitor 130 is formed is etched to form the capacitor 130. As shown in FIG. 7B, an oxide film 101 to be used as a mask is deposited for etching the substrate 100 to be described later, and a metal material Pt is deposited to form the bottom electrode layer 131 of the capacitor 130. Pattern.

이어, 고유전물질의 캐패시터물질(132)을 도 7c에 도시된 바와 같이, 바닥전극층(131) 위에 증착하여 패턴한 후, 그 위에 상극전극층(133)이 형성되도록 금속물질(Cu)을 증착하여 패턴한다.Subsequently, as shown in FIG. 7C, the capacitor material 132 of the high dielectric material is deposited on the bottom electrode layer 131 to be patterned, and then a metal material Cu is deposited to form the upper electrode layer 133 thereon. Pattern.

그 후, 도 7d에 도시된 바와 같이, 저유전물질(120)을 캐패시터(130)가 형성된 기판(100) 위에 코팅하여 후술되는 인덕터(110)가 지지되는 지지층을 형성하고,캐패시터(130)와 인덕터(110)를 전기적으로 연결하기 위한 연결홀(121)을 패턴한다.Subsequently, as shown in FIG. 7D, the low dielectric material 120 is coated on the substrate 100 on which the capacitor 130 is formed to form a support layer on which the inductor 110 described later is supported, and the capacitor 130 The connection hole 121 for electrically connecting the inductor 110 is patterned.

인덕터(110)를 형성하기 위해 도 7e에 도시된 바와 같이, 저유전물질(120) 위에 씨앗 금속층(seed layer:111)을 형성하기 위해 금속물질(Cu)을 증착한 후, 인덕터(110)가 형성될 영역이 패턴된 몰드(160)를 형성한다. 도금공정에 의해 패턴된 부분과 연결홀(121)에 금속물질을 채워 넣어 인덕터(110)와 연결부(221)를 형성한다.As shown in FIG. 7E to form the inductor 110, after depositing the metal material Cu to form a seed layer 111 on the low dielectric material 120, the inductor 110 is formed. The region to be formed forms a patterned mold 160. The inductor 110 and the connecting portion 221 are formed by filling a metal material into the patterned portion and the connecting hole 121 by the plating process.

다음, 도 7f에 도시된 바와 같이, 몰드(160)를 제거한 후, 씨앗 금속층(111)을 패턴한다.Next, as shown in FIG. 7F, after the mold 160 is removed, the seed metal layer 111 is patterned.

도 7g에 도시된 바와 같이, 기판(100)의 상부 및 하부에 각각 보호막(140)을 형성하고, 기판(100)에 캐패시터(130)가 형성된 부분의 보호막(140)을 패턴하여 산화막(101)을 식각한다. 그 후, 도 7h에 도시된 바와 같이 캐패시터(130)가 형성된 부분의 기판(100)을 식각한다.As shown in FIG. 7G, the protective layer 140 is formed on the upper and lower portions of the substrate 100, and the oxide layer 101 is patterned by patterning the protective layer 140 at the portion where the capacitor 130 is formed on the substrate 100. Etch Thereafter, as shown in FIG. 7H, the substrate 100 of the portion where the capacitor 130 is formed is etched.

기판(100)의 상부 및 하부에 형성된 보호막(140)을 제거하면, 도 7i에 도시된 바와 같이, 다른 실시예의 고역통과필터가 제작된다.If the protective film 140 formed on the upper and lower portions of the substrate 100 is removed, as shown in FIG. 7I, a high pass filter according to another embodiment is manufactured.

도 5a 및 도 5b에 도시된 바와 같이, 본 발명에 따른 저역통과필터 역시 앞에서 설명한 고역통과필터에 대해 인덕터(L)와 캐패시터(C)의 수와 디자인이 다를뿐 그 구조는 동일하다.As shown in FIGS. 5A and 5B, the low pass filter according to the present invention also has the same structure and the number and design of the inductor L and the capacitor C for the high pass filter described above.

이상의 실시예와 같이, 기판상의 저유전물질로 형성된 지지층의 상,하부에 인덕터(L)와 캐패시터(C)를 스택 구조로 배치함으로써, 기판상의 공간 활용을 최대한 활용할 수 있다.As described above, the inductor L and the capacitor C are disposed in the stack structure on the upper and lower portions of the support layer formed of the low dielectric material on the substrate, thereby making the most of the space utilization on the substrate.

또한, 기존의 유전체 기판에 의해 인덕터(L)와 캐패시터(C)가 지지됨에 따른 기판손실의 문제점을 저유전물질의 지지층에 의해 지지시킴으로써 기판손실을 최소화하여 인덕터 특성(Q값)을 향상시킬 수 있다.In addition, the problem of substrate loss caused by the support of the inductor (L) and the capacitor (C) by the existing dielectric substrate is supported by the low dielectric material support layer, thereby minimizing the substrate loss and improving the inductor characteristics (Q value). have.

본 발명에 따르면, 종래의 기판상에 한층으로 소자를 배치하는 구조에 비해 기판상의 저유전물질로 형성된 지지층에 의해 스택구조로 인덕터와 캐패시터를 배치함으로써 공간활용을 최대화 할 수 있다.According to the present invention, space utilization can be maximized by arranging inductors and capacitors in a stacked structure by a support layer formed of a low dielectric material on a substrate, compared to a structure in which devices are disposed on a single substrate on a conventional substrate.

또한, 종래의 인덕터 특성에 악영향을 주었던 기판과의 기생효과를 최소화하기 위해 저유전물질로 인덕터를 지지시키며 또한, 해당되는 기판을 식각하여 인덕터를 공기 중에 배치시킴으로써 인덕터 특성(Q값)을 향상시킬 수 있다.In addition, in order to minimize the parasitic effect with the substrate which adversely affected the conventional inductor characteristics, the inductor is supported by a low dielectric material, and the inductor characteristics (Q value) can be improved by etching the corresponding substrate and placing the inductor in the air. Can be.

이상에서는 본 발명의 바람직한 실시예에 대해서 도시하고 설명하였으나, 본 발명은 상술한 특정의 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형 실시가 가능한 것은 물론이고, 그와 같은 변경은 청구범위 기재의 범위 내에 있게 된다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention is not limited to the specific embodiments of the present invention without departing from the spirit of the present invention as claimed in the claims. Anyone skilled in the art can make various modifications, as well as such modifications are within the scope of the claims.

Claims (10)

기판;Board; 저유전물질이며, 상기 기판상에 형성되는 지지층;A support layer formed of a low dielectric material on the substrate; 상기 지지층의 상부 및 하부 중 어느 하나에 형성되는 인덕터; 및An inductor formed on any one of upper and lower portions of the support layer; And 상기 지지층의 상기 상부 및 상기 하부 중 다른 하나에 형성되는 캐패시터;를 포함하며,And a capacitor formed on the other of the upper and lower portions of the support layer. 상기 지지층은, 그 하부에 형성되는 상기 인덕터 및 상기 캐패시터가 공기 중에 노출되도록 상기 기판에 의해 지지되는 것을 특징으로 하는 LC 소자.And the support layer is supported by the substrate such that the inductor and the capacitor formed underneath are exposed to air. 제 1항에 있어서,The method of claim 1, 상기 저유전물질은 BCB(bicyclobutene)물질 및 Polymer물질 중 어느 하나인 것을 특징으로 하는 LC 소자.The low dielectric material is an LC device, characterized in that any one of a BCB (bicyclobutene) material and a polymer material. 제 1항에 있어서,The method of claim 1, 상기 지지층을 관통하여 형성되며, 상기 지지층의 상부 및 하부에 형성되는 상기 인덕터 및 상기 캐패시터를 전기적으로 연결시키는 연결부;를 더 포함하는 것을 특징으로 하는 LC 소자.And a connection part formed through the support layer and electrically connecting the inductor and the capacitor formed on and under the support layer. 제 1항에 있어서,The method of claim 1, 상기 지지층의 상부 및 하부에 형성되는 상기 인덕터 및 상기 캐패시터는 상호간에 스택 구조로 형성된 것을 특징으로 하는 LC 소자.And the inductor and the capacitor formed on the upper and lower portions of the support layer are formed in a stack structure with each other. 기판에 인덕터 및 캐패시터 중 어느 하나를 형성하는 단계;Forming any one of an inductor and a capacitor on the substrate; 상기 인덕터 및 상기 캐패시터 중 어느 하나가 형성된 상기 기판상에 저유전물질인 지지층을 형성하는 단계;Forming a support layer of a low dielectric material on the substrate on which one of the inductor and the capacitor is formed; 상기 지지층 상부에 상기 인덕터 및 상기 캐패시터 중 다른 하나를 형성하는 단계; 및Forming another one of the inductor and the capacitor on the support layer; And 상기 지지층의 하부인 상기 인덕터 및 상기 캐패시터가 형성되는 상기 기판의 영역을 식각하는 단계;를 포함하는 것을 특징으로 하는 LC 소자의 제작방법.And etching an area of the substrate on which the inductor and the capacitor, which are under the support layer, are formed. 제 5항에 있어서,The method of claim 5, 상기 저유전물질은 BCB(bicyclobutene) 계열 및 Polymer 계열 중 어느 한 계열의 물질인 것을 특징으로 하는 LC 소자의 제작방법.The low dielectric material is a manufacturing method of the LC device, characterized in that the material of any one of the BCB (bicyclobutene) series and Polymer series. 제 5항에 있어서,The method of claim 5, 상기 지지층을 관통하여 연결부를 형성하는 단계;를 더 포함하는 것을 특징으로 하는 LC 소자의 제작방법.And forming a connection part through the support layer. 제 5항에 있어서,The method of claim 5, 상기 지지층의 상부 및 하부에 형성되는 상기 인덕터 및 상기 캐패시터는 스택 구조로 형성되는 것을 특징으로 하는 LC 소자의 제작방법.And the inductor and the capacitor formed on the upper and lower portions of the support layer have a stack structure. 삭제delete 삭제delete
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