KR20020065053A - a thin film tra nsistor array panel for a liquid crystal display and a method for manufacturing the same - Google Patents

Abstract

PURPOSE: A TFT(Thin Film Transistor) substrate for an LCD(Liquid Crystal Display) and a method for manufacturing the same are provided to remove the conditions for forming an oxide film of high resistance from an upper part of aluminum layer for the designing of uniform process conditions and minimize the contact resistance of contact parts including pad parts by forming inter-metallic compound in the contact part by annealing. CONSTITUTION: A manufacturing method of a TFT substrate for an LCD includes the steps of forming a gate wire including gate lines(22) and gate electrodes(26) connected to the gate lines by stacking and patterning a conductive material on an insulating substrate, forming a gate insulating film, forming a semiconductor layer(40) on the gate insulating film, stacking a conductive material for a data wire and a buffer layer in sequence on the gate insulating film, removing the buffer layer after annealing, forming the data wire including data lines(62) intersecting the gate lines, source electrodes(65) connected to the data lines and adjacent to the gate electrodes, and drain electrodes(66) facing to the source electrodes with respect to the gate electrodes by patterning the conductive material for the data wire, forming first contact holes(76) for exposing the drain electrode by stacking and patterning a protection film, and forming pixel electrodes(82) electrically connected to the exposed drain electrodes.

Description

A thin film transistor substrate for a liquid crystal display and a method of manufacturing the same {a thin film tra nsistor array panel for a liquid crystal display and a method for manufacturing the same}

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

On the other hand, in order to prevent signal delay, the wiring generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of using indium tin oxide (ITO) in the pad part to secure the pad part as in a liquid crystal display device, aluminum or aluminum alloy and ITO have poor contact characteristics, and thus intervene with other metals such as molybdenum series or chromium. The aluminum or aluminum alloy of the pad portion must be removed, which complicates the manufacturing process. In order to solve this problem, a technology for securing the pad part reliability using indium zinc oxide (IZO) in the pad part has been developed. However, a problem arises in that the contact resistance of the pad portion is increased and the display characteristics of the liquid crystal display are deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a signal wiring made of a low resistance material and ensuring the reliability of a pad part.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor substrate for liquid crystal display devices.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 6A, and 7A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

5 is a sectional view showing the next step of 4b;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A, and is a cross-sectional view showing the next step in FIG. 5.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 8 taken along lines IX-IX 'and X-X',

11A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention,

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively.

12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C;

FIG. 13A is a layout view of a thin film transistor substrate at a next step of FIGS. 12A and 12B;

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A, 15A, 16A and 14B, 15B, 16B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the following steps in the order of the process. ,

17A is a layout view of a thin film transistor substrate in the next steps of FIGS. 16A and 16B,

17B and 17C are cross-sectional views taken along the lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A.

In order to solve this problem, an intermetallic compound including at least a conductive material of a buffer layer is formed between the metal layer and the buffer layer by successively stacking and annealing an aluminum-based metal layer and a buffer layer to form a wiring connected to the pixel electrode. The pixel electrode of the IZO is electrically connected to the wiring through the intermetallic compound.

According to the present invention, a gate wiring including a gate line and a gate electrode connected to the gate line is formed by stacking and patterning a conductive material for a gate wiring on an insulating substrate, and forming a gate insulating film thereon. Subsequently, a semiconductor layer is formed on the gate insulating film, the conductive material for data wiring and the buffer layer are successively stacked, annealing is performed, and the buffer layer is removed. Subsequently, the conductive material for the data wiring is patterned to form a data wiring including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode positioned opposite the source electrode to a gate electrode adjacent to the gate electrode. . Next, a first contact hole that exposes the drain electrode is formed by stacking and patterning a passivation layer, and a pixel electrode connected to the drain electrode is formed on the passivation layer.

The data line and the semiconductor layer may be formed by a photolithography process using a photoresist pattern having different thicknesses, and the photoresist pattern may include a first portion having a first thickness, a second portion thicker than the first thickness, and no thickness. It is preferred to include a third portion except for the first and second portions.

In the photolithography process, the photoresist pattern may be formed using a photomask including a first region, a second region having a higher transmittance than the first region, and a third region having a higher transmittance than the second region. In the process, the first part is formed between the source electrode and the drain electrode, and the second part is formed above the data line.

In order to adjust the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the translucent film or the exposure machine is preferably formed in the photomask, and the thickness of the first portion is 1/2 or less of the thickness of the second portion. It is preferable to form.

Here, the gate wiring and the data wiring are preferably formed of an aluminum-based metal, and the pixel electrode is preferably formed of IZO.

In the thin film transistor substrate for a liquid crystal display device according to the embodiment of the present invention, a gate line including a gate line through which a scan signal extending in a horizontal direction is transmitted and a gate electrode of a thin film transistor that is part of the gate line are formed. A gate insulating film covering the gate wirings is formed. A semiconductor pattern made of a semiconductor is formed on the gate insulating layer, and a data line extending in the vertical direction, a source electrode of a thin film transistor which is a branch of the data line, and a source electrode are separated from the source electrode and the gate electrode on the semiconductor pattern or the gate insulating layer. A data wiring including a drain electrode of an opposing thin film transistor is formed, and an intermetallic compound is formed on the data wiring. A passivation layer pattern having a first contact hole exposing the drain electrode is formed on the data line and the semiconductor pattern, and a pixel electrode electrically connected to the drain electrode through the intermetallic compound is formed on the passivation layer pattern. have.

The gate line may further include a gate pad connected to the gate line to receive a signal from the outside, and the data line may further include a data pad connected to the data line to receive a signal from the outside. Has second and third contact holes exposing the gate pad and the data pad, and are connected to the gate pad and the data pad through the second and third contact holes, and the auxiliary gate pad and the auxiliary data pad are formed on the same layer as the pixel electrode. It is formed more.

The pixel electrode is preferably made of indium tin oxide (IZO), which is a transparent conductive material, and the gate wiring and the data wiring are preferably made of an aluminum-based metal. In addition, the buffer layer preferably comprises chromium or molybdenum or molybdenum alloy.

An ohmic contact layer pattern heavily doped with impurities may be further formed between the semiconductor pattern and the data line, and the data line may be formed only on the upper portion of the semiconductor pattern. The contact layer pattern may have the same shape as the data line, and the semiconductor pattern may have the same shape as the data line except for the channel portion.

Next, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. do.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II.

A gate wiring made of an aluminum-based metal material having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is provided with a gate pad along with a protective film 70 formed thereafter. (24) It has a contact hole 74 that exposes the top.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), etc. The data wirings 62, 64, 66, 68 made of metal or conductors are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, and the data line 62 is a branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 55. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56.

The data lines 62, 65, 66, and 68 are preferably formed of a single film of aluminum series, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Examples thereof include Cr / Al (or Al alloy) or Al / Mo. In the embodiment of the present invention, the data lines 62, 65, 66, and 68 may be formed of the lower layer 601 of Cr and aluminum-based. The upper film 602 is formed.

Intermetallic compounds 90 are formed on the data lines 62, 65, 66, and 68 to minimize contact resistance with the pixel electrodes 82 or the auxiliary data pads 88 of the IZO. . Here, the intermetallic compound 90 is to improve contact characteristics between two conductive layers made of different materials, and is at least the same aluminum-based conductive material as the upper layer 602 of the data lines 62, 65, 66, and 68. It may include and include a conductive material of chromium or molybdenum or molybdenum alloy.

The passivation layer 70 is formed on the data wires 62, 65, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. The passivation layer 70 is provided with contact holes 76 and 78 respectively exposing the drain electrode 66 and the intermetallic compound 90 on the data pad 68, and the gate pad (together with the gate insulating layer 30). A contact hole 74 is formed that exposes 24.

On the passivation layer 70, the intermetallic compound 90 on the drain electrode 66 is contacted through the contact hole 76 to be electrically connected to the drain electrode 66 and to the pixel electrode 82 positioned in the pixel. An auxiliary gate pad 84 and an auxiliary data pad 88 connected to the intermetallic compound 90 above the gate pad 24 and the data pad 68 through the holes 74 and 78, respectively. Pixel wirings are formed.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In the structure according to the embodiment of the present invention, the low resistance includes the gate wirings 22, 24, and 26 and the data wirings 62, 65, 66, and 68 made of aluminum-based metal, so that the liquid crystal display having a high resolution is large. Applicable to the device. At the same time, the data pad 68 and the drain electrode 66 and the auxiliary data pad 88 and the pixel electrode 82 made of IZO are in contact with each other through the intermetallic compound 90 for minimizing their contact resistance. The display characteristic of the liquid crystal display device can be improved.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, an aluminum-based conductive film having a low resistance is stacked and patterned on the substrate 10 to a thickness of about 2,500 kV to form a gate line 22, a gate electrode 26, and a gate pad. The horizontal gate wiring including 24 is formed.

Next, as shown in FIGS. 4A and 4B, a three-layer film of the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated and patterned using a mask. The semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned to form the semiconductor layer 40 and the ohmic contact layer 50 on the gate insulating layer 30 facing the gate electrode 24.

Next, as shown in FIG. 5, the lower film 601 made of molybdenum, molybdenum alloy, chromium or the like has a thickness of about 300 kPa, and the upper film 602 made of aluminum-based metal having low resistance is about 2,500 kPa. The buffer film 900 made of molybdenum, molybdenum alloy, chromium or the like is successively laminated without sequentially releasing the vacuum. Here, the contact resistance of the contact portion in the subsequent process, such as Al ₂ O ₃ which can be formed on the aluminum-based upper film 602 in the air by successively stacking the buffer film 900 on the upper film 602 in a vacuum state It is possible to prevent the formation of a high-resistance residual film, which causes the increase. Subsequently, an annealing is performed to form an intermetallic compound 90 between the aluminum based upper layer 602 and the buffer layer 900, that is, two layers made of a conductive material. In this case, the intermetallic compound 90 includes at least the conductive material of the buffer film 900. Of course, such an intermetallic compound 90 may be formed on the gate wirings 22, 24, and 26.

6A and 6B, the buffer layer 900 is removed, and then the lower layer 601 and the upper layer 602 are patterned by a photo process using a mask to intersect the gate line 22. A source electrode 65 connected to the line 62 and the data line 62 and extending to an upper portion of the gate electrode 26, and the data line 62 is connected to one end of the data pad 68 and the source electrode 65. ) And a data line including a drain electrode 66 facing the source electrode 66 with respect to the gate electrode 26. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, the upper layer 602 may be etched by wet etching, and the lower layer 601 may be etched by dry etching. In addition, when the buffer film 900 is removed, the intermetallic compound 90 is not removed and remains on the data lines 62, 65, 66, and 68.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 7A and 7B, a protective film 70 made of silicon nitride or an organic insulating film is stacked, and then patterned by dry etching together with the gate insulating film 30 by a photolithography process using a mask. Contact holes 74, 76, and 78 are formed to expose the pad 24, the drain electrode 66, and the data pad 68.

Next, as shown in FIGS. 1 and 2, the IZO film is laminated and patterned using a mask to contact the intermetallic compound 90 on the drain electrode 66 through the contact hole 76 to contact the drain electrode ( An auxiliary gate pad 86 connected to the gate pad 24 and the intermetallic compound 90 on the data pad 68 through the pixel electrode 82 and the contact holes 74 and 78 which are electrically connected to the 66. ) And auxiliary data pads 88 are formed, respectively.

In the manufacturing method according to the exemplary embodiment of the present invention, the upper layer 602 and the buffer layer 900 of the data lines 62, 65, 66, and 68 are continuously deposited in a vacuum state, thereby forming the aluminum-based upper layer 602. It is possible to prevent the formation of a high-resistance aluminum oxide film on the surface, so that a uniform manufacturing process can be designed irrespective of changes in the manufacturing process conditions. In addition, the intermetallic compound 90 may be formed to improve contact characteristics between the IZO and the aluminum-based metal, thereby minimizing contact resistance of the contact including the pad.

As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

FIG. 8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are lines IIX-IIX 'and IX-IX', respectively, of the thin film transistor substrate shown in FIG. 8. A cross-sectional view taken along the line.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. In addition, the gate line includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of an aluminum-based conductive material having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66 and 68 may also be formed in a single layer like the gate lines 22, 24, 26 and 28, but similarly to the first embodiment, they include chromium or molybdenum or molybdenum alloys. It may be formed as a double film.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

An intermetallic compound 90 is formed on the data lines 62, 64, 65, 66, 68 as in the first embodiment.

The passivation layer 70 is formed on the data wires 62, 64, 65, 66, and 68, and the passivation layer 70 forms the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor. It has exposed contact holes 76, 78 and 72, and also has a contact hole 74 which exposes the gate pad 24 together with the gate insulating film 30. As shown in FIG. The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

Similar to the first embodiment, the intermetallic compound 90 on the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor is exposed through the contact holes 76, 78, 72. .

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO), and is electrically connected to the drain electrode 66 through the contact hole 76 via the intermetallic compound 90 to transmit an image signal. Receive. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is electrically connected to the conductor pattern 64 for the storage capacitor through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Although transparent IZO is used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 8 to 10 using four masks will be described in detail with reference to FIGS. 8 to 10 and FIGS. 11A to 17C. .

First, as shown in FIGS. 11A to 11C, the gate line 22 and the gate are formed on the substrate 10 by a photolithography process using a first mask by stacking a conductive material having low resistance as in the first embodiment. A gate wiring including a pad 24, a gate electrode 26, and a storage electrode 28 and made of an aluminum-based metal having low resistance is formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Successively deposited to a thickness of 600 kPa, and then the conductive layer 60 of the conductive material for data wiring having a low resistance like an aluminum-based metal and a buffer layer (not shown) as in the first embodiment by sputtering or the like. Laminate in succession. Subsequently, an annealing is performed to form an intermetallic compound 90 on the conductor layer 60, and then the photoresist film 110 is coated on the photoresist 110 to a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 110 is irradiated with light through a second mask and then developed to form photoresist patterns 112 and 114 as illustrated in FIGS. 13B and 13C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 14A and 14B, the exposed conductor layer 60 of the other portion B and the intermetallic compound 90 thereon are removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in Figs. 14A and 14B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 15A and 15B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 15A and 15B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 16A and 16B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in the " For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 17A to 17C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 68, and the conductive capacitor 64 for the storage capacitor, respectively. Form exposed contact holes 76, 74, 78, 74.

Finally, as shown in FIGS. 8 to 10, the contact holes 72 and 76 are deposited via the intermetallic compound 90 by depositing an IZO layer having a thickness of 400 μs to 500 μs and etching using a fourth mask. The pixel electrode 82 electrically connected to the drain electrode 66 and the conductive pattern 64 for the storage capacitor, the auxiliary hole pad 84 and the intermetallic compound 90 connected to the contact hole 74 and the gate pad 24. Auxiliary data pads 88 connected to the data pads 68 are formed in the contact holes 78 via the?

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

In this embodiment of the present invention, to improve the contact characteristics of the aluminum-based metal and the IZO film, an annealing process is performed therebetween to include at least an aluminum-based conductive material and an intermetallic including chromium, molybdenum or molybdenum alloy Compound was formed.

In the first or second embodiment of the present invention, the buffer film 900 is formed of a molybdenum tungsten alloy film at a temperature range of about 150 ° C., and annealed for about 2 hours at a temperature range of about 200 ° C. A thin film transistor substrate was fabricated, and the contact holes 72, 74, 76, and 78 were formed in the range of 4 × 4 μm to 7 × 7 μm. As a result, the contact resistance of the contact portion was measured to be about E4Ω / 200EA. I noticed a significant decrease.

As described above, according to the present invention, uniform process conditions can be designed by removing high-resistance oxide film forming conditions that can be formed on the aluminum-based metal layer in the manufacturing process, and by forming an intermetallic compound in the contact portion through annealing It is possible to minimize the contact resistance of the contact including the pad portion. In addition, by forming a wiring with low-resistance aluminum or an aluminum alloy, the characteristics of a large-screen high-definition product can be improved.

Claims (20)

Stacking and patterning a conductive material for a gate wiring on an insulating substrate to form a gate wiring including a gate line and a gate electrode connected to the gate line; Forming a gate insulating film, Forming a semiconductor layer on the gate insulating layer; Sequentially stacking a conductive material for data wiring and a buffer layer on the gate insulating layer; Annealing and then removing the buffer layer, Data including a data line crossing the gate line by patterning the conductive material for data wiring, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode disposed opposite the source electrode with respect to the gate electrode; Forming wiring, Stacking and patterning a protective film to form a first contact hole exposing the drain electrode, Forming a pixel electrode electrically connected to the exposed drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And the data line and the semiconductor layer are formed by a photolithography process using a photoresist pattern having a partially different thickness. In claim 2, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 3, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a higher transmittance than the first region, and a third region having a higher transmittance than the second region. Method for manufacturing a thin film transistor substrate for a device. In claim 4, And forming the first portion between the source electrode and the drain electrode and the second portion over the data line in the photolithography process. In claim 5, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask in order to differently control the transmittance of the first to third regions. In claim 3, And a thickness of the first portion is less than or equal to 1/2 of a thickness of the second portion. In claim 1, The conductive material for the gate wiring and the data wiring includes an aluminum-based metal. In claim 1, The buffer layer is a method of manufacturing a thin film transistor substrate for a liquid crystal display device containing chromium, molybdenum or molybdenum alloy. In claim 1, The gate line further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line further includes a data pad which transfers an image signal from an external source to the data line. The passivation layer has second and third contact holes exposing the gate pad together with the data pad and the gate insulating layer. Fabrication of a thin film transistor substrate for a liquid crystal display device further comprising an auxiliary gate pad and an auxiliary data pad electrically connected to the gate pad and the data pad through the second and third contact holes on the same layer as the pixel electrode, respectively. Way. In claim 1, And the pixel electrode is formed of IZO. In claim 1, And a resistive contact layer between the semiconductor layer and the data line. In claim 12, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the data line, the contact layer, and the semiconductor layer are formed using one mask. Board, A gate line formed on the substrate, the gate line including a gate line through which a scan signal extending in a horizontal direction is transmitted, and a gate electrode of a thin film transistor that is part of the gate line; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating layer and formed of a semiconductor; A data line formed on the semiconductor pattern or the gate insulating layer and extending in a vertical direction, a source electrode of the thin film transistor which is a branch of the data line, and separated from the source electrode to face the source electrode with respect to the gate electrode; A data line including a drain electrode of the thin film transistor; A passivation layer pattern formed on the data line and the semiconductor pattern and having a first contact hole exposing the drain electrode; A drain electrode and a pixel electrode formed on the passivation layer pattern and through the first contact hole; Intermetallic compound formed on the gate wiring or the data wiring Thin film transistor substrate for a liquid crystal display device comprising a. The method of claim 14, The gate line further includes a gate pad connected to the gate line to receive a signal from the outside, and the data line further includes a data pad connected to the data line to receive a signal from the outside, The passivation layer pattern and the gate insulating layer have second and third contact holes exposing the gate pad and the data pad. The liquid crystal further includes an auxiliary gate pad and an auxiliary data pad electrically connected to the gate pad and the data pad via the intermetallic compound in the second and third contact holes and formed of the same layer as the pixel electrode. Thin film transistor substrate for display device. The method of claim 14, The pixel electrode is a thin film transistor substrate for a liquid crystal display device made of indium tin oxide (IZO) which is a transparent conductive material. The method of claim 14, The gate wiring and the data wiring include a thin film transistor substrate for an aluminum-based metal. The method of claim 14, The intermetallic compound includes a chromium or molybdenum or molybdenum alloy. The method of claim 14, And a resistive contact layer pattern formed between the semiconductor pattern and the data line and heavily doped with impurities. The method of claim 14, The semiconductor pattern is a thin film transistor substrate for a liquid crystal display device having the same shape as the data line except for the channel portion.