KR20020060843A - Method of fabricating a semiconductor device - Google Patents
Method of fabricating a semiconductor device Download PDFInfo
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- KR20020060843A KR20020060843A KR1020010001902A KR20010001902A KR20020060843A KR 20020060843 A KR20020060843 A KR 20020060843A KR 1020010001902 A KR1020010001902 A KR 1020010001902A KR 20010001902 A KR20010001902 A KR 20010001902A KR 20020060843 A KR20020060843 A KR 20020060843A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 반도체 기판표면을 습식산화로 산화시켜 산화막을 형성하고 온도를 상승시켜 NO분위기에서 제 1 어닐링하여 질화산화막을 형성한 후 다시 산소분위기에서 제 2 어닐링시켜 질화산화막의 질소를 질화산화막 중앙상부로 이동시킨 제 1 게이트절연막용을 형성하므로서 질화산화막 제거시 질소가 기판에 잔류하지 않도록 하고, 질화산화막 제거를 과도식각으로 실시하여 기판에 잔류한 질소성분을 감소시키며, 또한, 제 2 게이트절연막 형성전 기판에 제 3 어닐링을 실시하여 기판 특성을 개선하도록 한 반도체장치의 게이트산화막 특성 개선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the surface of a semiconductor substrate is oxidized by wet oxidation to form an oxide film, the temperature is increased, and the first annealing is performed in an NO atmosphere to form a nitride oxide film. By annealing to form a first gate insulating film which moves nitrogen of the nitride oxide film to the center of the nitride oxide film, nitrogen is not retained on the substrate when the nitride oxide film is removed, and the nitrogen oxide remaining on the substrate is removed by performing excessive etching. In addition, the present invention relates to a method for improving gate oxide film characteristics of a semiconductor device in which a third annealing is performed on a substrate before forming a second gate insulating film to improve substrate characteristics.
최근에 화상, 음성 및 문자 등을 동시에 표현하는 멀티미디어(multimedia) 등과 같은 시스템(system)은 다양하고 복잡하며 향상된 기능을 가지면서 소형화 및 경량화가 요구되고 있다. 이와 같이 요구를 충족시키기 위해서는 시스템을 구성하는 서로다른 기능을 갖는 반도체회로들을 통합하여 동일한 칩에 형성하는 1칩(one chip)화 하는 기술이 개발되고 있다.Recently, systems such as multimedia, which simultaneously display images, voices, and texts, are required to be miniaturized and lightweight while having various, complex, and improved functions. In order to meet the demand as described above, a technology for forming a single chip in which semiconductor circuits having different functions constituting a system are integrated and formed on the same chip has been developed.
1칩화된 반도체회로는 서로 다른 기능을 가지며 서로 다른 전원에서 동작하는 다수의 회로가 동일한 반도체기판에 본래의 기능과 성능이 유지되도록 형성되어야 한다. 즉, 동일한 반도체기판 상에 서로 다른 구동 전압을 갖는 트랜지스터의 구성이 필요하며, 이를 구현하기 위해서는 소자들의 문턱전압(threshold voltage)을 서로 다르도록 조절하여야 한다.Single-chip semiconductor circuits have different functions, and a plurality of circuits operating in different power sources must be formed such that the original functions and performances are maintained on the same semiconductor substrate. That is, a configuration of transistors having different driving voltages is required on the same semiconductor substrate, and in order to implement this, the threshold voltages of the devices must be adjusted to be different from each other.
또한, 1칩에는 로직부와 메모리용 디램부가 동시에 형성될 수 있다.In addition, the logic unit and the memory DRAM unit may be simultaneously formed on one chip.
디램부와 로직부가 결합된 반도체장치를 제조할 경우, 디램부에 형성된 로직부의 게이트절연막으로 사용되는 질화산화막을 제거한 후 디램소자의 게이트절연막으로 사용될 열산화막을 디램부의 기판 표면을 열산화시켜 형성하게 된다. 그러나, 이 경우 질화산화막이 제거된 디램부의 기판 표면에는 질소성분이 잔류하게 되어 후속 공정에서 형성될 열산화막의 특성을 저하시키게 된다.When manufacturing a semiconductor device in which a DRAM unit and a logic unit are coupled, a thermal oxide film to be used as a gate insulating layer of the DRAM element is removed by thermally oxidizing a substrate surface of the DRAM unit after removing the nitride oxide film used as the gate insulating layer of the logic unit formed in the DRAM unit. do. However, in this case, nitrogen components remain on the substrate surface of the DRAM portion from which the nitride oxide film has been removed, thereby degrading the characteristics of the thermal oxide film to be formed in a subsequent process.
즉, 디램소자와 로직소자가 결합된 반도체장치 제조시 서로 다른 게이트전극을 형성하게 되며, 이러한 게이트전극들은 일반적으로 일측의 게이트절연막 및 게이트전극을 형성한 후 타측의 게이트절연막을 산화막으로 형성하게 된다. 그러나, 붕소이온의 기판 침투를 방지하기 위하여 로직소자의 게이트절연막을 질화산화막(nitrided oxide)으로 형성할 경우, 디램부에서 질화산화막 식각 후에도 실리콘기판의 표면에는 질소성분이 잔류하게 된다.That is, when fabricating a semiconductor device in which a DRAM device and a logic device are combined, different gate electrodes are formed, and these gate electrodes generally form one gate insulating film and one gate electrode and then form another gate insulating film as an oxide film. . However, in order to prevent boron ions from penetrating the substrate, when the gate insulating layer of the logic element is formed of nitrided oxide, nitrogen components remain on the surface of the silicon substrate even after etching the nitride oxide layer in the DRAM portion.
따라서, 잔류한 질소성분은 디램부의 기판 상에 형성되는 게이트산화막의 특성을저하시킨다.Therefore, the remaining nitrogen component deteriorates the characteristics of the gate oxide film formed on the substrate of the DRAM unit.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 게이트산화막 형성 공정단면도이다.1A to 1C are cross-sectional views of a gate oxide film forming process of a semiconductor device according to the related art.
도 1a를 참조하면, 소자활성영역과 소자격리영역이 필드산화막(11)에 의하여 정의되고, 제 1 게이트절연막으로 질화산화막이 형성되는 로직부(LOGIC1)와 제 2 게이트절연막이 형성되는 디램부(DRAM1)가 정의된 반도체 기판인 실리콘 기판(10) 상부 표면에 질화산화막(12)을 형성한다. 상기에서, 질화산화막(12)은 노출된 기판(10) 표면을 습식산화시켜 산화막을 형성한 다음 산화막을 NO분위기에서 어닐링시켜 형성한다.Referring to FIG. 1A, a device active region and a device isolation region are defined by a field oxide film 11, and a DRAM portion in which a nitride oxide film is formed as a first gate insulating film and a DRAM portion in which a second gate insulating film is formed. The nitride oxide film 12 is formed on the upper surface of the silicon substrate 10, which is a semiconductor substrate in which the DRAM1 is defined. In the above, the nitride oxide film 12 is formed by wet oxidation of the exposed surface of the substrate 10 to form an oxide film, and then annealing the oxide film in an NO atmosphere.
그리고, 질화산화막(13)상에 로직부 게이트 형성용 제 1 폴리실리콘층(13)을 화학기상증착 등으로 증착하여 형성한다.The first polysilicon layer 13 for forming logic gates is deposited on the nitride oxide film 13 by chemical vapor deposition or the like.
도 1b를 참조하면, 포토리쏘그래피로 제 1 폴리실리콘층과 질화산화막을 건식식각으로 패터닝하여 로직부(LOGIC)의 소정 부위에만 잔류한 제 1 폴리실리콘층(130)과 질화산화막(120)으로 이루어진 제 1 게이트(130)와 제 1 게이트절연막(120)을 형성한다.Referring to FIG. 1B, the first polysilicon layer and the nitride oxide layer are patterned by dry etching by photolithography to the first polysilicon layer 130 and the nitride oxide layer 120 remaining only at a predetermined portion of the logic unit LOGIC. The first gate 130 and the first gate insulating layer 120 are formed.
그러나, 게이트패터닝용 식각시 질화산화막의 질소성분(121)이 기판표면에 잔류하게 되고 이는 디램부(DRAM)에 형성되는 제 2 게이트절연막의 특성을 저하시키는 원인이 된다.However, during etching of the gate patterning, the nitrogen component 121 of the nitride oxide film remains on the substrate surface, which causes deterioration of the characteristics of the second gate insulating film formed in the DRAM.
도 1c를 참조하면, 디램부(DRAM1)의 기판(10)상에 디램소자의 제 2 게이트절연막으로 사용될 열산화막(121)을 형성한다. 상기에서, 열산화막(121)은 로직부(LOGIC1)를 마스크층(도시안함)으로 덮고 형성할 수 있다.Referring to FIG. 1C, a thermal oxide film 121 to be used as the second gate insulating film of the DRAM device is formed on the substrate 10 of the DRAM unit DRAM1. In the above description, the thermal oxide layer 121 may cover the logic unit LOGIC1 with a mask layer (not shown).
도시되지는 않았지만, 열산화막(121)상에 디램부(DRAM1) 제 2 게이트 형성용 제 2 폴리실리콘층을 형성한 후, 제 2 폴리실리콘층과 열산화막을 포토리쏘그래피로 패터닝하여 제 2 게이트와 제 2 게이트절연막을 형성한 다음, 디램부와 로직부에 적절한 도전형의 불순물 이온주입으로 도핑영역을 제 1, 제 2 게이트 측면 하단에 형성하여 트랜지스터 소자를 완성한다.Although not shown, after forming a second polysilicon layer for forming a second gate of the DRAM unit DRAM1 on the thermal oxide film 121, the second polysilicon layer and the thermal oxide film are patterned by photolithography to form a second gate. And a second gate insulating film are formed, and then a doping region is formed on the lower side of the first and second gate sides by implanting impurity ions of a suitable conductivity type in the DRAM and logic sections to complete the transistor device.
상술한 바와 같이 종래의 기술에서는 붕소이온의 기판 침투를 방지하기 위하여 로직소자의 게이트절연막을 질화산화막(nitrided oxide)으로 형성할 경우, 디램부에서 질화산화막 식각 후에도 실리콘기판의 표면에는 질소성분이 잔류하게 되어 잔류한 질소성분은 디램부의 기판 상에 형성되는 게이트산화막의 특성을 저하시키는 문제점이 있다.As described above, in the prior art, when the gate insulating layer of the logic element is formed of nitrided oxide to prevent boron ions from penetrating the substrate, nitrogen components remain on the surface of the silicon substrate even after etching the nitride oxide film in the DRAM part. As a result, the remaining nitrogen component deteriorates the characteristics of the gate oxide film formed on the substrate of the DRAM unit.
본 발명의 목적은 반도체 기판표면을 습식산화로 산화시켜 산화막을 형성하고 온도를 상승시켜 NO분위기에서 제 1 어닐링하여 질화산화막을 형성한 후 다시 산소분위기에서 제 2 어닐링시켜 질화산화막의 질소를 질화산화막 중앙상부로 이동시킨 제 1 게이트절연막용을 형성하므로서 질화산화막 제거시 질소가 기판에 잔류하지 않도록 하고, 질화산화막 제거를 과도식각으로 실시하여 기판에 잔류한 질소성분을 감소시키며, 또한, 제 2 게이트절연막 형성전 기판에 제 3 어닐링을 실시하여 기판 특성을 개선하도록 한 반도체장치의 게이트산화막 특성 개선방법을 제공함에 있다.An object of the present invention is to oxidize the surface of the semiconductor substrate by wet oxidation to form an oxide film, the temperature is increased, the first annealing in the NO atmosphere to form a nitride oxide film, and the second annealing in the oxygen atmosphere again to nitrogen nitride oxide film Forming the first gate insulating film moved to the upper center to prevent nitrogen from remaining on the substrate when removing the nitride oxide film, and removing the nitride oxide film by excessive etching to reduce the nitrogen content remaining on the substrate. A method of improving the gate oxide film characteristics of a semiconductor device in which a third annealing is performed on a substrate before forming an insulating film to improve substrate characteristics.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 소자활성영역과 소자격리영역이 정의된 반도체 기판상에 습식산화막을 형성하는 단계와, 상기 습식산화막에 NO 어닐링을 실시하여 상기 습식산화막에 질소성분이 첨가된 질화산화막을 형성하는 제 2 단계와, 상기 질화산화막에 산소 어닐링을 실시하여 상기 질소성분을 상기 질화산화막의 상부 표면으로 이동시키는 제 3 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a wet oxide film on a semiconductor substrate on which a device active region and a device isolation region are defined; And a third step of forming a nitride oxide film to which the nitrogen component is added, and moving the nitrogen component to the upper surface of the nitride oxide film by performing oxygen annealing on the nitride oxide film.
바람직하게는, 상기 제 3 단계 이후 상기 질화산화막의 소정부위를 불산으로 제거하여 상기 기판 표면을 노출시키는 단계와, 노출된 상기 기판 표면을 소정 온도의 암모니아로 세정하는 단계와, 세정된 상기 기판을 열처리하는 단계와, 열처리된 상기 기판 표면에 열산화막을 형성하는 단계를 더 포함하여 이루어진다.Preferably, after the third step, removing a predetermined portion of the nitride oxide film with hydrofluoric acid to expose the substrate surface, cleaning the exposed substrate surface with ammonia at a predetermined temperature, and cleaning the substrate. And thermally forming a thermal oxide film on the heat-treated substrate surface.
상기 목적들을 달성하기 위한 본 발명의 또 다른 실시예에 따른 반도체장치의 제조방법은 제 1 영역과 제 2 영역이 정의된 반도체 기판상에 질화산화막을 형성하는 제 1 단계와, 상기 제 1 게이트절연막상에 제 1 도전층을 형성하는 제 2 단계와, 상기 제 1 도전층과 상기 질화산화막을 제거하여 잔류한 상기 제 1 도전층과 상기 질화산화막으로 이루어진 제 1 게이트와 제 1 게이트절연막을 상기 제 2 영역에 형성하는 제 3 단계와, 노출된 상기 기판을 암모니아로 세정하여 상기 기판 표면을 소정 두께로 식각하는 제 4 단계와, 상기 기판에 어닐링을 실시하는 제 5 단계와, 상기 제 2 영역을 마스크층으로 덮는 제 6 단계와, 노출된 상기 제 2 영역의 상기 기판 표면에 열산화막과 제 2 도전층을 차례로 형성하고 패터닝하여 잔류한 상기 제 2 도전층과 상기 열산화막으로 이루어진 제 2 게이트와 제 2 게이트절연막을 형성하는 제 7 단계와, 노출된 상기 소자활성영역에 불순물 도핑층을 형성하여 소스/드레인을 상기 제 1 영역과 제 2 영역에 각각 형성하는 제 8 단계를 포함하여 이루어진다.According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a nitride oxide film on a semiconductor substrate having a first region and a second region defined therein; Forming a first conductive layer on the film; removing the first conductive layer and the nitride oxide film; and forming a first gate and a first gate insulating film formed of the first conductive layer and the nitride oxide film. A third step of forming the second area, a fourth step of cleaning the exposed substrate with ammonia, and etching the surface of the substrate to a predetermined thickness; a fifth step of annealing the substrate; and A sixth step of covering the mask layer; and a thermal oxide film and a second conductive layer are sequentially formed and patterned on the exposed surface of the substrate in the second region, and the remaining second conductive layer and the thermal oxidation are patterned. A seventh step of forming a second gate and a second gate insulating film made of a film; and an eighth forming an impurity doping layer in the exposed device active region to form source / drain in the first region and the second region, respectively. A step is made.
바람직하게, 상기 제 1 단계는 상기 기판상에 습식산화막을 형성하는 단계와, 상기 습식산화막에 NO 어닐링을 실시하여 상기 습식산화막에 질소성분이 첨가된 질화산화막을 형성하는 단계와, 상기 질화산화막에 산소 어닐링을 실시하여 상기 질소성분을 상기 질화산화막의 상부 표면으로 이동시키는 단계로 이루어진다.Preferably, the first step may include forming a wet oxide film on the substrate, performing annealing of the wet oxide film to form a nitride oxide film to which a nitrogen component is added to the wet oxide film, and Oxygen annealing is performed to move the nitrogen component to the upper surface of the nitride oxide film.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 게이트산화막 형성 공정단면도1A to 1C are cross-sectional views of a gate oxide film forming process of a semiconductor device according to the related art.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 게이트산화막 형성공정 단면도2A to 2C are cross-sectional views of a gate oxide film forming process of a semiconductor device according to the present invention.
본 발명은 서로 다른 도전형으로 도핑특성을 갖는 폴리실리콘으로 이루어진 듀알 게이트를 갖는 소자 형성시 이에 적합한 게이트절연막으로 사용되는 질화산화막의 기판 표면에 끼치는 악영향을 배제하기 위하여 질화산화막에 열처리를 실시하여 질화산화막에 포함된 질소성분을 질화산화막 상부 표면측으로 이동시켜 질소성분 잔류방지를 일차 달성하고, 질화산화막 제거로 노출되는 기판 표면 세정공정을 고온에서 암모니아로 기판 표면을 식각하는 것으로 진행하여 질소성분 잔류방지를 이차 달성한 후, 열산화막 형성전 고온의 어닐링을 기판에 실시하여 기판 표면을 완화시킨 후 열산화막을 성장시킨다.The present invention is nitrided by performing heat treatment on the nitride oxide film to remove the adverse effect on the substrate surface of the nitride oxide film used as a gate insulating film suitable for forming a device having a dual gate made of polysilicon having a doping characteristic with a different conductivity type Nitrogen contained in the oxide film is moved to the upper surface side of the nitride oxide film to achieve the first prevention of the residual nitrogen component, and the substrate surface cleaning process exposed by removing the nitride oxide film is performed by etching the substrate surface with ammonia at high temperature to prevent the nitrogen component remaining. After the secondary is achieved, a high temperature annealing is performed on the substrate before thermal oxide film formation to relax the substrate surface, and then the thermal oxide film is grown.
즉, 본 발명에서는 질화산화막을 형성하기 위하여 실리콘기판 표면을 습식산화시켜 습식산화막을 형성한 후, 반응온도를 상승시켜 소정의 온도를 유지한 다음, NO 분위기에서 어닐링을 습식산화막에 실시하여 질화산화막을 형성한 후, 다시 산소 분위기에서 약 5분 정도 어닐링을 질화산화막에 실시하여 질화산화막에 포함된 질소성분이 질화산화막 상부 표면으로 소정 거리만큼 이동시킨다. 이때, 실제로, 질화산화막에 포함된 질소성분은 약 1-3Å 정도 상측으로 이동하게 되므로, 디램부의 게이트산화막을 형성하기 위한 질화산화막 제거시 기판에 잔류하는 질소성분량을 감소시킨다. 이때, 질화산화막은 산소 투과를 억제하는 기능을 가지므로 산소 어닐링을 실시하여도 실제 질화산화막의 두께 증가량은 미미하므로 무시할 수 있다.That is, in the present invention, in order to form a nitride oxide film, the surface of the silicon substrate is wet oxidized to form a wet oxide film, and then the reaction temperature is increased to maintain a predetermined temperature, and then annealing is performed on the wet oxide film in the NO atmosphere to form the nitride oxide film. After forming, the annealing is performed on the nitride oxide film for about 5 minutes in an oxygen atmosphere to move the nitrogen component included in the nitride oxide film to the upper surface of the nitride oxide film by a predetermined distance. At this time, in practice, since the nitrogen component contained in the nitride oxide film is moved upward by about 1-3 kW, the amount of nitrogen component remaining on the substrate is reduced when the nitride oxide film for forming the gate oxide film of the DRAM part is removed. At this time, since the nitride oxide film has a function of suppressing oxygen permeation, even though oxygen annealing is performed, the increase in thickness of the nitride oxide film is insignificant and thus can be ignored.
게다가, 본 발명에서는 기판에 잔류하는 질소성분 제거를 보장하기 위하여 불산 등으로 질화산화막의 소정 부위를 제거하여 기판 표면을 노출시킨 다음, 50-60℃ 정도의 고온에서 암모니아 세정을 실시하여 기판의 표면을 약 5Å 정도 제거한다. 따라서, 암모니아 세정에 의한 기판의 식각은 질화산화막에 의하여 실리콘 기판에 잔류한 질소성분을 완전히 제거할 수 있다. 참고로, 불산에 의한 질화산화막 제거로는 기판의 잔류 질소성분을 완전히 제거하기 곤란하다.In addition, in the present invention, in order to ensure the removal of nitrogen components remaining on the substrate, the surface of the substrate is exposed by removing a predetermined portion of the nitride oxide film with hydrofluoric acid or the like, and then ammonia cleaning is performed at a high temperature of about 50-60 ° C. Remove about 5Å. Therefore, the etching of the substrate by ammonia cleaning can completely remove the nitrogen component remaining on the silicon substrate by the nitride oxide film. For reference, it is difficult to completely remove the residual nitrogen component of the substrate by removing the nitride oxide film by hydrofluoric acid.
또한, 본 발명에서는 디램용 게이트산화막 형성전에 암모니아 세정된 실리콘기판 표면에 급속열처리(rapid thermal process)를 약 1000℃에서 10초 정도 실시하거나 질소분위기 어닐링을 약 900℃에서 20분정도 실시한다. 물론, 질소 분위기 어닐링은 게이트산화막 형성 공정과 동시에(in-situ) 진행할 수 있다. 이와 같이, 디램용 게이트산화막 형성전에 어닐링을 실시하면 실리콘기판에 잔류한 질소성분이 제거되어 발생하는 기판 표면의 불균일함을 완화시키는 효과가 있다.Further, in the present invention, a rapid thermal process is performed on the surface of the ammonia-cleaned silicon substrate before forming the gate oxide film for DRAM for about 10 seconds at about 1000 ° C or about 20 minutes at about 900 ° C for nitrogen atmosphere annealing. Of course, the nitrogen atmosphere annealing may proceed in-situ with the gate oxide film forming process. As described above, annealing before forming the gate oxide film for DRAM has the effect of alleviating the nonuniformity of the substrate surface caused by the removal of the nitrogen component remaining on the silicon substrate.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 게이트산화막 형성공정 단면도이다.2A to 2C are cross-sectional views of a gate oxide film forming process of a semiconductor device according to the present invention.
도 2a를 참조하면, 소자활성영역과 소자격리영역이 필드산화막(21)에 의하여 정의되고, 제 1 게이트절연막으로 질화산화막이 형성되는 로직부(LOGIC2)와 제 2 게이트절연막이 형성되는 디램부(DRAM2)가 정의된 반도체 기판인 실리콘 기판(20) 상부 표면에 질화산화막(22)을 형성한다. 상기에서, 질화산화막(22)은 실리콘 기판(20) 표면을 습식산화시켜 습식산화막을 형성한 후, 반응온도를 상승시켜 소정의 온도를 유지한 다음, NO 분위기에서 어닐링을 습식산화막에 실시하여 질화산화막(22)을 형성한 후, 다시 산소 분위기에서 약 5분 정도 어닐링을 질화산화막에 실시하여 질화산화막에 포함된 질소성분(N)이 질화산화막(22) 상부 표면으로 소정 거리만큼 이동시킨다. 이때, 실제로, 질화산화막(22)에 포함된 질소성분(N)은 약 1-3Å 정도 상측으로 이동하게 되므로, 디램부(DRAM2)의 게이트산화막을 형성하기 위한 질화산화막 제거시 기판에 잔류하는 질소성분량을 감소시킨다. 이때, 질화산화막(22)은 산소 투과를 억제하는 기능을 가지므로 산소 어닐링을 실시하여도 실제 질화산화막(22)의 두께 증가량은 미미하므로 무시할 수 있다.Referring to FIG. 2A, the device active region and the device isolation region are defined by the field oxide layer 21, and the logic unit LOGIC2 in which the nitride oxide layer is formed as the first gate insulation layer and the DRAM unit in which the second gate insulation layer is formed ( The nitride oxide film 22 is formed on the upper surface of the silicon substrate 20, which is a semiconductor substrate in which the DRAM 2 is defined. In the above, the nitride oxide film 22 wet-oxidizes the surface of the silicon substrate 20 to form a wet oxide film, and then raises the reaction temperature to maintain a predetermined temperature, and then performs annealing on the wet oxide film in the NO atmosphere to nitride it. After the oxide film 22 is formed, annealing is again performed for about 5 minutes in an oxygen atmosphere to move the nitrogen component N included in the nitride oxide film to the upper surface of the nitride oxide film 22 by a predetermined distance. At this time, in practice, since the nitrogen component N included in the nitride oxide film 22 moves upward by about 1 to 3 kW, nitrogen remaining on the substrate when removing the nitride oxide film for forming the gate oxide film of the DRAM unit DRAM2 is removed. Reduce the amount of ingredients. At this time, since the nitride oxide film 22 has a function of suppressing oxygen permeation, even though oxygen annealing is performed, the actual increase in thickness of the nitride oxide film 22 is insignificant and thus can be ignored.
도 2b를 참조하면, 질화산화막(22)상에 로직부(LOGIC2) 게이트 형성용 제 1 폴리실리콘층(도시안함)을 화학기상증착(chemical vapor deposition) 등으로 증착하여 형성한다.Referring to FIG. 2B, a first polysilicon layer (not shown) for forming a logic portion (LOGIC2) gate (not shown) is formed on the nitride oxide film 22 by chemical vapor deposition.
그리고, 포토리쏘그래피로 제 1 폴리실리콘층과 질화산화막을 건식식각 등의 비등방성식각으로 패터닝하여 로직부(LOGIC2)의 소자활성영역을 양분하도록 소정 부위에만 잔류한 제 1 폴리실리콘층(23)과 질화산화막(220)으로 이루어진 제 1 게이트(23)와 제 1 게이트절연막(220)을 형성한다. 이때, 질화산화막의 제거는 불산 등을 이용하여 제거하고, 제 1 게이트(23) 하부에 잔류한 제 1게이트절연막(220)을 잔류 질화산화막으로 형성하는 이유는 소스/드레인 등을 형성하기 위한 불순물 이온주입시 붕소이온 등이 기판으로 침투하는 것을 방지하기 위해서이다.The first polysilicon layer 23 remaining only at a predetermined portion so as to bisect the element active region of the logic portion LOGIC2 by patterning the first polysilicon layer and the nitride oxide film by anisotropic etching such as dry etching by photolithography. A first gate 23 and a first gate insulating film 220 formed of a superoxide oxide film 220 are formed. At this time, the nitride oxide film is removed using hydrofluoric acid and the like, and the reason for forming the first gate insulating film 220 remaining under the first gate 23 as the residual nitride oxide film is an impurity for forming a source / drain or the like. This is to prevent boron ions and the like from penetrating into the substrate during ion implantation.
따라서, 로직부(LOGIC2)의 소자활성영역의 기판(20) 표면이 노출되는 동시에 디램부(DRAM2)의 소자활성영역 기판(20) 표면(S)이 노출된다.Accordingly, the surface of the substrate 20 of the device active region of the logic unit LOGIC2 is exposed, and the surface S of the device active region substrate 20 of the DRAM unit DRAM2 is exposed.
그리고, 노출된 기판 표면(S)을 세정한다. 이때, 세정공정은 약 50 - 60℃ 정도의 고온에서 암모니아를 이용하여 실시한다. 이러한 암모니아 세정 결과, 기판(20)표면이 소정 두께로 식각되어지고, 그 결과 기판 표면에 잔류한 질소성분이 제거된다. 그리고, 기판의 식각량은 약 5Å 정도이다.Then, the exposed substrate surface S is cleaned. At this time, the washing step is carried out using ammonia at a high temperature of about 50-60 ℃. As a result of this ammonia cleaning, the surface of the substrate 20 is etched to a predetermined thickness, and as a result, the nitrogen component remaining on the surface of the substrate is removed. The etching amount of the substrate is about 5 kPa.
그 다음, 기판(20) 표면에 급속열처리(rapid thermal process)를 약 1000℃에서 10초 정도 실시하거나 질소분위기 어닐링을 약 900℃에서 20분정도 실시한다. 물론, 질소분위기 어닐링은 후속공정인 디램부(DRAM2)에 형성될 게이트산화막 형성 공정과 동시에(in-situ) 진행할 수 있다. 이와 같이, 디램용 게이트산화막 형성전에 어닐링을 실시하면 실리콘기판에 잔류한 질소성분이 제거되어 발생하는 기판 표면의 불균일함을 완화시킨다.Then, a rapid thermal process is performed on the surface of the substrate 20 at about 1000 ° C. for about 10 seconds, or nitrogen atmosphere annealing is performed at about 900 ° C. for about 20 minutes. Of course, the nitrogen atmosphere annealing may proceed in-situ with the gate oxide film forming process to be formed in the DRAM unit DRAM2 which is a subsequent process. As described above, annealing prior to forming the gate oxide film for DRAM reduces the non-uniformity of the substrate surface caused by the removal of nitrogen components remaining on the silicon substrate.
도 2c를 참조하면, 디램부(DRAM2)의 기판(20)상에 디램소자의 제 2 게이트절연막으로 사용될 열산화막(24)을 형성한다. 상기에서, 열산화막(24)은 로직부(LOGIC2)를 마스크층(도시안함)으로 덮고 형성할 수 있다.Referring to FIG. 2C, a thermal oxide layer 24 to be used as the second gate insulating layer of the DRAM device is formed on the substrate 20 of the DRAM unit DRAM2. In the above description, the thermal oxide layer 24 may cover the logic unit LOGIC2 with a mask layer (not shown).
이후, 도시되지는 않았지만, 로직부(LOGIC2)를 마스크층으로 덮은 상태에서 열산화막(24)상에 디램부(DRAM2) 제 2 게이트 형성용 제 2 폴리실리콘층을 형성한 후, 제2 폴리실리콘층과 열산화막을 포토리쏘그래피로 패터닝하여 제 2 게이트와 제 2 게이트절연막을 형성한 다음, 마스크층을 제거한 다음, 디램부(DRAM2)와 로직부(LOGIC2)에 적절한 도전형의 불순물 이온주입으로 도핑영역을 제 1, 제 2 게이트 측면 하단에 형성하여 디램부(DRAM2)와 로직부(LOGIC2)에 트랜지스터 소자를 각각 완성한다.Subsequently, although not shown, the second polysilicon layer is formed on the thermal oxide film 24 in the state in which the logic portion LOGIC2 is covered with the mask layer, and then the second polysilicon layer for forming the second portion of the DRAM portion DRAM2 is formed. The layer and the thermal oxide film are patterned by photolithography to form the second gate and the second gate insulating film, and then the mask layer is removed. Then, the impurity ion implantation of the conductive type suitable for the DRAM portion and the logic portion LOGIC2 is performed. Doping regions are formed at the lower ends of the first and second gate sides to complete transistor devices in the DRAM unit DRAM2 and the logic unit LOGIC2, respectively.
따라서, 본 발명은 붕소 등의 침투성이 큰 불순물 도핑에 기인한 기판 채널영역의 오염을 방지하고자 게이트절연막을 질화산화막으로 형성시 기판 표면에 질소성분이 잔류하여 타부위에 형성되는 게이트산화막의 특성열화를 방지하여 소자신뢰성을 향상시키는 장점이 있다.Therefore, in order to prevent contamination of the substrate channel region due to the impurity doping of boron or the like, the present invention deteriorates the characteristics of the gate oxide film formed at the other part by nitrogen component remaining on the substrate surface when the gate insulating film is formed of the nitride oxide film. There is an advantage to improve the device reliability by preventing.
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