KR100677042B1 - A method for forming gate of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a gate of a semiconductor device capable of preventing the deterioration of the quality of the gate oxide film. A method of forming a gate of a semiconductor device according to the present invention includes the steps of: a) forming a dummy oxide film on a semiconductor substrate on which a device isolation film is formed by thermal diffusion; b) forming a dummy gate by forming a gate pattern on the dummy oxide layer and performing etching accordingly; c) depositing nitride films on both sidewalls of the dummy gate to form the gate sidewalls; d) implanting ions on the active region of the semiconductor substrate to form a source / drain and forming silicide on the source / drain; e) depositing a first intermetallic material on the exposed front surface and performing CMP planarization; f) patterning and etching to remove dummy gates; g) depositing a gate oxide film on a portion where the dummy gate is removed, and performing annealing using NO (Nitric Oxygen) gas; And h) depositing a gate poly on the gate oxide film and performing CMP planarization to form a gate. According to the present invention, since the gate oxide film is formed after the sidewalls are formed, penetration of contaminants can be prevented to improve breakdown voltage (BV) characteristics and improve gate oxide film quality (GOI) characteristics.

Gate, GOI, MOSFET, Boron Penetration, Breakdown Voltage

Description

A method for forming gate of semiconductor device

FIG. 1 is a diagram illustrating a semiconductor device in which quality deterioration of a gate oxide film according to the related art may occur.

2 is a diagram illustrating a semiconductor device capable of preventing the deterioration of a gate oxide film according to an embodiment of the present invention.

3A to 3N are diagrams illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device capable of preventing the deterioration of the quality of a gate oxide film.

As semiconductor devices become smaller among semiconductor technologies used in submicron-MOSFETs, as the size of devices decreases, enhancement of gate oxide integrity (GOI) characteristics is emerging as an important issue. Due to this, there is a problem in that it is easily polluted, and the gate characteristics are weakened due to boron penetration.

Here, the gate oxide integrity (GOI) refers to the quality of the gate oxide film, and is expressed as a voltage (BV: breakdown voltage) when the leakage current becomes a breakdown current while increasing the voltage.

Meanwhile, FIG. 1 is a diagram illustrating a semiconductor device in which quality deterioration of a gate oxide film according to the related art may occur.

Referring to FIG. 1, the gate oxide film 113 and the gate 114 are formed on the Si-substrate 111 on which the device isolation layer 112 is formed, and ions are implanted to activate the Si-substrate 111. Source / drain 116 is formed in the region. Here, reference numeral 115 denotes a spacer formed on both sidewalls of the gate 114.

Specifically, the method of forming the gate oxide film 113 and the gate poly 114 of the conventional semiconductor device is continuously performed after annealing so as not to damage the gate 114 after the ion implantation for the threshold voltage VT. That is, N poly ion implantation is performed after N poly patterning, and then gate patterning is performed after annealing for activating a dopant after poly ion implantation. Next, after etching to form a gate pattern, a gate poly oxide film and a sidewall nitride film are deposited to form sidewall spacers. Here, reference numeral A denotes a portion where quality deterioration of the gate oxide film occurs.

However, according to the related art, the above-described gate formation process causes deterioration of the characteristics of GOI (gate oxide integrity), i.e., impurity of impurities toward the gate oxide film through a number of thermal processes and cleaning processes. Infiltration and diffusion of contaminants also cause a phenomenon that the breakdown voltage is lowered by weakening the gate oxide film.

An object of the present invention for solving the above problems, by performing the gate formation after the conventional thermal diffusion process and the cleaning process, it is possible to prevent the gate oxide film quality deterioration that may occur during many thermal diffusion process and cleaning process after the gate oxide film process The present invention provides a method for forming a gate of a semiconductor device.

As a means for achieving the above object, the gate forming method of a semiconductor device according to the present invention,

a) forming a dummy oxide film on the semiconductor substrate on which the device isolation film is formed by thermal diffusion;

b) forming a dummy gate by forming a gate pattern on the dummy oxide layer and etching the gate pattern;

c) depositing nitride films on both sidewalls of the dummy gate to form gate sidewalls;

d) implanting ions on the active region of the semiconductor substrate to form a source / drain and forming silicide on the source / drain;

e) depositing a first intermetallic material (PSG) on the exposed front surface and performing chemical mechanical polishing (CMP) planarization;

f) patterning and etching to remove the dummy gate;

g) depositing a gate oxide film on a portion where the dummy gate is removed, and performing annealing using NO (Nitric Oxygen) gas; And

h) depositing a gate poly on the gate oxide and performing CMP planarization to form a gate

Characterized in that it comprises a.

Here, the thickness of the dummy oxide film of step a) is the same as the thickness on which the gate oxide film and the gate poly are formed.

Here, the thickness of the dummy oxide film in step a) is 1500 to 3000 kPa.

Here, the thickness of the nitride film of step c) is characterized in that 1000 ~ 3000Å.

In this case, Si ₃ N ₄ is formed by reacting DCS (SiH ₂ Cl ₂ ) + NH ₃ as an atmosphere gas for forming the nitride film of step c).

Here, step d) is characterized in that the silicide is formed only on the source / drain.

Here, the first PSG deposition thickness of step e) is performed at 1.5 to 3 times the height of the dummy gate, and is equal to the gate height by the CMP planarization.

Here, the gate oxide film of step g) is formed at 700 ~ 900 ℃ using oxygen (O ₂ ) gas or oxygen + hydrogen (O ₂ + H ₂ ) gas.

Here, the gate oxide film of step g) is formed at the bottom surface of 20 ~ 200Å, the side portion of the gate nitride film sidewall is formed as a nitride film (SiN) reacts with oxygen (O ₂ ) gas to form a thick oxide film, 10Å A less than thin gate oxide film is formed.

Here, the NO gas of step g) passes through the gate oxide film to bond with the silicon substrate to form a SiON film on the surface, and the SiON film has a thickness of 2 to 10 kPa to prevent boron ions from penetrating. Characterized in that.

Here, the SiON film is formed using N ₂ : NO = 9.5L: 0.5L.

Here, the NO gas annealing of step g) is carried out at a process temperature of 800 ~ 950 ℃, proceeds to a process pressure of less than 700 Torr, the annealing time is characterized in that carried out for 10 to 60 minutes.

Here, the NO gas of step g) forms a silicon film at the interface between the sidewall nitride film and the gate oxide film, and the silicon film is less than 10 GPa, so that phosphors or boron in the gate poly are externally diffused ( Out Diffusion) is characterized in that it serves to prevent.

Here, the gate of step h) is formed by depositing polysilicon to be utilized as a gate electrode on the gate oxide film by LPCVD method.

Here, the gate thickness of step h) is pre-deposited by a thickness of 1.5 to 3 times, and is formed by 1500Å to 3000Å by CMP planarization, and the CMP planarization is performed by the height at which the first PSG is formed. It is done.

In addition, the gate forming method of a semiconductor device according to the present invention, i) performing N + (P +) poly patterning and N + (P +) poly ion implantation on the gate; j) performing annealing for gate activation after the poly ion implantation; k) forming a gate silicide on the gate; And l) depositing a second intermetallic material on the exposed front surface.

Here, step i) is implanted with phosphorous (Phosphorous) to form an NMOS, the first PSG serves as a mask of N + poly ion implantation, step i) is implanted boron (Boron) to implant the PMOS And the first PSG serves as a mask for P + poly ion implantation.

Here, the annealing process of step j) uses a rapid thermal oxidation process (RTP), it characterized in that for 10 seconds to 600 seconds at 500 ~ 1000 ℃.

According to the present invention, the gate oxide film is formed after the sidewalls are formed, thereby preventing the infiltration of contaminants that may occur in the conventional gate etching thermal diffusion process and the cleaning process, thereby improving breakdown voltage (BV) characteristics. The characteristics of the quality (GOI) can be improved, and further, by performing NO annealing after the gate oxide film is formed, the boron penetration can be prevented to improve the gate oxide film quality, and a dummy oxide film by a thermal diffusion method is formed to form the gate oxide film. By stripping before formation, it is possible to remove surface damage from ion implantation and damage to improve gate oxide film quality.

Hereinafter, a method of forming a gate of a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

The embodiment of the present invention improves the breakdown voltage (BV) characteristics by preventing the infiltration of contaminants that may occur in the conventional gate etching thermal diffusion process and cleaning process by performing the gate formation after the conventional thermal diffusion process and cleaning process. It is disclosed that the characteristics of the gate oxide film quality (GOI) can be improved accordingly.

2 is a diagram illustrating a semiconductor device capable of preventing the deterioration of a gate oxide film according to an embodiment of the present invention.

Referring to FIG. 2, an isolation region 212 is formed on a Si-substrate 211, and a source / drain region is formed in an active region that determines electrical characteristics of the MOSFET channel between the isolation regions 212. 215 is formed. The silicide 216 is formed on the source / drain 215, and the first PSG 217 is formed.

In the gate according to the embodiment of the present invention, the dummy oxide layer is formed in advance, and then patterned and etched to form a dummy gate. After removing the dummy gate, the gate oxide layers 219a and 219b are formed, and then the gate ( 220 '). Here, the NO gas is annealed when the gate oxide films 219a and 219b are formed to form the SiON films 218a and 218b.

At this time, the NO gas is passed through the gate oxide film 219a to be bonded to the silicon substrate 211 to form a SiON film on the surface, the thickness of the SiON film is formed 2 ~ 10Å by the penetration of boron (boron) ion Will be prevented.

In addition, the NO gas forms a silicon film at an interface between the sidewall nitride film 214 and the gate oxide film 219b, and the silicon film is formed to be less than 10 GPa so that phosphors or boron in the gate poly are externally formed. It plays a role of preventing out diffusion.

Therefore, in the semiconductor device according to the embodiment of the present invention, the gate oxide films 219a and 219b are formed after the sidewall nitride film 214 is formed, thereby preventing the infiltration of contaminants to improve breakdown voltage (BV) characteristics. . In addition, NO annealing is performed after the gate oxide films 219a and 219b are formed to prevent boron penetration, and a dummy oxide film is formed by a thermal diffusion method to strip before the gate oxide film is formed, thereby implanting and damaging the ion. To remove surface damage.

3A to 3N are diagrams illustrating a gate forming method of a semiconductor device according to an exemplary embodiment of the present invention.

In the method of forming a gate of a semiconductor device according to an embodiment of the present invention, first, referring to FIG. 3A, a P-type threshold voltage (VTP) or an N-type threshold is formed on a silicon substrate 211 on which an isolation layer 212 is formed. Ion implantation for voltage VTN is performed, followed by stripping damage annealing and pad oxide film.

Specifically, ion implantation is performed to form a P-type or N-type threshold voltage (VT), followed by activating the ion implanted ions, and surface damage during ion implantation of the silicon substrate 211. In order to recover, damage prevention annealing is carried out using rapid thermal oxidation process (RTP) equipment. Here, the rapid thermal oxidation process (RTP) is usually carried out for 10 seconds to 100 using nitrogen (N ₂ ) gas at 100 ~ 1050 ℃.

Next, the pad oxide layer (pad oxide), which was previously required for forming the STI 212 and forming the channel, is removed.

Next, referring to FIG. 3B, a dummy oxide layer is formed on the exposed entire surface from which the pad oxide layer is removed.

Specifically, in order to remove physical damage to the surface of the silicon substrate 211 generated during the above-described ion implantation and the conventional CMP planarization for forming the STI 212, an oxide film (not shown) is typically performed. Not formed).

In this case, the thermal diffusion oxidation process refers to forming an oxide film (SiO ₂ ) by reacting with the silicon substrate 211 using oxygen (O ₂ ) gas or oxygen + hydrogen (O ₂ + H ₂ ) gas. An oxide film of about 50% is formed toward the silicon substrate 211 and the oxide film is oxidized about 50% toward the upper surface of the surface.

For example, if the oxide film of 1000 Å is formed, 500 Å is formed in the first silicon substrate 211 and 500 Å is formed in the upper side.

As the oxide film is formed in the upper and lower portions as described above, about 500 GPa of the silicon substrate 211 is a place where damage occurs during conventional ion implantation, and an element capable of lowering the quality of the gate oxide film to be subsequently processed is included. It is in a state.

In order to eliminate this problem, the dummy oxide film 213 is formed in advance according to the embodiment of the present invention.

The thickness of the dummy oxide film 213 may be the same as that of the gate oxide film and the gate poly to be subsequently formed. Typically, the dummy oxide film 213 has a thickness of 1500 to 3000 GPa.

The dummy oxide film 213 according to the embodiment of the present invention is subsequently etched and removed, and a gate oxide film and a gate poly-silicon are formed in the removed portion.

Next, referring to FIG. 3C, gate patterning and etching are performed on the dummy oxide layer 213. In detail, a gate pattern is subsequently formed to form a gate, and etching is performed to form a dummy gate 213 '.

Next, referring to FIG. 3D, a nitride film is deposited on both sides of the dummy gate 213 ′, and a blanket etch is performed to form the gate sidewall 214. . In this case, the thickness of the nitride film 214 is usually about 1000 to 3000 GPa, and at this time, Si ₃ N ₄ is formed by reacting DCS (SiH ₂ Cl ₂ ) + NH ₃ as an atmosphere gas for forming the nitride film 214. do.

Next, referring to FIG. 3E, ion implantation and annealing are performed to form the source / drain 215 on the active region of the silicon substrate 211.

Next, referring to FIG. 3F, silicide 216 is formed on the source / drain 215. Here, since the gate 213 'is made of an oxide film SiO ₂ , no silicide is formed, and only the source / drain 215 region on the silicon substrate 211 is formed of silicide.

Next, referring to FIG. 3G, the first PSG 217 is formed by depositing on the exposed front surface using an intermetallic material (PSG or BPSG) to separate the gate and the metal layer to be subsequently formed. Subsequently, CMP planarization is performed. In this case, the thickness of the first PSG deposition is 1.5 to 3 times the height of the dummy gate 213 'and becomes equal to the height of the gate 213' by subsequent CMP planarization.

Since the dummy oxide film serving as the dummy gate 213 'has a thickness of 1500 to 3000 GPa, the first PSG 217 has a thickness of 2250 to 9000 GPa. This is to protect the gate 213 'side safely during subsequent CMP planarization, and also to target the correct CMP thickness. Also, be careful not to damage the sidewalls 214 on both sides of the gate during the CMP planarization.

Next, referring to FIG. 3H, the dummy oxide layer 213 ′ is removed by patterning and etching according to forming a gate. In this case, the etching of the dummy oxide film 213 'may be performed by a wet method or a dry method. Here, reference numeral B denotes that the dummy oxide film 213 'is removed by etching.

Next, referring to FIG. 3I, gate oxide films 219a and 219b are formed on the etching portion B, and nitric oxide (NO) annealing is performed. Specifically, in order to form the gate oxide films 219a and 219b, oxygen (O ₂ ) gas or oxygen + hydrogen (O ₂ + H ₂ ) gas is used at 700 to 900 ° C. to 20 to 200 kPa.

In this case, the gate oxide films 219a and 219b are formed at a bottom surface of 20 to 200 GPa, but a portion where the gate nitride film sidewall 214 is formed is a nitride film (SiN) and reacts with oxygen (O ₂ ) gas to form a thick oxide film. However, the thin gate oxide film 219b is formed to be less than 10 GPa.

This is the same principle as the formation of ONO capacitors. When ONO1 (oxide) + ONO2 (nitride) + ONO3 (oxide) is formed, when ONO3 is formed, it is less than about 20 kW on the surface of the nitride film at 300 mW on the monitored wafer. .

Thereafter, when the formation of the gate oxide films 219a and 219b is completed, annealing is performed immediately using NO (Nitric oxygen) gas, wherein the NO gas passes through the gate oxide film 219a to form the silicon substrate. In combination with (211) to form a SiON film 218a on the surface. The SiON film 218a prevents boron from penetrating, thereby improving GOI characteristics and also improving breakdown voltage, thereby enhancing the characteristics of the gate oxide films 219a and 219b. It plays a role.

The SiON film 218a is usually formed using N ₂ : NO = 9.5L: 0.5L, the process temperature proceeds at 800 to 950 ° C, the process pressure proceeds at less than 700 Torr, and the annealing time is 10 It is carried out for about 60 minutes to about 60 minutes to form the thickness of the SiON film 218a.

On the other hand, a silicon film 218b of less than 10 kV is formed at the interface between the sidewall nitride film 214 and the gate oxide film 219b, and the silicon film is formed of phosphorous or boron in poly when forming P / N poly. Prevents out diffusion. Here, reference numeral C denotes in detail that the gate oxide films 219a and 219b and the SiON films 218a and 218b are formed.

Next, referring to FIG. 3J, the gate 220 is formed by depositing poly-silicon to be utilized as a gate electrode on the gate oxide layers 219a and 219b by LPCVD.

Here, the thickness of the gate 220 is to be deposited in advance by about 1.5 to 3 times the thickness in order to form a thickness of 1500 ~ 3000Å in advance, the gate 220 is accurately formed during the subsequent CMP planarization It is to. Therefore, the CMP planarization advances to 1500-3000 kPa, which is the height of the gate 220, as long as the first PSG 217 is formed.

Here, gate silicide formation and second PSG deposition are subsequently performed, in which case it is not necessary to perform CMP. The reason is that the planarization is already performed in the CMP planarization process of FIG. 3J according to the embodiment of the present invention, so that the planarization (CMP) operation is not required after the second PSG deposition to be subsequently formed.

Next, referring to FIG. 3K, patterning and ion implantation are performed to form an NMOS or PMOS.

In order to form NMOS, ion implantation is performed with phosphorous (Phosphorous), where the first PSG 217 serves as a mask for N + poly ion implantation.

In addition, boron is implanted to form PMOS, where the first PSG 217 likewise serves as a mask for P + poly ion implantation.

Next, referring to FIG. 3L, the gate 220 ′ is formed by annealing to activate poly ion implantation. At this time, the annealing process uses a rapid thermal oxidation process (RTP), and proceeds for 10 seconds to 600 seconds at 500 ~ 1000 ℃.

Next, referring to FIG. 3M, the silicide 221 is formed by depositing titanium (Ti) on the gate 220 ′.

Next, referring to FIG. 3N, the second PSG 222 film is deposited to separate the formed gate 220 ′ and the metal layer to be subsequently formed.

As a result, the gate forming method of the semiconductor device according to the embodiment of the present invention can prevent the infiltration of contaminants that may occur in the conventional gate etching thermal diffusion process and the cleaning process by forming the gate oxide layer after the sidewalls are formed. .

While the invention has been shown and described in connection with specific embodiments thereof, it is well known in the art that various modifications and changes can be made therein without departing from the spirit and scope of the invention as indicated by the claims. Anyone who has a can easily know.

According to the present invention, the gate oxide film is formed after the sidewalls are formed, thereby preventing the infiltration of contaminants that may occur in the conventional gate etching thermal diffusion process and the cleaning process, thereby improving breakdown voltage (BV) characteristics, and thus the gate oxide film quality. It can improve the characteristics of (GOI).

In addition, according to the present invention, by performing NO annealing after the gate oxide film is formed, boron penetration can be prevented to improve the gate oxide film quality.

In addition, according to the present invention, by forming a dummy oxide film by a thermal diffusion method and stripping the gate oxide film before forming the gate oxide film, it is possible to remove surface damage from ion implantation and damage, thereby improving gate oxide film quality.

Claims (22)

a) forming a dummy oxide film on the semiconductor substrate on which the device isolation film is formed by thermal diffusion; b) forming a dummy gate by forming a gate pattern on the dummy oxide layer and etching the gate pattern; c) depositing nitride films on both sidewalls of the dummy gate to form gate sidewalls; d) implanting ions on the active region of the semiconductor substrate to form a source / drain and forming silicide on the source / drain; e) depositing a first intermetallic material (PSG) on the exposed front surface and performing chemical mechanical polishing (CMP) planarization; f) patterning and etching to remove the dummy gate; g) depositing a gate oxide film on a portion where the dummy gate is removed, and performing annealing using NO (Nitric Oxygen) gas; And h) depositing a gate poly on the gate oxide layer and performing CMP planarization to form a gate; i) performing N + (P +) poly patterning and N + (P +) poly ion implantation on the gate; j) performing annealing for gate activation after the poly ion implantation; k) forming a gate silicide on the gate; And l) depositing a second intermetallic material on the exposed front surface Gate forming method of a semiconductor device comprising a. The method of claim 1, The thickness of the dummy oxide film of step a) is the same as the thickness of the gate oxide film and the gate poly to be formed. The method according to claim 1 or 2, And a thickness of the dummy oxide film of step a) is 1500 to 3000 kPa. The method of claim 1, And the thickness of the nitride film of step c) is 1000 to 3000 kV. The method of claim 1, C) forming Si ₃ N ₄ by reacting DCS (SiH ₂ Cl ₂ ) + NH ₃ as an atmosphere gas for forming the nitride film of step c). The method of claim 1, In step d), the silicide is formed only on the source / drain. The method of claim 1, And the first PSG deposition thickness of step e) is 1.5 to 3 times the height of the dummy gate, and is equal to the gate height by the CMP planarization. The method of claim 1, The gate oxide film of step g) is formed at 700 ~ 900 ℃ using oxygen (O ₂ ) gas or oxygen + hydrogen (O ₂ + H ₂ ) gas. The method of claim 1, The gate oxide film of step g) is formed at a bottom surface of 20 to 200 GPa, and the portion of the gate nitride film sidewall is formed as a nitride film (SiN) to react with oxygen (O ₂ ) gas so that a thick oxide film is not formed. A method for forming a gate of a semiconductor device, characterized in that a gate oxide film is formed. The method of claim 1, And the NO gas of step g) passes through the gate oxide film and is combined with the silicon substrate to form a SiON film on a surface thereof. The method of claim 10, The SiON film is formed using N ₂ : NO = 9.5L: 0.5L, the gate forming method of a semiconductor device. The method of claim 10, The thickness of the SiON film is 2 to 10Å is formed to prevent the penetration of boron ions, the gate forming method of a semiconductor device. The method of claim 1, The NO gas annealing of step g) is performed at a process temperature of 800 to 950 ° C., a process pressure of less than 700 Torr, and annealing time is performed for 10 to 60 minutes. Way. The method of claim 1, And the NO gas of step g) forms a silicon film at an interface between the sidewall nitride film and the gate oxide film. The method of claim 14, The silicon film has a thickness of less than 10 GPa, and serves to prevent the out diffusion of the phosphor (Phosphors) or boron in the gate poly (Out Diffusion). The method of claim 1, The gate of step h) is formed by depositing poly-silicon to be utilized as a gate electrode on the gate oxide film by the LPCVD method. The method of claim 1, The gate thickness of the step h) is deposited in advance by 1.5 to 3 times the thickness, the gate forming method of a semiconductor device, characterized in that formed by 1500Å to 3000Å by CMP planarization. The method of claim 17, And the CMP planarization is performed by a height at which the first PSG is formed. delete The method of claim 1, In step i), phosphorus (Phosphorous) is implanted to form an NMOS, wherein the first PSG serves as a mask of N + poly ion implantation method. The method of claim 1, In step i), boron is implanted to form a PMOS, and the first PSG serves as a mask for P + poly ion implantation. The method of claim 1, The annealing process of step j) uses a rapid thermal oxidation process (RTP), and the gate forming method of a semiconductor device, characterized in that for 10 seconds to 600 seconds at 500 ~ 1000 ℃.

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