KR20010058614A - Method For Forming The Gate Oxide Having Double Structure - Google Patents
Method For Forming The Gate Oxide Having Double Structure Download PDFInfo
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- KR20010058614A KR20010058614A KR1019990065965A KR19990065965A KR20010058614A KR 20010058614 A KR20010058614 A KR 20010058614A KR 1019990065965 A KR1019990065965 A KR 1019990065965A KR 19990065965 A KR19990065965 A KR 19990065965A KR 20010058614 A KR20010058614 A KR 20010058614A
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- Prior art keywords
- oxide film
- oxide layer
- nitride oxide
- atmosphere
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000007789 gas Substances 0.000 claims abstract description 15
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 abstract description 11
- -1 boron ion Chemical class 0.000 abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 230000009977 dual effect Effects 0.000 description 4
- 238000010030 laminating Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은, 게이트산화막을 이중구조로 형성하여 상부에 주입되는 보론이온의 이동을 차단하도록 하는 구조에 관한 것으로서, 특히, 반도체기판 상에 NO가스의 분위기에서 제1질화산화막을 적층한 후, 산소가스의 분위기에서 연속하여 산화막을 적층하고, 그후 재차 NO가스의 분위기에서 제2질화산화막을 적층하므로 질화산화막을 이중구조로 형성하여 상부 폴리실리콘층에 주입된 보론이온이 게이트절연막을 통하여 하부로 확산되는 것을 방지하도록 하는 이중구조 게이트산화막 형성방법에 관한 것이다.The present invention relates to a structure in which a gate oxide film is formed in a double structure to block the movement of boron ions injected into the upper portion, and in particular, after laminating a first nitride oxide film in an atmosphere of NO gas on a semiconductor substrate, Since the oxide films are successively laminated in the gas atmosphere, and then the second nitride oxide film is laminated again in the atmosphere of NO gas, boron ions implanted into the upper polysilicon layer are diffused downward through the gate insulating film. It relates to a double structured gate oxide film forming method to prevent it.
일반적으로, 반도체소자가 고집적화됨에 따라 트랜지스터 게이트의 게이트절연막(게이트 산화막이라함)의 두께 감소도 동시에 이루어지고 있다. 대략적으로 30Å이하의 두께로 적층되고 있다.In general, as semiconductor devices are highly integrated, the thickness of the gate insulating film (called a gate oxide film) of the transistor gate is also reduced. It is laminated to the thickness of about 30 micrometers or less.
특히, 듀얼게이트(이중전극게이트) PMOS의 경우, 게이트전극층에 보론 (Boron)이온을 주입하게 되는 데 이 보론이온은, 후속 열공정에서 게이트산화막을 통하여 반도체기판까지 확산되어지게 된다.In particular, in the case of a dual gate (double electrode gate) PMOS, boron ions are implanted into the gate electrode layer, and the boron ions are diffused to the semiconductor substrate through the gate oxide layer in a subsequent thermal process.
그런데, 실리콘기판으로 확산된 보론이온은 채널의 불순물에 영향을 끼쳐서 문턱전압(Vt; Threshold Voltage)을 증가시키는 역할을 하게 된다. 이는 게이트 반도체소자의 고집적하가 이루어짐에 따라 게이트의 유효길이 감소하게 되므로 문턱전압이 롤 오프(Roll-Off)되는 현상이 분명하게 나타나고 있으며, 보론의 확산 현상을 억제하지 않고서는 소자의 전기적인 특성이 나빠지는 문제점를해결할 수 없게 된다.However, the boron ions diffused into the silicon substrate affect the impurities in the channel to increase the threshold voltage (V t ). Since the effective length of the gate decreases as the gate semiconductor device is highly integrated, the threshold voltage roll-off is clearly observed, and the electrical characteristics of the device are not suppressed without suppressing the diffusion of boron. This worsening problem cannot be solved.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 NO가스의 분위기에서 제1질화산화막을 적층한 후, 산소가스의 분위기에서 연속하여 산화막을 적층하고, 그후 재차 NO가스의 분위기에서 제2질화산화막을 적층하므로 질화산화막을 이중구조로 형성하여 상부 폴리실리콘층에 주입된 보론이온이 게이트절연막을 통하여 하부로 확산되는 것을 방지하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and the first nitride oxide film is laminated on a semiconductor substrate in an atmosphere of NO gas, the oxide film is subsequently laminated in an atmosphere of oxygen gas, and then the oxide film is again produced in the atmosphere of NO gas. Since the nitride oxide film is stacked, the nitride oxide film is formed in a double structure to prevent the boron ions injected into the upper polysilicon layer from diffusing downward through the gate insulating film.
도 1 내지 도 3은 본 발명에 따른 이중구조를 갖는 게이트 산화막의 형성방법을 순차적으로 보인 도면이다.1 to 3 are views sequentially showing a method of forming a gate oxide film having a dual structure according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 질화산화막10 semiconductor substrate 15 nitrided oxide film
20 : 산화막 25 : 제2질화산화막20: oxide film 25: second nitride oxide film
이러한 목적은 반도체기판 상에 게이트절연막을 적층하는 소자 형성 방법에 있어서, 반도체기판상에 NO가스의 분위기에서 제1질화산화막을 적층하는 단계와; 상기 결과물 상에 산소가스 분위기에서 산화막을 적층하는 단계와; 상기 단계 후에 상기 산화막 상에 NO가스 분위기에서 제2질화산화막을 적층하는 단계를 포함하여 이루어진 이중구조 게이트산화막 형성방법을 제공함으로써 달성된다.An object forming method of stacking a gate insulating film on a semiconductor substrate comprises the steps of: laminating a first nitride oxide film on a semiconductor substrate in an atmosphere of NO gas; Stacking an oxide film on the resultant in an oxygen gas atmosphere; After the step is achieved by providing a double structured gate oxide film forming method comprising the step of laminating a second nitride oxide film on the oxide film in the NO gas atmosphere.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1 내지 도 3은 본 발명에 따른 이중구조를 갖는 게이트 산화막의 형성방법을 순차적으로 보인 도면이다.1 to 3 are views sequentially showing a method of forming a gate oxide film having a dual structure according to the present invention.
도 1에 도시된 바와 같이, 반도체기판(10)상에 게이트절연막을 적층하는 소자 형성 방법에 있어서, 반도체기판(10)상에 NO가스의 분위기에서 제1질화산화막 (15)을 적층하도록 한다.As shown in FIG. 1, in the device forming method of stacking a gate insulating film on a semiconductor substrate 10, the first nitride oxide film 15 is laminated on the semiconductor substrate 10 in an atmosphere of NO gas.
그리고, 도 2에 도시된 바와같이, 상기 결과물 상에 산소가스 분위기에서 산화막(20)을 적층하도록 한다.As shown in FIG. 2, the oxide film 20 is laminated on the resultant product in an oxygen gas atmosphere.
이 때, 산소가스 분위기에서 산화를 하면, 질소의 농도가 제1질화산화막(15)내에 분포하게 된다.At this time, when oxidizing in an oxygen gas atmosphere, the concentration of nitrogen is distributed in the first nitride oxide film 15.
그리고, 상기 단계 후에 상기 산화막(20) 상에 NO가스 분위기에서 제2질화산화막(25)을 적층하도록 한다.After the step, the second nitride oxide film 25 is laminated on the oxide film 20 in an NO gas atmosphere.
이와 같이, 상기 제1질화산화막(15)/산화막(20)/제2질화산화막(25)으로 된 질화산화막이 두개의 층으로 된 게이트절연막(30)을 형성하게 된다.As such, the nitride oxide film formed of the first nitride oxide film 15, the oxide film 20, and the second nitride oxide film 25 forms a gate insulating film 30 having two layers.
이후 상기 게이트절연막(30) 상에 게이트전극층(폴리실리콘층)을 적층한 후 보론이온을 주입하여 열공정으로 어닐링을 하더라도, 하부에 있는 제1,제2질화산화막(15)(25)에 의하여 반도체기판(10)으로 확산되는 것을 방지하게 된다.Thereafter, after stacking a gate electrode layer (polysilicon layer) on the gate insulating layer 30 and injecting boron ions to perform annealing in a thermal process, the first and second nitride oxide films 15 and 25 at the bottom thereof are formed. It is possible to prevent the diffusion into the semiconductor substrate 10.
상기한 바와 같이, 본 발명에 따른 이중구조 게이트산화막 형성방법을 이용하게 되면, 반도체기판 상에 NO가스의 분위기에서 제1질화산화막을 적층한 후, 산소가스의 분위기에서 연속하여 산화막을 적층하고, 그후 재차 NO가스의 분위기에서 제2질화산화막을 적층하므로 질화산화막을 이중구조로 형성하여 상부 폴리실리콘층에 주입된 보론이온이 게이트절연막을 통하여 하부로 확산되는 것을 방지하여 원활한 소자의 전기적인 특성을 얻도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the dual structured gate oxide film forming method according to the present invention is used, the first nitride oxide film is laminated on the semiconductor substrate in the atmosphere of NO gas, and then the oxide films are successively laminated in the atmosphere of oxygen gas. After that, since the second nitride oxide film is laminated in the atmosphere of NO gas, the nitride oxide film is formed in a double structure to prevent the boron ions injected into the upper polysilicon layer from diffusing downward through the gate insulating film, thereby improving the electrical characteristics of the device. It is a very useful and effective invention to get.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990065965A KR20010058614A (en) | 1999-12-30 | 1999-12-30 | Method For Forming The Gate Oxide Having Double Structure |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990065965A KR20010058614A (en) | 1999-12-30 | 1999-12-30 | Method For Forming The Gate Oxide Having Double Structure |
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| KR1019990065965A KR20010058614A (en) | 1999-12-30 | 1999-12-30 | Method For Forming The Gate Oxide Having Double Structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040025187A (en) * | 2002-09-18 | 2004-03-24 | 삼성전자주식회사 | Gate Insulating Structure Of Semiconductor Device And Method Of Forming The Same |
| KR100677042B1 (en) * | 2004-12-23 | 2007-01-31 | 동부일렉트로닉스 주식회사 | A method for forming gate of semiconductor device |
| KR100766270B1 (en) * | 2001-12-14 | 2007-10-15 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
-
1999
- 1999-12-30 KR KR1019990065965A patent/KR20010058614A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100766270B1 (en) * | 2001-12-14 | 2007-10-15 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
| KR20040025187A (en) * | 2002-09-18 | 2004-03-24 | 삼성전자주식회사 | Gate Insulating Structure Of Semiconductor Device And Method Of Forming The Same |
| KR100677042B1 (en) * | 2004-12-23 | 2007-01-31 | 동부일렉트로닉스 주식회사 | A method for forming gate of semiconductor device |
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