KR100305187B1 - Method for manufacturing gate oxynitride of semiconductor devices - Google Patents
Method for manufacturing gate oxynitride of semiconductor devices Download PDFInfo
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- KR100305187B1 KR100305187B1 KR1019990002265A KR19990002265A KR100305187B1 KR 100305187 B1 KR100305187 B1 KR 100305187B1 KR 1019990002265 A KR1019990002265 A KR 1019990002265A KR 19990002265 A KR19990002265 A KR 19990002265A KR 100305187 B1 KR100305187 B1 KR 100305187B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 4
- 230000002265 prevention Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000002019 doping agent Substances 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
반도체 소자의 미세화에 대응하여 게이트 특성이 우수하며, 신뢰성 있는 극박 게이트 산질화막을 제조하는 방법에 관한 것으로, 소자 분리 영역이 정의된 실리콘웨이퍼의 액티브 영역에 희생 산화막을 통해 임계 전압 조절, 펀치 스루 방지, 채널 스톱 형성, 웰 형성 등을 위한 이온 주입 공정을 한 후,가스 분위기에서 급속 열처리하여 액티브 영역의 실리콘웨이퍼에 질소를 도핑한다. 그리고, 액티브 영역의 실리콘웨이퍼 상에 형성된 희생 산화막을 제거한 후, 실리콘웨이퍼를 질소 가스 분위기에서 급속 열처리하여 이온 주입 공정에 의한 실리콘웨이퍼의 손상을 회복시킨다. 그리고, 실리콘웨이퍼를 열 산화하여 액티브 영역의 실리콘웨이퍼에 게이트 산질화막을 형성한다. 이와 같이 질소 이온 주입 공정 없이 산질화막을 형성하므로 이온 주입에 의한 실리콘웨이퍼의 결함을 방지할 수 있을 뿐만 아니라, 이에 따라 제조된 극박 게이트 산질화막의 전류 누설 등에 대한 특성이 향상되어 반도체 소자의 신뢰성을 향상시키며, 특히 산질화막에 의해 P 모스에서 보론 도펀트의 확산에 따른 게이트 페너트레이션을 방지할 수 있어 극박 게이트의 신뢰성을 향상시킨다.The present invention relates to a method for manufacturing a highly reliable ultrathin gate oxynitride film in response to the miniaturization of semiconductor devices, and to control threshold voltages and prevent punch through through a sacrificial oxide film in an active region of a silicon wafer in which device isolation regions are defined. After the ion implantation process for channel stop formation, well formation, Rapid heat treatment in a gas atmosphere is used to dope nitrogen into the silicon wafer in the active region. After removing the sacrificial oxide film formed on the silicon wafer in the active region, the silicon wafer is rapidly thermally treated in a nitrogen gas atmosphere to recover damage to the silicon wafer by the ion implantation process. The silicon wafer is thermally oxidized to form a gate oxynitride film on the silicon wafer in the active region. Thus, since the oxynitride film is formed without the nitrogen ion implantation process, not only the defect of the silicon wafer due to the ion implantation can be prevented, but the characteristics of the current leakage of the ultra-thin gate oxynitride film thus manufactured are improved, thereby improving the reliability of the semiconductor device. In particular, an oxynitride film can prevent gate penetration due to diffusion of boron dopant in P-MOS, thereby improving reliability of the ultrathin gate.
Description
본 발명은 반도체 소자의 게이트 산화막을 제조하는 방법에 관한 것으로, 더욱 상세하게는가스의 첨가에 의해 반도체 소자의 게이트 산화막을 산질화막(oxynitride)으로 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a gate oxide film of a semiconductor device, and more particularly A method for producing a gate oxide film of a semiconductor device into an oxynitride by addition of a gas.
현재 및 장래의 반도체 산업은 서브 미크론(sub-micron)에로의 소자 사이즈의 축소화가 진행되고 있다. 그리고, 이에 대응하여 반도체 소자의 구동을 위한 게이트 산화막의 두께도 수십 Å이하로 얇아지고 있으며, 채널 길이도 서브 미크론 -0.4 미크론- 이하로 축소되고 있다.In the current and future semiconductor industry, reduction of device size to sub-micron is underway. Correspondingly, the thickness of the gate oxide film for driving the semiconductor element is also reduced to several tens of microwatts or less, and the channel length is reduced to sub-micron -0.4 micron- or less.
그러나, 게이트 산화막의 두께가 얇아짐에 따라 P 모스 폴리 전극으로부터보론 도펀트(dopant)()의 확산에 의해 게이트 페너트레이션(penetration)이 발생하여 전계 효과 트랜지스터의 전류 누설(leakage)을 초래한다. 또한, 게이트 산화막의 두께가 30Å 정도에서는 F-N 터널(Fowler-Nordheim tunnel)에 의한 전류 누설이 발생하며, 그 이하의 두께에서는 게이트 산화막의 절연 내압 특성 저하로 직접적인 터널 현상 등이 발생한다.However, as the thickness of the gate oxide film becomes thinner, boron dopants from the P MOS poly electrode ( ), Gate penetration occurs due to the diffusion of c), resulting in current leakage of the field effect transistor. In addition, when the thickness of the gate oxide film is about 30 GPa, current leakage by the FN tunnel (Fowler-Nordheim tunnel) occurs, and when the thickness is less than that, a direct tunnel phenomenon occurs due to a decrease in dielectric breakdown voltage characteristics of the gate oxide film.
이중 보론 도펀트의 확산에 의한 게이트 페너트레이션은 근본적으로 산화막 게이트에서는 피할 수 없으며, 또한 현재 수준의 반도체 소자에서는 소자 동작의 신뢰성을 저하시키는 등 치명적인 문제를 유발케 할 수도 있다.Gate penetration due to the diffusion of the double boron dopant is fundamentally inevitable in the oxide gate, and may cause fatal problems such as deteriorating the reliability of device operation in current-class semiconductor devices.
이와 같은 극박 산화막 게이트의 단점을 보완하기 위해 최근에는 게이트 산화막대신 산질화막을 이용한 게이트 산질화막을 이용하고 있다.In order to make up for the shortcomings of the ultra-thin oxide gate, a gate oxynitride layer using an oxynitride layer has been used instead of the gate oxide layer.
그러면, 이러한 게이트 산질화막을 제조하는 종래의 방법을 도 1a 내지 도 1f를 참조하여 설명한다.Then, the conventional method of manufacturing such a gate oxynitride film is demonstrated with reference to FIGS. 1A-1F.
먼저, 도 1a에 도시한 바와 같이, 실리콘웨이퍼(1) 상에 선택적 산화법이나 트렌치에 의한 소자 분리 영역(2)을 형성하여 반도체 소자가 형성될 액티브 영역을 정의한 다음, 포토리소그래피(photolithography) 공정에 의해 액티브 영역만 드러나도록 감광막 패턴(4)을 형성한다. 그리고, 감광막 패턴(4)을 마스크로 희생 산화막(3)을 통해 액티브 영역에 임계 전압 조절, 펀치 스루(punch through) 방지, 채널 스톱(channel stop) 형성, 웰(well) 형성 등을 위한 이온 주입(I1)을 실시한다.First, as shown in FIG. 1A, an isolation region 2 is formed on the silicon wafer 1 by a selective oxidation method or a trench to define an active region in which a semiconductor device is to be formed, and then a photolithography process is performed. As a result, the photosensitive film pattern 4 is formed so that only the active region is exposed. Then, using the photoresist pattern 4 as a mask, ion implantation is performed in the active region through the sacrificial oxide layer 3 to control a threshold voltage, prevent punch through, form a channel stop, and form a well. (I1) is performed.
그 다음 도 1b에 도시한 바와 같이, 감광막 패턴(4)을 마스크로 질소(N) 이온 주입을 한 후, 도 1c에서와 같이 애싱(ashing) 및 습식 세정 공정을 통해 감광막 패턴을 제거한다.Next, as illustrated in FIG. 1B, after the photosensitive film pattern 4 is implanted with nitrogen (N) ion, the photoresist pattern is removed through an ashing and wet cleaning process as shown in FIG. 1C.
그 다음 도 1d에 도시한 바와 같이, 실리콘웨이퍼(1)를 질소 가스() 분위기에서 급속 열처리(RTP ; rapid thermal processing)(A1)하여 이온 주입에 의해 손상된 액티브 영역의 실리콘웨이퍼(1)의 표면 손상을 회복시킨 후, 도 1e에서와 같이 실리콘웨이퍼(1)를 세정하여 액티브 영역의 희생 산화막(3)을 제거한다.Then, as shown in Fig. 1D, the silicon wafer 1 is replaced with nitrogen gas ( After recovering the surface damage of the silicon wafer 1 in the active region damaged by ion implantation by rapid thermal processing (RTP) in an atmosphere, the silicon wafer 1 is cleaned as shown in FIG. The sacrificial oxide film 3 in the active region is removed.
그 다음 도 1f에 도시한 바와 같이, 퍼니스(furnace)에서 실리콘웨이퍼(1)를 열 산화(A2)한다. 그러면, 실리콘웨이퍼(1)에 이온 주입된 질소(N)에 의해 산화 속도가 억제되어 액티브 영역의 실리콘웨이퍼(1)에는 극박의 산질화막(5)이 형성된다.1F, the silicon wafer 1 is thermally oxidized (A2) in a furnace. Then, the oxidation rate is suppressed by nitrogen (N) ion-implanted into the silicon wafer 1, and an ultrathin oxynitride film 5 is formed on the silicon wafer 1 in the active region.
이와 같은 종래 반도체 소자의 게이트 산질화막의 제조 방법은 실리콘웨이퍼에 질소 이온을 주입한 후, 퍼니스에서 실리콘웨이퍼를 열 산화하는 것으로, 극박의 게이트 산질화막을 형성할 수는 있지만, 이온 주입에 따른 결함이 실리콘웨이퍼에 존재하므로 이에 의해 전류 누설이 유발될 수 있다.The conventional method for manufacturing a gate oxynitride film of a semiconductor device is to inject nitrogen ions into a silicon wafer, and then thermally oxidize the silicon wafer in a furnace, so that a very thin gate oxynitride film can be formed. Since this is present in the silicon wafer, this can cause current leakage.
또한, 열 산화 공정에서가스 첨가를 첨가하여 산질화막을 형성하는 것도 가능하지만, 이것은또는가스에 의한 산질화막에 비해 게이트 특성이 열악한 결점이 있다.In addition, in the thermal oxidation process It is also possible to form an oxynitride film by adding gas addition, but this or The gate characteristic is poor compared to the oxynitride film | membrane by gas.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 반도체 소자의 미세화에 대응하여 게이트 특성이 우수하며, 신뢰성 있는 극박 게이트 산질화막을 제조하는 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for producing an ultra-thin gate oxynitride film having excellent gate characteristics in response to miniaturization of a semiconductor device.
도 1a 내지 도 1f는 반도체 소자의 게이트 산질화막을 제조하는 종래의 방법을 도시한 공정도이고,1A to 1F are process diagrams showing a conventional method for manufacturing a gate oxynitride film of a semiconductor device,
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 게이트 산질화막을 제조하는 방법을 도시한 공정도이다.2A to 2F are process diagrams illustrating a method of manufacturing a gate oxynitride film of a semiconductor device according to the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 소자 분리 영역이 정의된 실리콘웨이퍼의 액티브 영역에 희생 산화막을 통해 임계 전압 조절, 펀치 스루 방지, 채널 스톱 형성, 웰 형성 등을 위한 이온 주입을 하고,가스 분위기에서 급속 열처리하여 실리콘웨이퍼에 질소(N)를 도핑한 후, 희생 산화막을 제거하고, 이온 주입에 따른 손상 회복을 위해 급속 열처리한 다음, 퍼니스에 의한 열 산화 공정을 실시하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides ion implantation for controlling the threshold voltage, punch-through prevention, channel stop formation, well formation, etc. through the sacrificial oxide film in the active region of the silicon wafer in which the device isolation region is defined, Doping nitrogen (N) to the silicon wafer by rapid heat treatment in a gas atmosphere, removing the sacrificial oxide film, rapid heat treatment for recovery of damage caused by ion implantation, and then performing a thermal oxidation process by a furnace .
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따라 반도체 소자의 게이트 산질화막을 제조하는 방법을 도시한 공정도이다.2A to 2F are process diagrams showing a method of manufacturing a gate oxynitride film of a semiconductor device according to the present invention.
먼저, 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11) 상에 선택적 산화법이나 트렌치에 의한 소자 분리 영역(12)을 형성하여 반도체 소자가 형성될 액티브 영역을 정의한 다음, 포토리소그래피 공정에 의해 액티브 영역만 드러나도록 감광막 패턴(14)을 형성한다. 그리고, 감광막 패턴(14)을 마스크로 희생 산화막(13)을 통해 액티브 영역에 임계 전압 조절, 펀치 스루 방지, 채널 스톱 형성, 웰 형성 등을 위한 이온 주입(I11)을 실시한 후, 도 2b에 도시한 바와 같이 애싱 및 습식 세정 공정을 통해 감광막 패턴을 제거한다.First, as shown in FIG. 2A, an isolation region 12 is formed on the silicon wafer 11 by a selective oxidation method or a trench to define an active region in which a semiconductor device is to be formed, and then an active region by a photolithography process. The photoresist pattern 14 is formed to be exposed only. After the photosensitive layer pattern 14 is used as a mask, ion implantation I11 is applied to the active region through the sacrificial oxide layer 13 to adjust the threshold voltage, prevent punch through, form a channel stop, form a well, and the like. As described above, the photoresist pattern is removed through an ashing and a wet cleaning process.
그 다음 도 2c에 도시한 바와 같이,가스 분위기에서 900℃ 내지 950℃의 온도로 700Torr 내지 760Torr의 압력에서 5초 내지 20초의 시간 동안 실리콘웨이퍼(11)를 급속 열처리(RTN)하여(A11) 액티브 영역의 실리콘웨이퍼에 질소를 도핑(doping)한다. 이때, 액티브 영역의 실리콘웨이퍼는 임계 전압 조절, 펀치 스루 방지, 채널 스톱 형성, 웰 형성 등을 위한 이온 주입 공정에 의해 내부의 실리콘(Si) 결합이 깨어져 있으므로, 고온의가스에서 해리된 질소가 실리콘웨이퍼 내부로 쉽게 확산 침투된다.Then as shown in Fig. 2c, Doping nitrogen into the silicon wafer in the active region by rapid heat treatment (RTN) of the silicon wafer 11 at a temperature of 900 to 950 ° C. at a pressure of 700 Torr to 760 Torr for 5 to 20 seconds (A11). )do. At this time, since the silicon wafer in the active region is broken by the ion implantation process for controlling the threshold voltage, preventing punch through, forming a channel stop, forming a well, and so on, Nitrogen dissociated from the gas is easily diffused and penetrated into the silicon wafer.
그 다음 도 2d에 도시한 바와 같이, 실리콘웨이퍼를 세정하여 액티브 영역의 실리콘웨이퍼(11) 상부의 희생 산화막(13)을 제거한 후, 도 2e에 도시한 바와 같이 실리콘웨이퍼(11)를 질소 가스() 분위기에서 급속 열처리(A12)하여 이온 주입에 의해 손상된 액티브 영역의 실리콘웨이퍼(11) 표면 손상을 회복시킨다. 그러면, 이온 주입 공정에 의해 발생된 실리콘웨이퍼(11)의 손상이 회복되어 실리콘은 재결합된다. 이때, 실리콘과 결합되지 않은 실리콘웨이퍼(11) 내의 도핑된 질소(N)는 실리콘웨이퍼(11)의 표면으로 파일 업(pile up)된다. 이것은 액티브 영역 실리콘웨이퍼(11) 표면의 자연 산화막층이 베리어(barrier) 역할을 함으로써 도핑된 질소(N)가 실리콘웨이퍼(11) 내부에서 달아나지 못하고 파일 업되기 때문이다.Then, as shown in FIG. 2D, the silicon wafer is cleaned to remove the sacrificial oxide film 13 on the silicon wafer 11 in the active region, and then the silicon wafer 11 is replaced with nitrogen gas (as shown in FIG. 2E). The heat treatment A12 is performed in an atmosphere to recover the surface damage of the silicon wafer 11 of the active region damaged by ion implantation. Then, the damage of the silicon wafer 11 generated by the ion implantation process is recovered and the silicon is recombined. At this time, the doped nitrogen (N) in the silicon wafer 11 that is not bonded to silicon is piled up to the surface of the silicon wafer 11. This is because the natural oxide layer on the surface of the active region silicon wafer 11 acts as a barrier so that the doped nitrogen N does not escape inside the silicon wafer 11 but piles up.
그 다음 도 1f에 도시한 바와 같이, 실리콘웨이퍼(11)를 세정하여 자연 산화막, 오염원 등을 제거한 후, 퍼니스를 이용하여 열 산화(A13)한다. 이때, 실리콘웨이퍼(11) 내부에 존재하는 질소(N)에 의해 실리콘웨이퍼(11)의 열 산화 속도가 저하되며, 도핑된 질소(N)에 의해 산질화막이 형성되므로 결과적으로 극박의 게이트 산질화막이 형성된다.Then, as shown in FIG. 1F, the silicon wafer 11 is cleaned to remove natural oxide film, pollutant, and the like, and then thermally oxidized (A13) using a furnace. At this time, the thermal oxidation rate of the silicon wafer 11 is lowered by nitrogen (N) present in the silicon wafer 11, and an oxynitride film is formed by the doped nitrogen (N). Is formed.
이와 같이 본 발명은 종래와 같은 질소 이온 주입 공정이 없으므로 이온 주입에 의한 실리콘웨이퍼의 결함을 방지할 수 있을 뿐만 아니라, 이에 따라 제조된 극박 게이트 산질화막의 전류 누설 등에 대한 특성이 향상되어 반도체 소자의 신뢰성을 향상시킬 수 있으며, 특히 산질화막에 의해 P 모스에서 보론 도펀트의 확산에 따른 게이트 페너트레이션을 방지할 수 있어 극박 게이트의 신뢰성을 향상시킬 수 있다.As described above, since the present invention does not have a nitrogen ion implantation process as described above, defects of the silicon wafer due to ion implantation can be prevented, and the characteristics of current leakage and the like of the ultrathin gate oxynitride film thus manufactured are improved. The reliability can be improved, and in particular, the gate penetration due to the diffusion of the boron dopant in the P-MOS can be prevented by the oxynitride film, thereby improving the reliability of the ultrathin gate.
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