KR100288687B1 - Gate electrode manufacturing method of semiconductor devices - Google Patents

Abstract

In order to manufacture the ultra-thin gate which is not only excellent in gate characteristics and also reliable in response to the miniaturization of semiconductor devices, the gate oxide film and polysilicon are formed on the silicon wafer where the active region is defined, and then the threshold voltage, punch through prevention, Ion implantation processes for channel stop, well formation and polysilicon doping are carried out continuously in a chain manner, with further N implantation. The silicon wafer is rapidly heat treated to recover damage by ion implantation and dopants, and the gate oxide film is nitrided to form a gate oxynitride film. Subsequently, the gate electrode is completed by patterning the polysilicon and the gate oxynitride film. After the polysilicon deposition, the ion implantation process for threshold voltage, punch through prevention, channel stop, well formation and poly doping is performed, and the process water is recovered by activating the poly doped dopant and recovering damage caused by ion implantation by rapid heat treatment. The process time can be shortened by simplifying the process, and by simultaneously performing N ion implantation and nitriding the gate oxide film during rapid heat treatment, characteristics such as leakage current and threshold voltage stabilization can be improved, and at the same time, the gate of the boron dopant in PMOS Gate deterioration due to penetration can be suppressed.

Description

GATE ELECTRODE MANUFACTURING METHOD OF SEMICONDUCTOR DEVICES

The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate electrode of a semiconductor device during a semiconductor device manufacturing process.

In the current and future semiconductor industry, the reduction of the size of semiconductor devices to sub-microns is in progress. Correspondingly, the thickness of the gate oxide film of the gate electrode for driving the semiconductor device is also reduced to several tens of microwatts or less, and the channel length is also reduced to less than sub microns.

However, as the thickness of the gate oxide film becomes thinner, gate penetration occurs due to diffusion of boron dopant (B ⁺ ) from the PMOS polyelectrode, and the gate current leakage of the field effect transistor (FET) ( leakage. In addition, when the thickness of the gate oxide film is about 30 GPa, current leakage by the FN tunnel (Fowler-Nordheim tunnel) occurs, and when the thickness is less than that, a direct tunnel phenomenon occurs due to a decrease in dielectric breakdown voltage characteristics of the gate oxide film.

Gate penetration due to the diffusion of the double boron dopant is fundamentally inevitable in the oxide gate, and may cause fatal problems such as deteriorating the reliability of device operation in current-class semiconductor devices.

In order to make up for the drawbacks of such ultrathin oxide gates, recently, a method of manufacturing a gate oxide layer as an oxynitride layer or an oxyfluoride layer by ion implantation of N ions or F ions and thermal oxidation is used.

1A and 1H, a gate electrode manufacturing method for forming a conventional gate oxide film as an oxynitride film will be described.

First, as shown in FIG. 1A, a semiconductor device is formed by forming a field oxide film 2 on a silicon wafer 1 by a selective oxidation method (LOCOS) or a trench (shallow trench isolation (STI)) process. After defining the active region to be formed, through the sacrificial oxide film 3 on the silicon wafer 1, the threshold voltage control, punch through prevention, channel stop formation, well formation, etc. Ion implantation (I1) is performed.

Next, as illustrated in FIG. 1B, N ions are implanted into the entire surface of the silicon wafer 1. At this time, in order to form the gate oxide film as an acid fluoride film, ion is implanted with F ion.

Then, as shown in FIG. 1C, the silicon wafer 1 is annealed (A1) to recover surface damage of the silicon wafer 1 in the active region damaged by the ion implantation process, and then shown in FIG. 1D. As described above, the silicon wafer 1 is cleaned to remove the sacrificial oxide film on the surface of the silicon wafer 1, and the silicon wafer 1 is charged into a furnace and thermally oxidized. Then, the oxidation rate is suppressed by the N implanted into the silicon wafer, and the ultra-thin gate oxynitride film 4 is formed by the implanted N.

Then, as shown in FIG. 1E, polysilicon 5 for electrode formation is deposited on the silicon wafer 1 front surface, and doped P-type or N-type dopant as shown in FIG. 1F. In this case, doping may be performed simultaneously with deposition of polysilicon by an in-situ process, and may be performed by various methods such as ion implantation (I 2) after poly deposition.

Then, as shown in Fig. 1G, the silicon wafer 1 is reloaded into the furnace to anneal the polysilicon 5 to diffuse the doped dopant and simultaneously activate the polysilicon 5 to lower the resistance.

1H, the gate electrode of the semiconductor element is completed by patterning the polysilicon 5 and the gate oxynitride film 4 on the silicon wafer 1 above.

In the conventional method of manufacturing a gate electrode of a semiconductor device, the ion implantation process for threshold voltage, punch through prevention, channel stop, well formation, ion implantation process for nitridation gate formation, ion implantation process for poly doping, etc. In addition to performing the ion implantation process, annealing for the restoration of damage caused by the ion implantation process and annealing for the activation of the poly-doped dopant have to be performed, thus increasing the number of processes and increasing the processing time.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a method for manufacturing an ultra-thin gate which is not only excellent in gate characteristics but also reliable in a simple process in response to miniaturization of semiconductor devices.

1A to 1H are process diagrams schematically illustrating a method of forming a gate electrode of a conventional semiconductor device.

2A to 2E are process diagrams schematically illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.

In order to achieve the above object, the present invention after forming the gate oxide film and polysilicon on the silicon wafer, the ion implantation process for the threshold voltage, punch through prevention, channel stop, well formation and polysilicon doping on the polysilicon Is continuously carried out in a chain manner, and additionally ion implanted, the silicon wafer is rapidly heat treated to recover damage from ion implantation and dopants are activated, and the gate oxide film is nitrided to form a gate oxynitride film. .

It is preferable to perform an ion implantation process so that the implantation depth of N to be ion implanted is within the polysilicon internal region, and the ion implantation amount is 1E12 to 1E14.

The rapid heat treatment in the above is preferably carried out for 5 seconds to 50 seconds at a temperature of 950 ℃ to 1100 ℃, pressure of 700 Torr to 780 Torr.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2E are process diagrams schematically illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, the field oxide film 12 is formed on the silicon wafer 11 by a selective oxidation method or a trench process to define an active region in which a semiconductor device is to be formed, and then the silicon wafer 11 is cleaned. The sacrificial oxide layer on top of the active region silicon wafer is removed to expose the silicon wafer surface. The gate oxide film 13 is grown on the active region silicon wafer by charging the silicon wafer 11 into the furnace and thermally oxidizing the silicon wafer 11.

Next, as shown in FIG. 2B, polysilicon 14 for forming a polyelectrode is deposited on the entire surface of the silicon wafer 11, that is, on the gate oxide layer 13.

Next, as shown in FIG. 2C, an ion implantation process I11 for threshold voltage, punch through prevention, channel stop, well formation, etc. and an ion implantation process I11 for polysilicon doping are performed on the polysilicon 14. Is carried out continuously in a chain manner, and the N ion implantation step (I11) is further performed. As a result, the dopant to be implanted (I11) penetrates through the gate oxide layer 13, resulting in through-gate ion implantation. At this time, the ion implantation depth of N is within the polysilicon internal region, and the ion implantation process is performed such that the ion implantation dose is about 1E12 to 1E14.

Then, as shown in FIG. 2D, the silicon wafer 11 is rapidly heat treated (A11) to recover damage caused by ion implantation, and simultaneously activate dopants doped with polysilicon. The N implanted into the polysilicon by the rapid heat treatment (A11) is thermally diffused to nitride the gate oxide film, thereby automatically forming the gate oxynitride film 16. At this time, the rapid heat treatment (A11) process is preferably carried out for 5 seconds to 50 seconds at a temperature of about 950 ℃ to 1100 ℃, a pressure of about 700 Torr to 780 Torr.

Next, as shown in FIG. 2E, the gate electrode of the semiconductor device is completed by patterning the polysilicon 14 and the gate oxynitride film 16 on the silicon wafer 11.

As described above, the present invention performs ion implantation process for threshold voltage, punch through prevention, channel stop, well formation and poly doping after polysilicon deposition, and recovers damage caused by ion implantation and activates poly doped dopant by rapid heat treatment. In addition, the process time can be simplified to shorten the process time, and additionally, N ion implantation can be performed at the same time to nitrate the gate oxide film during the rapid heat treatment to form the gate oxynitride film, thereby improving characteristics such as leakage current and threshold voltage stabilization. In addition, gate degradation due to gate penetration of the boron dopant in the PMOS can be suppressed.

Claims (3)

Cleaning the silicon wafer in which the active region is defined to remove the sacrificial oxide film, and thermally oxidizing the silicon wafer to form a gate oxide film, and depositing polysilicon on the silicon wafer; Continuously implanting an ion implantation process over the polysilicon for threshold voltage, punch through prevention, channel stop, well formation and polysilicon doping, further implanting N; Rapidly heat-treating the silicon wafer to activate the dopants for damage recovery by the ion implantation, and to nitride the gate oxide film to form a gate oxynitride film; And forming a gate electrode by patterning the polysilicon and the gate oxynitride film. The method of claim 1, wherein an ion implantation process is performed such that an implantation depth of N to be implanted is within the polysilicon internal region, and an ion implantation amount is 1E12 to 1E14. . The method of claim 1, wherein the rapid heat treatment is performed at a temperature of 950 ° C. to 1100 ° C. and a pressure of 700 Torr to 780 Torr for 5 seconds to 50 seconds.