JP3319721B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a highly reliable gate insulating film and functioning as a MOS field effect transistor or a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, in many fields using semiconductor devices, a gate electrode is formed on a gate insulating film, a channel region is formed below the gate electrode, and source / drain diffusion layers are formed on both sides thereof. A MOS field-effect transistor (MOSFET) in which the current value between the source and drain diffusion layers and on / off are controlled by a voltage applied to the gate electrode; A non-volatile semiconductor memory device having a floating gate electrode for holding a charge is widely used.

FIGS. 15A to 15D are cross-sectional views showing a manufacturing process of a semiconductor device according to a conventional technique functioning as a MOSFET. In FIGS. 15A to 15D, 11
1 is a semiconductor substrate, 112 is a gate oxide film, 113 is a gate electrode, 114 is arsenic ion as an impurity ion implanted into the semiconductor substrate to form an LDD diffusion layer.
15a and 115b are LDD diffusion layers, 116a and 116b are side wall spacers, 117 is a source diffusion layer, and 118 is a drain diffusion layer.

Hereinafter, a method for manufacturing a semiconductor device according to the prior art will be described with reference to FIGS.

In a step shown in FIG. 15A, a gate oxide film 11 is formed on a first conductivity type (for example, P-type) Si substrate 111.
2, the gate electrode 113 is formed.

Next, in the step shown in FIG. 15B, a low concentration arsenic ion 114 as an impurity ion of the second conductivity type is implanted into the Si substrate 111 from above the gate electrode 13. LDD diffusion layers 115a and 115b are formed in regions located on both sides of the gate electrode 113 in the inside.

Next, in a step shown in FIG. 15C, after an insulating film such as a silicon oxide film is deposited on the substrate, anisotropic etching is performed to form a sidewall spacer 116a on the side surface of the gate electrode 113. , 116b. At this time, in a region that is not covered with the gate electrode 113 or the sidewall spacers 116a and 116b, the gate oxide film 112 is also etched.

Thereafter, in a step shown in FIG. 15D, the gate electrode 113 and the side wall spacers 116a, 116a, 1
Arsenic ions as high-concentration second-conductivity-type impurity ions are implanted into Si substrate 111 from above 16b, and LD
A source diffusion layer 117 and a drain diffusion layer 118 are formed outside the D diffusion layers 115a and 115b, respectively.

Also, a gate oxide film, a floating gate electrode, an O
A nonvolatile semiconductor memory device having a structure in which an NO film and a control gate electrode are stacked also basically has the structure shown in FIGS.
It is formed by the same procedure as the step shown in FIG.

[0010]

The leakage characteristics and disturb characteristics (changes in threshold voltage with time) of MOSFETs and nonvolatile semiconductor memory devices having the above-mentioned conventional structures vary greatly, and the values themselves are not sufficient. There was also a problem that there were many points to be improved. Then, the present inventor examined the cause of the above-mentioned variation or deterioration of the characteristics, and found that damage at the end of the gate oxide film at the time of impurity ion implantation was considered as one cause. In other words, in the impurity ion implantation step shown in FIG. 15B, ion implantation is generally performed in a direction inclined by about 7 ° from a direction perpendicular to the substrate surface in order to prevent channeling and the like. At this time, there is a possibility that impurity ions penetrating the end of the gate electrode are introduced into the gate oxide film. In the case of a nonvolatile semiconductor memory device, it is considered that impurities are introduced not only into the gate oxide film but also into the interlayer insulating film such as the ONO film.

It has also been observed that in any of the manufacturing steps including a step involving a heat treatment in an oxidizing atmosphere, both ends of the gate oxide film become extremely thick, and a birth beak occurs. The bird's beak may have the same effect as the change in the gate length, that is, a variation in the threshold voltage.

In particular, in a nonvolatile semiconductor memory device, a bird's beak occurs in a gate oxide film, thereby deteriorating electron injection efficiency or extraction efficiency, or a bird's beak occurs in an interlayer insulating film between a floating gate electrode and a control gate electrode. As a result, there is also a problem that a local stress is applied to the portion to deteriorate the device characteristics.

A first object of the present invention is to reduce the variation in characteristics such as the threshold voltage by taking measures for suppressing damage to both ends of a gate oxide film or occurrence of bird's beak. It is an object of the present invention to provide a method for manufacturing a semiconductor device which functions as a MOSFET having excellent characteristics.

A second object of the present invention is to reduce the variation in characteristics such as threshold voltage by taking measures such as suppressing the damage to the gate oxide film and the occurrence of bird's beak. It is an object of the present invention to provide a method of manufacturing a semiconductor device which functions as a good nonvolatile semiconductor memory device itself.

[0015]

A first method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device functioning as a MOS field effect transistor, wherein a gate insulating film and a gate electrode are formed on a semiconductor substrate. (A) forming sequentially, and a CVD insulating film made of a silicon oxide film having a thickness of 5 nm or more and 30 nm or less covering the exposed surface of the gate electrode by a CVD method at a temperature of 800 ° C. or less on the semiconductor substrate. And (b) forming an LDD diffusion layer of the first conductivity type in the semiconductor substrate by implanting impurity ions into the semiconductor substrate from above the gate electrode and the CVD insulating film ( and c) and before and after the step (c), impurity ions are implanted into the semiconductor substrate, so that the semiconductor substrate has a second conductivity type. Forming a diffusion layer to be a punch-through stopper in step (d); and step (c) above.
And after (d), the CV on the side of the gate electrode
(E) forming a sidewall spacer with the D insulating film interposed therebetween and removing the CVD insulating film on the semiconductor substrate; and after the step (e), a first conductivity type is formed in the semiconductor substrate. Forming a source / drain diffusion layer of (d), wherein the LDD diffusion layer is formed so as to overlap the gate electrode.

According to this method, the phenomenon that the impurity ions implanted into the semiconductor substrate in the step (c) penetrate the gate electrode at the end of the gate electrode can be suppressed, so that the damage in the gate insulating film can be suppressed. Therefore, a semiconductor device having a highly reliable gate insulating film can be manufactured, and high reliability of the semiconductor device can be realized. On the other hand, since the growth of the insulating film by the CVD method can be performed at a low temperature of 800 ° C. or less, bird's beak does not occur in the gate insulating film and does not become an obstacle to miniaturization of a semiconductor device. Further, since the gate electrode is covered with the CVD insulating film, diffusion of impurities contained in the gate electrode to the outside can be prevented, so that a semiconductor device with less variation in characteristics can be formed.

By performing the steps of coating the CVD insulating film and implanting the impurity ions twice or more, an LDD structure having a gentle impurity concentration gradient can be obtained, and a semiconductor device having excellent electric characteristics can be realized. .

In addition, the thickness of the CVD insulating film is 5 nm.
Since the thickness is 30 nm or less , damage to the gate insulating film due to ion implantation can be reliably reduced, and the LDD diffusion layer and the gate electrode can be overlapped within an appropriate range without excessive heat treatment. .

In the first method for manufacturing a semiconductor device , after the steps (c) and (d), the step
Before (e), a step of performing a heat treatment for recovering damage in the gate insulating film caused by the implantation of the impurity ions in an atmosphere containing at least oxygen is further provided. Leakage can be reduced more effectively, and problems such as a change in threshold voltage with time can be suppressed.

By performing the step of performing the above heat treatment in an oxynitriding atmosphere, it is possible to further obtain an effect of reducing a trap amount by repairing a dangling bond existing between the gate insulating film and the semiconductor substrate. .

According to a second method of manufacturing a semiconductor device of the present invention,
A method of manufacturing a semiconductor device that functions as a MOS field effect transistor, and the step (a) sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate, on the semiconductor substrate, CVD at 800 ° C. below the temperature The thickness covering the exposed surface of the gate electrode is 5 nm or more and 3
A step (b) of forming a CVD insulating film made of a silicon oxide film having a thickness of 0 nm or less, and a step of performing anisotropic etching of the CVD insulating film to leave a side wall CVD insulating film on the side surface of the gate electrode ( c) forming an LDD diffusion layer of the first conductivity type in the semiconductor substrate by implanting impurity ions into the semiconductor substrate from above the gate electrode and the side wall CVD insulating film; Forming a diffusion layer serving as a punch-through stopper of the second conductivity type in the semiconductor substrate by implanting impurity ions into the semiconductor substrate before and after the step (d); The above steps
After (d) and (e) , a step (f) of forming a side wall spacer on the side surface of the gate electrode with the side wall CVD insulating film interposed therebetween, and after the step (f), the inside of the semiconductor substrate is formed. Forming a source / drain diffusion layer of the first conductivity type (g ).
This is a method in which a diffusion layer is formed so as to overlap the gate electrode.

According to this method, since the CVD insulating film on the semiconductor substrate is removed, the acceleration energy at the time of impurity ion implantation for forming the LDD diffusion layer can be reduced. Therefore, penetration of impurity ions at both ends of the gate electrode can be further suppressed.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment First, a first embodiment of the present invention will be described. FIG.
5A to 5E are cross-sectional views illustrating a process of manufacturing a semiconductor device functioning as a MOSFET according to the embodiment.

1A to 1E, reference numeral 11 denotes Si.
A substrate, 12 a gate oxide film, 13 a gate electrode, 14 arsenic ions as impurity ions implanted into the Si substrate 11 to form an LDD diffusion layer, 15a and 1
5b is an LDD diffusion layer, 16a and 16b are side wall spacers, 17 is a source diffusion layer, 18 is a drain diffusion layer, and 19 is a CVD insulating film made of a silicon oxide film deposited by a CVD method.

First, in a step shown in FIG. 1A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation, and then a gate oxide film 12 is formed thereon. A gate electrode 13 made of polysilicon doped with phosphorus is formed.

Next, in a step shown in FIG. 1B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 10 nm is deposited on the substrate by a low pressure CVD method, and the gate oxide film 12 and the gate electrode 13 are formed by CVD. It is covered with an insulating film 19.

Next, in the step shown in FIG. 1C, the Si substrate 11 is formed from above the gate electrode 13 and the CVD insulating film 19.
Arsenic ions 14 are implanted into the substrate, and N-type LDDs are
The diffusion layers 15a and 15b are formed. The implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁴ c.
m- ² . In order to overlap the LDD diffusion layers 15a and 15b with the gate electrode 13, the ion implantation angle is inclined by about 25 ° from a direction substantially perpendicular to the substrate surface (four-step implantation).

Next, in the step shown in FIG. 1D, after a TEOS film is deposited on the substrate, anisotropic etching is performed, and a TEOS film is formed on the side surface of the gate electrode 13 with the CVD insulating film 19 interposed therebetween. Sidewall spacers 16a,
16b is formed. In this step, the gate oxide film 12 and the CVD insulating film 19 on the Si substrate 11 are removed.

Thereafter, in the step shown in FIG. 1E, arsenic ions are implanted into the Si substrate 11 from above the gate electrode 13, the CVD insulating film 19, and the sidewall spacers 16a and 16b, thereby forming the LDD diffusion layer 15a. , 15b, an N-type source diffusion layer 17 and a drain diffusion layer 18 are formed respectively. The ion implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
In the step shown in FIG. 3C, since the side surface of the gate electrode 13 is covered with the CVD insulating film 19, the LDD diffusion layer 1 is formed.
Arsenic ions 14 implanted into the Si substrate 11 for the purpose of forming 5a and 15b penetrate the gate electrode 13 at the end of the gate electrode 13 and the gate oxide film 1 thereunder.
2 can be suppressed. Therefore, damage in gate oxide film 12 caused by the above-described conventional method of manufacturing a semiconductor device, specifically, a region of gate oxide film 12 that functions as a gate insulating film (located below gate electrode 13). Part) (similarly in the following embodiments),
A semiconductor device having a gate oxide film having high insulation and reliability can be obtained. That is, MOSFE
High reliability of the semiconductor device functioning as T can be realized.

Further, the CVD formed by the CVD method
Since the growth of the insulating film is performed at a low temperature of 800 ° C. or less, as in the case of forming a thick protective oxide film by thermal oxidation performed at a relatively high temperature, the gate oxide film 1 is formed.
The bird's beak does not occur at both ends of a region (a region actually functioning as a gate insulating film) located below the gate electrode 13 of the gate electrode 2, and the gate length can be accurately controlled. Therefore, it is advantageous for miniaturization of a semiconductor device. Further, by performing the CVD process at a lower temperature condition than the thermal oxidation process, impurities such as phosphorus doped in the gate electrode 13 diffuse into the gate oxide film 12 and the Si substrate 11 below the gate electrode 13. Can be suppressed.

Further, the gate electrode 13 is formed on the CVD insulating film 1.
By covering with 9, it is possible to prevent impurities in the gate electrode 13 from being diffused to the side and above the gate electrode 13, so that there is also an advantage that a semiconductor device with less variation in characteristics can be obtained. .

Before or after the step of implanting arsenic ions 14 shown in FIG. 1C of this embodiment, B (boron) ions or BF ₂ ions for forming a P-type diffusion layer serving as a punch-through stopper are provided. May be implanted into the Si substrate 11 from above the CVD insulating film 19 and the gate oxide film 12.
Further, P (phosphorus) ions may be used instead of arsenic ions. It is clear that the same effects as in the present embodiment can be obtained in these cases.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG.
5A to 5E are cross-sectional views illustrating a process of manufacturing a semiconductor device functioning as a MOSFET according to the embodiment.
2A to 2E, 11 is a Si substrate, 12 is a gate oxide film, 13 is a gate electrode, 14 is arsenic as an impurity ion implanted into the Si substrate 11 to form an LDD diffusion layer. Ions, 15a and 15b are LDD
Diffusion layers, 16a and 16b are side wall spacers, 17 is a source diffusion layer, 18 is a drain diffusion layer, 19
Is C composed of a silicon oxide film deposited by the CVD method.
This is a VD insulating film.

First, in the step shown in FIG. 2A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm was formed on a Si substrate 11 made of P-type silicon, and phosphorus was doped thereon. Gate electrode 1 made of polysilicon
Form 3

Next, in the step shown in FIG. 2B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 10 nm is deposited on the substrate by a low pressure CVD method, and the gate oxide film 12 and the gate electrode 13 are formed by CVD. It is covered with an insulating film 19. Subsequently, anisotropic etching is performed to remove the CVD insulating film 19 excluding the portion on the side surface of the gate electrode 13 and the gate oxide film 12 excluding the portion below the gate electrode 13.

Next, in the step shown in FIG. 2C, the Si substrate 11 is placed from above the gate electrode 13 and the CVD insulating film 19.
Arsenic ions 14 are implanted into the substrate, and N-type LDDs are
The diffusion layers 15a and 15b are formed. The implantation conditions are, for example, an acceleration energy of 30 keV and a dose of 5 × 10 ¹⁴ c.
m- ² . In order to overlap the LDD diffusion layers 15a and 15b with the gate electrode 13, the ion implantation angle is inclined by about 25 ° from a direction substantially perpendicular to the substrate surface (four-step implantation).

Next, in the step shown in FIG. 2D, after depositing a TEOS film on the substrate, anisotropic etching is performed to form a film on the side surface of the gate electrode 13 from the TEOS film via the CVD insulating film 19. Sidewall spacers 16a, 1
6b is formed.

Thereafter, in the step shown in FIG. 2E, arsenic ions are implanted into the Si substrate 11 from above the gate electrode 13, the CVD insulating film 19, and the sidewall spacers 16a and 16b, thereby forming the LDD diffusion layer 15a. , 15b, an N-type source diffusion layer 17 and a drain diffusion layer 18 are formed respectively. The ion implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
In the step shown in FIG. 3C, since the side surface of the gate electrode 13 is covered with the CVD insulating film 19, the LDD diffusion layer 1 is formed.
Arsenic ions 14 implanted into the Si substrate 11 for the purpose of forming 5a and 15b are prevented from penetrating through the gate electrode 13 at the end of the gate electrode 13. Therefore,
The same effects as in the first embodiment can be obtained.
In particular, according to the method of the present embodiment, in the step shown in FIG.
Since the insulating film 19 is removed, the implantation energy at the time of implanting impurity ions can be reduced. As a result, there is an advantage that the amount of impurities penetrating through the CVD insulating film 19 on the side surface of the gate electrode 13 and reaching the gate oxide film 12 is reduced as compared with the manufacturing process of the first embodiment.

Before or after the step of implanting arsenic ions 14 shown in FIG. 2C of this embodiment, B (boron) ions or BF ₂ ions for forming a P-type diffusion layer serving as a punch-through stopper May be implanted into the Si substrate 11 from above the CVD insulating film 19 and the gate oxide film 12.
In that case, it is apparent that the same effects as those of the present embodiment can be obtained.

The coating of the CVD insulating film 19 and the implantation of the impurity ions for forming the LDD diffusion layers 15a and 15b are repeated twice or more while gradually increasing the concentration of the impurity ions, whereby a gentler operation is achieved. An LDD structure having an impurity concentration gradient can be obtained, and a semiconductor device having excellent electric characteristics can be realized.

-Proper Range of Thickness of CVD Insulating Film-Next, the proper range of the thickness of the CVD insulating film 19 in the first and second embodiments will be described.

FIG. 3 shows the CV of the leak characteristic of the gate oxide film.
FIG. 4 is a characteristic diagram showing a dependency on a D insulating film thickness. In the figure, the horizontal axis represents the thickness of the CVD oxide film, and the vertical axis represents the leak current of the gate oxide film. As shown in the figure, by depositing a CVD insulating film of 5 nm or more, the leak current of the gate oxide film is drastically reduced, and it can be seen that the effect of reducing damage to the gate oxide film due to ion implantation is great. . However, as the thickness of the CVD insulating film increases, the effect of reducing the damage becomes more remarkable. However, in order to allow the LDD diffusion layer and the gate electrode to overlap within an appropriate range without excessive heat treatment, the CVD insulating film is required. Is preferably 30 nm or less.

In the first and second embodiments, the CVD insulating film 19 is made of a silicon oxide film. However, the CVD insulating film 19 may be made of a silicon nitride film. When the CVD film 19 is formed of a silicon oxide film, there is an advantage that stress applied to a base is smaller than that of a silicon nitride film. On the other hand, when the CVD insulating film 19 is formed of a silicon nitride film, there is an advantage that the occurrence of bird's beaks in the gate oxide film 12 can be more effectively suppressed in a subsequent step performed at a high temperature (such as an impurity diffusion step). is there. This is the same in an embodiment relating to a MOSFET described later.

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIG.
5A to 5C are cross-sectional views illustrating a process of manufacturing a semiconductor device functioning as the nonvolatile semiconductor memory device according to the embodiment. 4A to 4C, 11 is a Si substrate, 12 is a gate oxide film, 17 is a source diffusion layer, 18 is a drain diffusion layer, 19 is an insulating film deposited by a CVD method, and 20 is a floating gate electrode. , 21 are interlayer insulating films, 22 is a control gate electrode, and 23 are phosphorus ions as impurity ions implanted into the Si substrate 11 to form a source diffusion layer and a drain diffusion layer.

First, in a step shown in FIG. 4A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon, and then a phosphorus-doped silicon oxide film is formed thereon. A floating gate electrode 20 made of polysilicon, an interlayer insulating film 21 made of an ONO film (a three-layer film having an oxide film provided above and below a nitride film), and a control gate electrode 22 made of polysilicon doped with phosphorus. I do.

Next, in a step shown in FIG. 4B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 10 nm is deposited on the substrate by a low pressure CVD method, and a gate oxide film 12 is formed.
And a multilayer body composed of the floating gate electrode 20, the interlayer insulating film 21, and the control gate electrode 22 are covered with a CVD insulating film.

Thereafter, in the step shown in FIG.
Phosphorus ions 2 are introduced into the Si substrate 11 from above the control gate electrode 22 and the floating gate electrode 20 covered with the insulating film 19.
3 and the floating gate electrode 2 in the Si substrate 11
An N-type source diffusion layer 17 and a drain diffusion layer 18 are formed in regions located on both sides of 0. The implantation conditions are, for example, an acceleration energy of 70 keV and a dose of 5 × 10 5
¹⁵ cm ^-2 . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
In the step shown in (c), the side surface of the floating gate electrode 20 is
Since the floating gate electrode 20 and the control gate electrode 22 are covered with the D insulating film 19, the penetration of phosphorus ions at the ends of the floating gate electrode 20 and the control gate electrode 22 can be suppressed. Therefore, a nonvolatile semiconductor memory device having the gate oxide film 12 and the interlayer insulating film 21 having high insulation and reliability can be obtained, and the number of times of rewriting of the nonvolatile semiconductor memory device and various disturbance characteristics can be improved. realizable.

Further, the CVD formed by the CVD method
Since the growth of the insulating film is performed at a low temperature of 800 ° C. or less, the floating gate electrode 20 in the gate oxide film 12 is formed as in the case of forming a thick protective oxide film by thermal oxidation.
The gate length can be accurately controlled without increasing the thickness (bird's beak) of a region (a portion actually functioning as a gate insulating film) located below the gate electrode. Therefore, it is advantageous for miniaturization of a semiconductor device. In addition, since the thickening (bird's beak) at the end of the interlayer insulating film 21 made of the ONO film can be suppressed, variation in element characteristics due to local stress being applied to the end of the interlayer insulating film is also reduced. Can be prevented.

Further, since the CVD process is performed at a lower temperature condition than the thermal oxidation process, the floating gate electrode 2
An impurity such as phosphorus doped with 0 is formed below the floating gate electrode 20 from the gate oxide film 12 or the Si substrate 11.
Can be suppressed.

Further, by covering the floating gate electrode 20 and the control gate electrode 22 with the CVD insulating film 19, the diffusion of impurities in the floating gate electrode 20 and the control gate electrode 22 to the outside can be prevented. Therefore, it is possible to obtain a non-volatile semiconductor memory device with less variation in characteristics.

In addition, the floating gate electrode 20 has a high quality CV
Since the semiconductor device is covered with the D insulating film 19, a nonvolatile semiconductor memory device having excellent charge retention characteristics can be obtained.

Before or after the step of implanting phosphorus ions 23 shown in FIG. 4C of this embodiment, B (boron) for forming a P-type diffusion layer serving as a threshold control layer or a punch-through stopper is formed. Ions or BF ₂ ions are passed through the CVD insulating film 19 and the gate oxide film 12 so that the Si substrate 11
You may inject into. In that case, it is apparent that the same effects as those of the present embodiment can be obtained.

(Fourth Embodiment) Next, a fourth embodiment will be described. FIG.
FIG. 3C is a cross-sectional view illustrating a step of manufacturing the semiconductor device functioning as the nonvolatile semiconductor memory device according to the embodiment. 5A to 5C, reference numeral 11 denotes a Si substrate, 1
2 is a gate oxide film, 17 is a source diffusion layer, 18 is a drain diffusion layer, 19 is a CVD insulating film made of a silicon oxide film deposited by a CVD method, 20 is a floating gate electrode, 2
Reference numeral 1 denotes an interlayer insulating film, 22 denotes a control gate electrode, and 23 denotes phosphorus ions as impurity ions implanted into the Si substrate 11 to form a source diffusion layer and a drain diffusion layer.

First, in the step shown in FIG. 5A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon, and then phosphorus-doped thereon. A floating gate electrode 20 made of polysilicon, an interlayer insulating film 21 made of an ONO film (a three-layer film having an oxide film provided above and below a nitride film), and a control gate electrode 22 made of polysilicon doped with phosphorus. I do.

Next, in a step shown in FIG. 5B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 10 nm is deposited on the substrate by a low pressure CVD method, and a gate oxide film 12 is formed.
And a multilayer body composed of the floating gate electrode 20, the interlayer insulating film and the control gate electrode 22 are covered with a CVD insulating film. Subsequently, anisotropic etching is performed to form a CVD insulating film 19 excluding portions on the side surfaces of the floating gate electrode 20, the interlayer insulating film 21, and the control gate electrode 22, and a gate oxide excluding a portion below the floating gate electrode 20. The film 12 is removed.

Thereafter, in the step shown in FIG.
Insulating film 19, control gate electrode 22, floating gate electrode 20
Phosphorus ions 23 are implanted into the Si substrate 11 from above or the like, and N-type source diffusion layers 17 and drain diffusion layers 18 are formed in regions located on both sides of the floating gate electrode 20 in the Si substrate 11. The implantation conditions include, for example, an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁵ cm ^−2.
It is. In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
In the step shown in (c), the side surface of the floating gate electrode 20 is
Since it is covered with the D insulating film 19, the phosphorus ions 23 implanted into the Si substrate 11 to form the source diffusion layer 17 and the drain diffusion layer 18 cause the floating gate electrode 20 at the end of the floating gate electrode 20. Penetration to the gate oxide film 12 is suppressed. Further, similarly to the third embodiment, in the step of forming the CVD insulating film 19, the end portion of the gate oxide film 12 is not thickened (bird's beak) unlike the thermal oxidation step. Can be controlled accurately. Therefore, it is advantageous for miniaturization of a semiconductor device. Also, an interlayer insulating film 21 made of an ONO film
(Bird's beak) can also be suppressed at the end of the device, so that it is possible to prevent variations in device characteristics due to local stress being applied to the end of the interlayer insulating film. Therefore, the same effect as in the fourth embodiment can be obtained.

By performing the coating of the CVD insulating film and the implantation of phosphorus ions twice or more while sequentially increasing the impurity ion concentration, a source / drain structure having a gentle impurity concentration gradient can be obtained. A nonvolatile semiconductor memory device having improved electrical characteristics can be realized.

Before or after the step of implanting the phosphorus ions 23 shown in FIG. 5C of this embodiment, B (boron) for forming a threshold control layer or a P-type diffusion layer serving as a punch-through stopper is formed. Ions or BF ₂ ions may be implanted into the Si substrate 11 from above the CVD insulating film 19 and the gate oxide film 12. In that case, it is apparent that the same effects as those of the present embodiment can be obtained.

-Proper Range of Thickness of CVD Insulating Film-Next, the proper range of the thickness of the CVD insulating film 19 in the third and fourth embodiments will be described.

Also in the third and fourth embodiments, the CV
The appropriate range of the D insulating film is the same as the appropriate range of the CVD insulating film in the above-described first and second embodiments. That is, from the dependence of the leak characteristics of the gate oxide film on the thickness of the CVD insulating film (see FIG. 3), the effect of reducing the damage to the gate oxide film due to ion implantation when the CVD insulating film is 5 nm or more. Is large. However, as the thickness of the CVD insulating film increases, the effect of reducing the damage becomes more remarkable. However, in order to allow the LDD diffusion layer and the gate electrode to overlap within an appropriate range without excessive heat treatment, the CVD insulating film is required. Is preferably 30 nm or less.

In the third and fourth embodiments, the CVD insulating film 19 is made of a silicon oxide film. However, the CVD insulating film 19 may be made of a silicon nitride film. When the CVD film 19 is formed of a silicon oxide film, there is an advantage that stress applied to a base is smaller than that of a silicon nitride film. On the other hand, when the CVD insulating film 19 is formed of a silicon nitride film, the generation of bird's beaks in the gate oxide film 12 and the interlayer insulating film 21 is more effectively performed in a subsequent step performed at a high temperature (such as an impurity diffusion step). There is an advantage that can be suppressed. This is the same in an embodiment relating to a nonvolatile semiconductor memory device described later.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. FIG.
1 is a sectional view of a semiconductor device functioning as a MOSFET according to the present embodiment. In the figure, 11 is a Si substrate made of P-type silicon, 12 is a gate oxide film made of a silicon oxide film, 13 is a gate electrode made of polysilicon,
15a and 15b are N-type LDD diffusion layers, 16a and 16b are sidewall spacers made of a TEOS film, 17 is an N-type source diffusion layer, 18 is an N-type drain diffusion layer, and 19 is silicon formed by a CVD method. This is a CVD insulating film made of an oxide film.

The feature of the semiconductor device according to the present embodiment is that the gate oxide film 12 is formed only immediately below the gate electrode 13, and the side wall spacers 16 a and 16 b are formed on the side surfaces of the gate oxide film 12 and the gate electrode 13. This is the point formed over. In such a structure, the gate oxide film 12 is patterned into the same shape as the gate electrode 13 in the step shown in FIG. 2A in the second embodiment, and thereafter, FIGS. This can be easily realized by performing the steps according to the same procedure as in the above).

In the semiconductor device according to the present embodiment,
As in the semiconductor device according to the second embodiment, LDD
During the implantation of the impurity ions for forming the diffusion layers 15a and 15b, the deterioration of the insulating property of the gate oxide film 12 due to the penetration of the impurity ions at the end of the gate electrode 13 can be suppressed. A semiconductor device having a gate oxide film can be obtained, and high reliability of the semiconductor device can be realized.

Further, the gate electrode 13 is formed of the CVD insulating film 1.
9, the impurity contained in the gate electrode 13 can be prevented from diffusing laterally or upward, and a semiconductor device with less variation in characteristics can be obtained.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described. FIG.
1 is a cross-sectional view of a semiconductor device functioning as a nonvolatile semiconductor memory device according to an embodiment. In the figure, 11 is a Si substrate made of P-type silicon, 12 is a gate oxide film made of a silicon oxide film, 17 is an N-type source diffusion layer, 1
8 is an N-type drain diffusion layer, 19 is a CVD insulating film made of a silicon oxide film formed by a CVD method, 20 is a floating gate electrode made of polysilicon, 21 is an ONO film (an oxide film is provided above and below a nitride film). And a control gate electrode 22 made of polysilicon.

A feature of the semiconductor device according to the present embodiment is that the gate oxide film 12 is formed only immediately below the floating gate electrode 20 and the sidewall spacers 16a and 16b
Are formed over the side surfaces of the control gate electrode 22, the interlayer insulating film 21, the floating gate electrode 20, and the gate oxide film 12. Such a structure is obtained by forming the gate oxide film 12 in the step shown in FIG.
Is patterned in the same shape as the control gate electrode 22, the interlayer insulating film 21, and the floating gate electrode 20, and then
It can be easily realized by performing the steps in the same procedure as in FIGS. 5B to 5C.

In the semiconductor device functioning as the nonvolatile semiconductor memory device according to the present embodiment, as in the semiconductor device according to the fourth embodiment, the source / drain diffusion layers 1
During the implantation of the impurity ions for forming the gate electrodes 7 and 18, the deterioration of the insulating property of the gate oxide film due to the penetration of the impurity ions at the end of the floating gate electrode 20 can be suppressed. Therefore, it is possible to obtain a nonvolatile semiconductor memory device provided with a gate oxide film having high insulation and reliability, and to improve the number of times of rewriting of the nonvolatile semiconductor memory device and various disturbance characteristics.

Further, since the floating gate electrode 20 is covered with the CVD insulating film 19, the floating gate electrode 20
Can be prevented from diffusing to the outside, and a non-volatile semiconductor memory device with less variation in characteristics can be obtained.

The floating gate electrode 20 is made of high quality CVD.
Since the semiconductor device is covered with the insulating film 19, a nonvolatile semiconductor memory device having excellent charge retention characteristics can be obtained.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described. FIG.
4A to 4F are cross-sectional views illustrating a process of manufacturing a semiconductor device functioning as a MOSFET according to the embodiment.

8A to 8F, reference numeral 11 denotes Si.
A substrate, 12 a gate oxide film, 13 a gate electrode, 14 arsenic ions as impurity ions implanted into the Si substrate 11 to form an LDD diffusion layer, 15a and 1
5b is an LDD diffusion layer, 16a and 16b are side wall spacers, 17 is a source diffusion layer, 18 is a drain diffusion layer, 19 is a CVD insulating film made of a silicon oxide film deposited by a CVD method, and 30 is a thermal oxide film. .

First, in a step shown in FIG. 8A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation. A gate electrode 13 made of polysilicon doped with phosphorus is formed.

Next, in a step shown in FIG. 8B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 15 nm is deposited on the substrate by a low pressure CVD method, and the gate oxide film 12 and the gate electrode 13 are formed by CVD. It is covered with an insulating film 19.

Next, in the step shown in FIG. 8C, the Si substrate 11 is placed from above the gate electrode 13 and the CVD insulating film 19.
Arsenic ions 14 are implanted into the substrate, and N-type LDDs are
The diffusion layers 15a and 15b are formed. The implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁴ c.
m- ² . In order to overlap the LDD diffusion layers 15a and 15b with the gate electrode 13, the ion implantation angle is inclined by about 25 ° from a direction substantially perpendicular to the substrate surface (four-step implantation).

Next, in the step shown in FIG.
In the oxygen atmosphere, rapid heat treatment for recovering damage in the gate oxide film 12 is performed. By this processing, the Si substrate 11 and the gate electrode 13 are thermally oxidized, and a thermal oxide film 30 having a thickness of about 5 nm is formed. At this time, the region of the gate oxide film 12 except for the region located below the gate electrode 13 (the region actually functioning as a gate insulating film) is slightly thickened. Since the thickened region penetrates below the gate electrode 13, small bird's beaks are formed at both ends of the region of the gate oxide film 12 which actually functions as a gate insulating film.

Next, in the step shown in FIG. 8E, after a TEOS film is deposited on the substrate, anisotropic etching is performed, and a TEOS film is formed on the side surface of the gate electrode 13 with the CVD insulating film 19 interposed therebetween. Sidewall spacers 16a,
16b is formed. In this step, the gate oxide film 12, the thermal oxide film 30, and the CVD insulating film 19 on the Si substrate 11 are removed.

Thereafter, in the step shown in FIG. 8F, the gate electrode 13, the CVD insulating film 19, the thermal oxide films 30a and 30b
Arsenic ions are implanted into the Si substrate 11 from above the sidewall spacers 16a and 16b to form N-type source diffusion layers 17 and drain diffusion layers 18 outside the LDD diffusion layers 15a and 15b, respectively. The ion implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
By covering the side surface of the gate electrode 13 with the CVD insulating film 19 in the step shown in FIG. 2B, the same effect as in the first embodiment can be exerted. That is,
Since the action of the arsenic ions 14 penetrating the end of the gate electrode 13 in the step shown in FIG. 8C can be suppressed, damage in the gate oxide film 12 can be suppressed. In addition, since a long-time, high-temperature heat treatment for forming a protective film is not performed, and the presence of the CVD insulating film 19, a large bird's beak occurs in a region of the gate oxide film 12 that functions as a gate insulating film. Outward diffusion of impurities such as phosphorus doped in the gate electrode 13 can be suppressed.

In addition, in the step shown in FIG. 8D, heat treatment in an oxidizing atmosphere is performed to re-oxidize the gate oxide film 12 which has been damaged due to the implantation of the arsenic ions 14 and has deteriorated insulative properties. Insulation can be restored. That is, by the CVD insulating film 19, FIG.
Although the penetration of the arsenic ions 14 through the gate electrode 13 in the step shown in FIG. 1 can be suppressed, it is difficult to completely eliminate the penetration. At this time, by performing thermal oxidation, it is considered that a repair operation for recombining the damage in the gate oxide film 12, specifically, recombining the oxygen with the portion of the silicon atom where the bond with oxygen is broken is performed. It is. As described above, by adding the step of recovering the damage of the gate oxide film 12, the gate oxide film 12 can exhibit higher reliability than the first and second embodiments.
Can be obtained.

In this case, unlike the step of forming a thermal oxide film as a protective film, the thermal oxidation step in the step shown in FIG. 8D is light for the purpose of only recovering the damage in the gate oxide film 12. In this case, a very large bird's beak is not formed in the gate oxide film 12 at that time. Therefore, it is possible to avoid variations in device characteristics and deterioration in device characteristics due to variations in gate length as in the conventional manufacturing method.

In particular, since heat treatment in an oxynitriding atmosphere is performed by rapid heat treatment, the amount of heat treatment can be suppressed to a minimum, so that there is little variation in characteristics, and it is advantageous for miniaturization.

The heat treatment step in the oxidizing atmosphere shown in FIG. 8D can be performed not only to restore the insulating property of the gate oxide film 12, but also to anneal the LDD diffusion layers 15a and 15b.

Further, before and after the step shown in FIG.
Phosphorus ions for improving the breakdown voltage of the drain diffusion layer,
Boron ion and BF for punch-through stop
_{Even when two} ions are implanted, the same effect as in the present embodiment can be obtained.

(Eighth Embodiment) Next, an eighth embodiment of the present invention will be described. FIG.
4A to 4F are cross-sectional views illustrating a process of manufacturing a semiconductor device functioning as a MOSFET according to the embodiment.

In FIGS. 9A to 9F, reference numeral 11 denotes Si.
A substrate, 12 a gate oxide film, 13 a gate electrode, 14 arsenic ions as impurity ions implanted into the Si substrate 11 to form an LDD diffusion layer, 15a and 1
5b is an LDD diffusion layer, 16a and 16b are side wall spacers, 17 is a source diffusion layer, 18 is a drain diffusion layer, 19 is a CVD insulating film made of a silicon oxide film deposited by a CVD method, and 31 is an oxynitride film. .

First, in the step shown in FIG. 9A, a gate oxide film 12 made of a 9-nm-thick silicon oxide film is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation, A gate electrode 13 made of polysilicon doped with phosphorus is formed.

Next, in a step shown in FIG. 9B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 15 nm is deposited on the substrate by a low pressure CVD method, and the gate oxide film 12 and the gate electrode 13 are formed by CVD. It is covered with an insulating film 19.

Next, in the step shown in FIG. 9C, the Si substrate 11 is placed from above the gate electrode 13 and the CVD insulating film 19.
Arsenic ions 14 are implanted into the substrate, and N-type LDDs are
The diffusion layers 15a and 15b are formed. The implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁴ c.
m- ² . In order to overlap the LDD diffusion layers 15a and 15b with the gate electrode 13, the ion implantation angle is inclined by about 25 ° from a direction substantially perpendicular to the substrate surface (four-step implantation).

Next, in the step shown in FIG. 9D, a rapid heating process for recovering damage in the gate oxide film 12 is performed under the conditions of N ₂ O atmosphere (oxynitriding atmosphere) and 1000 ° C. . By this processing, the Si substrate 11 and the gate electrode 13 are oxynitrided, and an extremely thin oxynitride film 31 having a thickness of about 3 nm is formed. At this time, the region of the gate oxide film 12 except for the region located below the gate electrode 13 (the region actually functioning as a gate insulating film) is slightly thickened. Since the thickened region penetrates below the gate electrode 13, very small bird's beaks are formed at both ends of the region of the gate oxide film 12 which actually functions as a gate insulating film.

Next, in the step shown in FIG. 9E, after a TEOS film is deposited on the substrate, anisotropic etching is performed to form a TEOS film on the side surface of the gate electrode 13 via the CVD insulating film 19 from the TEOS film. Sidewall spacers 16a, 1
6b is formed.

Thereafter, in the step shown in FIG. 9F, arsenic ions are implanted into the Si substrate 11 from above the gate electrode 13, the CVD insulating film 19, and the sidewall spacers 16a and 16b, thereby forming the LDD diffusion layer 15a. , 15b, an N-type source diffusion layer 17 and a drain diffusion layer 18 are formed respectively. The ion implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
By covering the side surface of the gate electrode 13 with the CVD insulating film 19 in the step shown in FIG. 2B, the same effect as in the seventh embodiment can be exerted. That is,
Since the action of the arsenic ions 14 penetrating the end of the gate electrode 13 in the step shown in FIG. 9C can be suppressed, damage to the gate oxide film 12 can be suppressed. Also,
By not performing a long-time, high-temperature heat treatment for forming the protective film, or by the presence of the CVD insulating film 19, a large bird's beak is generated and impurities such as phosphorus doped in the gate electrode 13 are not directed outward. Diffusion can be suppressed.

In addition, in the step shown in FIG. 9D, a heat treatment in an oxynitriding atmosphere is performed to reoxidize the gate oxide film 12 which has been damaged by the implantation of the arsenic ions 14 and has deteriorated insulation. To restore the insulation. Further, since the gate oxide film 12 is nitrided at this time, the dangling bond existing between the Si substrate 11 and the gate oxide film 12 is repaired. Therefore, the characteristic deterioration of the gate oxide film 12 after the application of the electric stress can be reduced, and the amount of trapped electrons in the gate oxide film 12 can be reduced. As a result, a semiconductor device having a gate oxide film with extremely high reliability can be obtained, and high reliability of the semiconductor device can be realized.

Further, since the heat treatment in the oxynitriding atmosphere is performed by rapid heat treatment, the amount of heat treatment can be suppressed to a minimum, so that there is little variation in characteristics and it is advantageous for miniaturization.

Moreover, since the oxynitriding step in the step shown in FIG. 9D is performed by a rapid heating process, the bird's beak formed on the gate oxide film 12 can be kept to a very small extent. Therefore, it is possible to avoid the variation of the device characteristics and the deterioration of the device characteristics due to the variation of the gate length as in the conventional manufacturing method.
This is a manufacturing process more suitable for miniaturization of the SFET.

The heat treatment step in the oxynitriding atmosphere shown in FIG. 9D can be performed not only to restore the insulating property of the gate oxide film 12, but also to anneal the LDD diffusion layers 15a and 15b. .

Further, before and after the step shown in FIG.
Phosphorus ions for improving the breakdown voltage of the drain diffusion layer,
Boron ion and BF for punch-through stop
_{Even when two} ions are implanted, the same effect as in the present embodiment can be obtained.

(Ninth Embodiment) Next, a ninth embodiment of the present invention will be described. FIG.
0 (a) to (f) are cross-sectional views illustrating a manufacturing process of a semiconductor device functioning as a MOSFET according to the present embodiment.

In FIGS. 10A to 10F, reference numeral 11 denotes S
i substrate, 12 a gate oxide film, 13 a gate electrode, 14
Is arsenic ions as impurity ions implanted into the Si substrate 11 to form an LDD diffusion layer; 15a and 15b are LDD diffusion layers; 16a and 16b are sidewall spacers; 17 is a source diffusion layer; and 18 is a drain diffusion The layer 19 is a CVD insulating film made of a silicon oxide film deposited by a CVD method.

First, in a step shown in FIG. 10A, a gate oxide film 12 made of a 9 nm-thick silicon oxide film is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation.
Is formed, a gate electrode 13 made of phosphorus-doped polysilicon is formed thereon.

Next, in a step shown in FIG. 10B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 25 nm is deposited on the substrate by a low pressure CVD method, and a gate oxide film 12 is formed.
And the gate electrode 13 is covered with a CVD insulating film 19.

Next, in the step shown in FIG. 10C, the Si substrate 1 is placed from above the gate electrode 13 and the CVD insulating film 19.
Arsenic ions 14 are implanted into the silicon substrate 1 and N-type LDs are
D diffusion layers 15a and 15b are formed. The implantation conditions include, for example, an acceleration energy of 50 keV and a dose of 5 × 10 ^14.
cm ^-2 . In order to overlap the LDD diffusion layers 15a and 15b with the gate electrode 13, the ion implantation angle is inclined by about 25 ° from a direction substantially perpendicular to the substrate surface (four-step implantation).

Next, in the step shown in FIG. 10D, a rapid heating process is performed in a nitriding atmosphere containing, for example, NO, NH _{3 and the} like at 1050 ° C. By this process, both ends of a region (a region actually functioning as a gate insulating film) of the gate oxide film 12 located below the gate electrode 13 are nitrided. However, the oxide film 30 and the oxynitride film 31 are not formed as in the seventh and eighth embodiments. No bird's beak is formed on the gate oxide film 12.

Next, in the step shown in FIG. 10E, after a TEOS film is deposited on the substrate, anisotropic etching is performed to form a TEOS film on the side surface of the gate electrode 13 with the CVD insulating film 19 interposed therebetween. Sidewall spacers 16a, 1
6b is formed.

Thereafter, in the step shown in FIG. 10F, arsenic ions are implanted into the Si substrate 11 from above the gate electrode 13, the CVD insulating film 19, and the sidewall spacers 16a and 16b, thereby forming the LDD diffusion layer 15a. , 15b, an N-type source diffusion layer 17 and a drain diffusion layer 18 are formed respectively. The ion implantation conditions are, for example, an acceleration energy of 50 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

According to the manufacturing method of this embodiment, FIG.
By covering the side surface of the gate electrode 13 with the CVD insulating film 19 in the step shown in FIG. 2B, the same effect as in the seventh embodiment can be exerted. That is,
Arsenic ions 14 in the step shown in FIG. 10C can suppress damage to the gate electrode 13. In addition, since a long-time, high-temperature heat treatment for forming a protective film is not performed and the presence of the CVD insulating film 19, a large bird's beak is generated and impurities such as phosphorus doped in the gate electrode 13 are removed. Can be suppressed.

In addition, in the step shown in FIG. 10D, by performing a heat treatment in a nitriding atmosphere, both ends of the gate oxide film 12 are nitrided. Dangling bonds are repaired. Therefore, the characteristic deterioration of the gate oxide film 12 after the application of the electric stress is reduced, and the gate oxide film 1
2, the amount of trapped electrons can be reduced.
As a result, a MOSFET provided with a gate oxide film having extremely high reliability can be obtained, and high reliability of the MOSFET can be realized.

Further, since heat treatment in a nitriding atmosphere is performed by rapid heat treatment, the amount of heat treatment can be minimized.
There is little variation in OSFET characteristics, and
It is also advantageous for miniaturization of ET.

Further, no bird's beak is formed in the gate oxide film 12 in the nitriding step in the step shown in FIG. Therefore, variations in device characteristics due to variations in gate length as in the conventional manufacturing method can be avoided, and the manufacturing process is more suitable for miniaturizing MOSFETs.

The heat treatment step in the nitriding atmosphere shown in FIG. 10D can be performed also for annealing the LDD diffusion layers 15a and 15b.

Further, before or after the step shown in FIG. 10C, even when phosphorus ions for improving the breakdown voltage of the drain diffusion layer, boron ions or BF ₂ ions for the purpose of punch-through stop are implanted. The same effects as those of the present embodiment can be obtained.

(Tenth Embodiment) Next, a tenth embodiment of the present invention will be described. FIGS. 11A to 11D are cross-sectional views illustrating manufacturing steps of a semiconductor device functioning as the nonvolatile semiconductor memory device according to the embodiment. 11A to 11D, 11 is a Si substrate, 12 is a gate oxide film, 17 is a source diffusion layer,
18 is a drain diffusion layer, 19 is an insulating film deposited by a CVD method, 20 is a floating gate electrode, 21 is an interlayer insulating film,
22, a control gate electrode; 23, phosphorus ions as impurity ions implanted into the Si substrate 11 to form a source diffusion layer and a drain diffusion layer; and 30, a thermal oxide film.

First, in the step shown in FIG. 11A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon by pyro oxidation.
Is formed thereon, a floating gate electrode 20 made of phosphorus-doped polysilicon, and an interlayer insulating film 2 made of an ONO film (a three-layer film formed by providing an oxide film above and below a nitride film).
A control gate electrode 22 made of 1, and phosphorus-doped polysilicon is sequentially formed.

Next, in a step shown in FIG. 11B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 20 nm is deposited on the substrate by a low pressure CVD method, and a gate oxide film 12 is formed.
And a multilayer body composed of the floating gate electrode 20, the interlayer insulating film 21, and the control gate electrode 22 are covered with a CVD insulating film.

Next, in the step shown in FIG.
Phosphorus ions 2 are introduced into the Si substrate 11 from above the control gate electrode 22 and the floating gate electrode 20 covered with the insulating film 19.
3 and the floating gate electrode 2 in the Si substrate 11
An N-type source diffusion layer 17 and a drain diffusion layer 18 are formed in regions located on both sides of 0. The implantation conditions are, for example, an acceleration energy of 70 keV and a dose of 5 × 10 5
¹⁵ cm ^-2 . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

Next, in the step shown in FIG.
Heat treatment for recovering damage to the gate oxide film 12 is performed in an oxygen atmosphere at a temperature of ° C. By this processing, Si
Substrate 11, control gate electrode 22, and floating gate electrode 2
0 is thermally oxidized to form a thermal oxide film 30 having a thickness of about 8 nm. At this time, a region of the gate oxide film 12 except for a region located below the floating gate electrode 20 (a region actually functioning as a gate insulating film) is slightly thickened.
Since the thickened region penetrates below the floating gate electrode 20, small bird's beaks are formed at both ends of the region of the gate oxide film 12 which actually functions as a gate insulating film. Similarly, both ends of the upper and lower oxide films sandwiching the nitride film in the interlayer insulating film 21 are slightly thickened, so that a small bird's beak is formed in the interlayer insulating film 21.

According to the manufacturing method of this embodiment, FIG.
By covering the side surfaces of the control gate electrode 22 and the floating gate electrode 20 with the CVD insulating film 19 in the step shown in FIG. 2B, the same effect as in the third embodiment can be exerted. That is, the action of the arsenic ions 14 penetrating through the end of the floating gate electrode 20 and the end of the control gate electrode 22 in the step shown in FIG. 11C can be suppressed, so that damage to the gate oxide film 12 and the interlayer insulating film 21 can be reduced. Can be suppressed. In addition, since a long-time, high-temperature heat treatment for forming the protective film is not performed and the presence of the CVD insulating film 19, a large bird's beak is generated and impurities such as phosphorus doped in the gate electrodes 22 and 20 are doped. Can be suppressed from spreading outward.

In addition, by performing a heat treatment in an oxidizing atmosphere in the step shown in FIG. 11D, the gate oxide film 12 and the interlayer insulating film 21 whose insulating properties have been deteriorated due to the damage caused by the implantation of the arsenic ions 14. Can be reoxidized to restore insulation. That is, the CVD insulating film 19
As a result, the arsenic ion 1 in the step shown in FIG.
Although the penetration of each of the gate electrodes 22 and 20 of No. 4 can be suppressed, it is difficult to completely eliminate the penetration. At this time, by performing thermal oxidation, a repair work such as damage in the gate oxide film 12 or the interlayer insulating film 21, more specifically, a repair operation of recombining oxygen with a portion of the silicon atom that has been disconnected from oxygen is cut off. It seems to be done. As described above, by adding the step of recovering the damage of the gate oxide film 12 by performing the thermal oxidation, the number of rewrites of the nonvolatile semiconductor memory device and the various disturbance characteristics can be improved.

In this case, unlike the step of forming a thermal oxide film as a protective film, the thermal oxidation step in the step shown in FIG. 11D recovers damage in the gate oxide film 12 and the interlayer insulating film 21. In this case, a large bird's beak is not formed in the gate oxide film 12 or the interlayer insulating film 21. Therefore, variations in threshold voltage due to variations in gate length and variations in device characteristics due to application of local stress to both ends of the interlayer insulating film 21 as in the conventional manufacturing method can be avoided. .

Further, since heat treatment in an oxidizing atmosphere is performed by rapid heat treatment, the amount of heat treatment can be minimized. As a result, variations in the characteristics of the nonvolatile semiconductor memory device are small, and miniaturization of the nonvolatile semiconductor memory device is required. Is also advantageous.

In addition, the floating gate electrode 20 has a high quality CV
Since the semiconductor device is covered with the D insulating film 19, a nonvolatile semiconductor memory device having excellent charge retention characteristics can be obtained.

Before and after the step of implanting phosphorus ions 23 shown in FIG. 11C of this embodiment, arsenic ions for increasing the surface concentration and facilitating the extraction of electrons, a threshold control layer or a punch-through stopper B (boron) ions or BF ₂ ions for forming a P-type diffusion layer to pass through the CVD insulating film 19 and the gate oxide film 12 to form S
It may be implanted into the i-substrate 11. Even in that case,
It is clear that the same effects as in the present embodiment can be obtained.

FIG. 14 is data showing the rewrite durability characteristics of the nonvolatile semiconductor memory devices manufactured by the manufacturing methods of the third and tenth embodiments, respectively. In the figure, the horizontal axis represents the number of times of rewriting, and the vertical axis represents the threshold voltage (V). Vt1 indicates a threshold voltage when electrons are injected into the floating gate electrode 20, and Vto indicates a threshold voltage when electrons are extracted from the floating gate electrode 20, respectively. In the same figure, the mark x indicates the threshold voltage of the nonvolatile semiconductor memory device manufactured by the manufacturing method of the third embodiment, and the mark ● in the figure indicates the manufacturing method of the nonvolatile semiconductor memory device of the tenth embodiment. The respective threshold voltages of the nonvolatile semiconductor memory device are shown.
Also in the semiconductor memory device manufactured by the manufacturing method of the third embodiment, the variation is smaller than the threshold voltage (not shown) of the nonvolatile semiconductor memory device manufactured by the above-described conventional manufacturing method. In addition, it has been confirmed that the rise of the threshold voltage in the electron extraction state is small. However, it is shown that the increase in the threshold voltage in the electron withdrawal state of the nonvolatile semiconductor memory device manufactured by the manufacturing method of the tenth embodiment is extremely small.
That is, according to the manufacturing method of the present embodiment, the effect of improving the number of times of rewriting of the nonvolatile semiconductor memory device and the effect of improving various disturbance characteristics are remarkably obtained.

(Eleventh Embodiment) Next, an eleventh embodiment of the present invention will be described. FIGS. 12A to 12D are cross-sectional views illustrating a manufacturing process of the semiconductor device functioning as the nonvolatile semiconductor memory device according to the present embodiment. 12A to 12D, 11 is a Si substrate, 12 is a gate oxide film, 17 is a source diffusion layer,
18 is a drain diffusion layer, 19 is an insulating film deposited by a CVD method, 20 is a floating gate electrode, 21 is an interlayer insulating film,
Reference numeral 22 denotes a control gate electrode, 23 denotes phosphorus ions as impurity ions implanted into the Si substrate 11 to form a source diffusion layer and a drain diffusion layer, and 31 denotes an oxynitride film.

First, in a step shown in FIG. 12A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation.
Is formed thereon, a floating gate electrode 20 made of phosphorus-doped polysilicon, and an interlayer insulating film 2 made of an ONO film (a three-layer film formed by providing an oxide film above and below a nitride film).
A control gate electrode 22 made of 1, and phosphorus-doped polysilicon is sequentially formed.

Next, in a step shown in FIG. 12B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 20 nm is deposited on the substrate by a low pressure CVD method, and a gate oxide film 12 is formed.
And a multilayer body composed of the floating gate electrode 20, the interlayer insulating film 21, and the control gate electrode 22 are covered with a CVD insulating film.

Next, in the step shown in FIG.
Phosphorus ions 2 are introduced into the Si substrate 11 from above the control gate electrode 22 and the floating gate electrode 20 covered with the insulating film 19.
3 and the floating gate electrode 2 in the Si substrate 11
An N-type source diffusion layer 17 and a drain diffusion layer 18 are formed in regions located on both sides of 0. The implantation conditions are, for example, an acceleration energy of 70 keV and a dose of 5 × 10 5
¹⁵ cm ^-2 . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

[0133] Next, in the step shown in FIG. 12 (d), N ₂ O
Is performed under an oxynitriding atmosphere containing 1000 ° C. at a temperature of 1000 ° C. to recover damage to the gate oxide film 12.
By this processing, the Si substrate 11, the control gate electrode 22
And the thickness of the floating gate electrode 20 is about 3
An oxynitride film 31 of nm is formed. At this time, the region of the gate oxide film 12 except for the region located below the floating gate electrode 20 (the region that actually functions as a gate oxide film) is slightly thickened. Also, this thickened area is
Since it penetrates below the floating gate electrode 20, slightly small bird's beaks are formed at both ends of a region of the gate oxide film 12 which actually functions as a gate insulating film. Similarly, both ends of the upper and lower oxide films sandwiching the nitride film in the interlayer insulating film 21 are slightly thickened.
1 has a very small bird's beak.

According to the manufacturing method of this embodiment, FIG.
By covering the side surfaces of the control gate electrode 22 and the floating gate electrode 20 with the CVD insulating film 19 in the step shown in (b), the same effect as in the tenth embodiment can be exerted. That is, the action of arsenic ions 14 penetrating through the floating gate electrode 20 and the control gate electrode 22 in the step shown in FIG. 12C can be suppressed, so that damage in the gate oxide film 12 and the interlayer insulating film 21 can be suppressed. Further, since a long-time, high-temperature heat treatment for forming the protective film is not performed and the presence of the CVD insulating film 19, a large bird's beak is generated and each gate electrode 2
It is possible to suppress the diffusion of impurities such as phosphorus doped into the layers 2 and 20 to the outside.

In addition, in the step shown in FIG. 12D, heat treatment is performed in an oxynitriding atmosphere to regenerate the gate oxide film 12 which has been damaged by the implantation of the phosphorus ions 23 due to the recovery of the damage and has deteriorated insulative properties. It is possible to obtain an effect that the insulating property can be restored by oxidation, and an effect that the gate oxide film 12 is nitrided to reduce the characteristic deterioration after the application of the electric stress and reduce the amount of trapped electrons. As a result, a nonvolatile semiconductor memory device having the gate oxide film 12 with extremely high reliability can be obtained, and the number of times of rewriting of the nonvolatile semiconductor memory device and various disturbance characteristics can be improved.

In this case, the oxynitridation step in the step shown in FIG. 12D is different from the step of forming a thermal oxide film as a protective film to recover damage in the gate oxide film 12 and the interlayer insulating film 21. Is performed only for the purpose, and the oxidizing action is smaller than in the thermal oxidation step in the tenth embodiment.
Only very small bird's beaks are formed. Therefore, variations in threshold voltage due to variations in gate length and variations in device characteristics due to application of local stress to both ends of the interlayer insulating film 21 as in the conventional manufacturing method can be avoided. .

Further, since the heat treatment in the oxynitriding atmosphere is performed by rapid heat treatment, the amount of heat treatment can be minimized.
The characteristics of the non-volatile semiconductor memory device are less likely to vary, and it is advantageous for miniaturization of the non-volatile semiconductor memory device.

In addition, the floating gate electrode 20 has a high quality CV
Since the semiconductor device is covered with the D insulating film 19, a nonvolatile semiconductor memory device having excellent charge retention characteristics can be obtained.

Furthermore, since the floating gate electrode 20 and the interlayer insulating film 21 are covered with the CVD insulating film 19, the diffusion of phosphorus doped in the floating gate electrode 20 to the outside can be prevented, so that the characteristics are improved. It is possible to obtain a non-volatile semiconductor memory device with little variation.

Before and after the step of implanting the phosphorus ions 23 shown in FIG. 12C of this embodiment, arsenic ions for increasing the surface concentration and facilitating the extraction of electrons, a threshold control layer or a punch-through stopper B (boron) ions or BF ₂ ions for forming a P-type diffusion layer to pass through the CVD insulating film 19 and the gate oxide film 12 to form S
It may be implanted into the i-substrate 11. Even in that case,
It is clear that the same effects as in the present embodiment can be obtained.

In this embodiment, the source diffusion layer 17
Although the step of implanting phosphorus ions 23 for the purpose of forming drain diffusion layer 18 is performed, it is apparent that the same effect as in the present embodiment can be obtained even when arsenic ions are implanted before or after that. .

(Twelfth Embodiment) Next, a twelfth embodiment of the present invention will be described. FIGS. 13A to 13D are cross-sectional views illustrating a manufacturing process of a semiconductor device functioning as the nonvolatile semiconductor memory device according to the present embodiment. 13A to 13D, 11 is a Si substrate, 12 is a gate oxide film, 17 is a source diffusion layer,
18 is a drain diffusion layer, 19 is an insulating film deposited by a CVD method, 20 is a floating gate electrode, 21 is an interlayer insulating film,
Reference numeral 22 denotes a control gate electrode, and reference numeral 23 denotes phosphorus ions as impurity ions implanted into the Si substrate 11 to form a source diffusion layer and a drain diffusion layer.

First, in the step shown in FIG. 13A, a gate oxide film 12 made of a silicon oxide film having a thickness of 9 nm is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation.
Is formed thereon, a floating gate electrode 20 made of phosphorus-doped polysilicon, and an interlayer insulating film 2 made of an ONO film (a three-layer film formed by providing an oxide film above and below a nitride film).
A control gate electrode 22 made of 1, and phosphorus-doped polysilicon is sequentially formed.

Next, in a step shown in FIG. 13B, a CVD insulating film 19 made of a silicon oxide film having a thickness of 30 nm is deposited on the substrate by a low pressure CVD method, and a gate oxide film 12 is formed.
And a multilayer body composed of the floating gate electrode 20, the interlayer insulating film 21, and the control gate electrode 22 are covered with a CVD insulating film.

Next, in the step shown in FIG.
Phosphorus ions 2 are introduced into the Si substrate 11 from above the control gate electrode 22 and the floating gate electrode 20 covered with the insulating film 19.
3 and the floating gate electrode 2 in the Si substrate 11
An N-type source diffusion layer 17 and a drain diffusion layer 18 are formed in regions located on both sides of 0. The implantation conditions are, for example, an acceleration energy of 70 keV and a dose of 5 × 10 5
¹⁵ cm ^-2 . In order to prevent channeling, the angle of ion implantation is inclined by about 7 ° from a direction substantially perpendicular to the substrate surface.

Next, in the step shown in FIG.
A rapid heating process is performed in a nitriding atmosphere containing NH ₃ or the like at 1050 ° C. At this time, the thermal oxide film 30 and the oxynitride film 31 as in the tenth and eleventh embodiments are not formed, and a bird's beak is not formed in the gate oxide film 12 and the interlayer insulating film 21.

According to the manufacturing method of this embodiment, FIG.
By covering the side surfaces of the control gate electrode 22 and the floating gate electrode 20 with the CVD insulating film 19 in the step shown in (b), the same effect as in the tenth embodiment can be exerted. That is, the action of arsenic ions 14 penetrating through the floating gate electrode 20 and the control gate electrode 22 in the step shown in FIG. 13C can be suppressed, so that damage in the gate oxide film 12 and the interlayer insulating film 21 can be suppressed. In addition, since a long-time, high-temperature heat treatment for forming a protective film is not performed and the presence of the CVD insulating film 19, bird's beaks are generated and the gate electrodes 22 and 20 are formed.
It is possible to suppress the diffusion of impurities such as phosphorus that is doped into the semiconductor substrate to the outside.

In addition, in the step shown in FIG. 13D, by performing a heat treatment in a nitriding atmosphere, the gate oxide film 12 is nitrided to reduce the characteristic deterioration after the application of the electric stress and to reduce the amount of trapped electrons. can do. As a result, a nonvolatile semiconductor memory device having the gate oxide film 12 with extremely high reliability can be obtained, and the number of times of rewriting of the nonvolatile semiconductor memory device and various disturbance characteristics can be improved.

Further, bird's beaks are not formed in the gate oxide film 12 and the interlayer insulating film 21 during the nitriding step in the step shown in FIG. Variations in threshold voltage due to variations and variations in device characteristics due to local application of stress to both ends of the interlayer insulating film 21 can be avoided.

In addition, since the heat treatment in the nitriding atmosphere is performed by rapid heat treatment, the amount of heat treatment can be minimized. As a result, the characteristics of the non-volatile semiconductor memory device have less variation and the non-volatile semiconductor memory device can be miniaturized. Is also advantageous.

In addition, the floating gate electrode 20 has a high quality CV
Since the semiconductor device is covered with the D insulating film 19, a nonvolatile semiconductor memory device having excellent charge retention characteristics can be obtained.

Further, since the floating gate electrode 20 and the interlayer insulating film 21 are covered with the CVD insulating film 19,
Since the diffusion of phosphorus doped in the floating gate electrode 20 to the outside can be prevented, a non-volatile semiconductor memory device with less variation in characteristics can be obtained.

Before and after the step of implanting phosphorus ions 23 shown in FIG. 13C of this embodiment, arsenic ions for increasing the surface concentration and facilitating extraction of electrons, a threshold control layer or a punch-through stopper B (boron) ions or BF ₂ ions for forming a P-type diffusion layer to pass through the CVD insulating film 19 and the gate oxide film 12 to form S
It may be implanted into the i-substrate 11. Even in that case,
It is clear that the same effects as in the present embodiment can be obtained.

-Conditions for Heat Treatment-The rapid heating in the oxidation step, oxynitridation step, and nitridation step in the seventh to twelfth embodiments is effective for preventing damage to the device while suppressing deterioration of device characteristics due to diffusion of impurities. To achieve the purpose, 800 to 1100 ° C is appropriate. Further, in order to suppress the formation of bird's beak, it is preferable to perform a short-time treatment within 120 seconds.

In the seventh to twelfth embodiments, C
Instead of the VD insulating film 19, a protective oxide film by thermal oxidation may be provided. In particular, since a thermal oxidation step or an oxynitridation step for removing damage is performed thereafter, even if the thickness of the protective oxide film formed by the first thermal oxidation is reduced,
Since the new oxide film 30 or oxynitride film 31 is formed in the thermal oxidation process or the oxynitridation process, the function of preventing diffusion of impurities can be ensured. Therefore, occurrence of bird's beak at both ends of the gate oxide film 12 and the interlayer insulating film 21 can be minimized.

[0156]

According to the method of manufacturing a semi-conductor device of the present invention, by coating the side surfaces of the gate electrode or floating gate electrode of the MOSFET on the insulating film formed by CVD, in order to form an LDD diffusion layer Can suppress the phenomenon that the impurity ions implanted into the semiconductor substrate penetrate through the gate electrode, so that the reliability of the gate insulating film is high, and
A method for manufacturing a semiconductor device which is excellent in controllability of a gate length and suitable for miniaturization can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a MOSFET according to a second embodiment of the present invention.

FIG. 3 is a characteristic diagram showing a dependency of a gate oxide film leakage characteristic on a thickness of a CVD insulating film (silicon oxide film) according to each embodiment of the present invention.

FIG. 4 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 5 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device functioning as a MOSFET according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device functioning as a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 8 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a MOSFET according to a seventh embodiment of the present invention.

FIG. 9 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a MOSFET according to an eighth embodiment of the present invention.

FIG. 10 shows a MOSFET according to a ninth embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing step of a semiconductor device functioning as a semiconductor device.

FIG. 11 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a nonvolatile semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 12 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a nonvolatile semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 13 is a sectional view illustrating a manufacturing process of a semiconductor device functioning as a nonvolatile semiconductor memory device according to a twelfth embodiment of the present invention.

FIG. 14 is data showing the rewriting endurance characteristics of the nonvolatile semiconductor memory devices manufactured by the manufacturing methods of the third and tenth embodiments in comparison with each other.

FIG. 15 is a cross-sectional view illustrating a manufacturing process of a semiconductor device functioning as a MOSFET according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Si substrate (semiconductor substrate) 12 Gate oxide film 13 Gate electrode 14 Arsenic ion 15a, 15b LDD diffusion layer 16a, 15b Side wall spacer 17 Source diffusion layer 18 Drain diffusion layer 19 CVD insulating film 20 Floating gate electrode 21 Interlayer insulating film 22 Control gate electrode 23 Phosphorus ion 24 Silicon oxide film 30 Thermal oxide film 31 Oxynitride film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/792 (72) Inventor Nobuyuki Tamura 1-1, Komachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Corporation (56) References JP-A-62-293776 (JP, A) JP-A-7-263682 (JP, A) JP-A-63-76377 (JP, A) JP-A-4-241425 (JP, A) JP-A-3 JP-157938 (JP, A) JP-A-6-13401 (JP, A) JP-A-3-1422841 (JP, A) JP-A-6-350093 (JP, A) JP-A-8-250609 (JP, A) JP-A-8-321607 (JP, A) JP-A-10-65028 (JP, A) JP-A-11-74525 (JP, A) JP-A-7-135255 (JP, A) JP-A-4- 211178 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/336 H01L 21/8247 H01L 27/115 H01L 29/78 H01L 2 9/788 H01L 29/792

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device that functions as a MOS field effect transistor, and the step (a) sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate, on the semiconductor substrate, 800 ° C. CVD of a silicon oxide film having a thickness of 5 nm or more and 30 nm or less covering the exposed surface of the gate electrode by the CVD method at the following temperature:
(B) forming an insulating film; and implanting impurity ions into the semiconductor substrate from above the gate electrode and the CVD insulating film to form a first conductivity type LDD diffusion layer in the semiconductor substrate. Forming a diffusion layer serving as a punch-through stopper of the second conductivity type in the semiconductor substrate by implanting impurity ions into the semiconductor substrate before and after the step (c); (D), after the steps (c) and (d), a sidewall spacer is formed on the side surface of the gate electrode with the CVD insulating film interposed therebetween, and the CVD on the semiconductor substrate is performed.
(E) removing an insulating film; and (f) forming a first conductivity type source / drain diffusion layer in the semiconductor substrate after the step (e). A method for manufacturing a semiconductor device, wherein the method is formed so as to overlap the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said gate insulating layer is formed by implanting said impurity ions after said steps (c) and (d) and before said step (e). A method for manufacturing a semiconductor device, further comprising a step of performing a heat treatment for recovering damage in a film in an atmosphere containing at least oxygen. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of performing the heat treatment is performed in an oxynitriding atmosphere. 4. A method of manufacturing a semiconductor device that functions as a MOS field effect transistor, and the step (a) sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate, on the semiconductor substrate, 800 ° C. CVD of a silicon oxide film having a thickness of 5 nm or more and 30 nm or less covering the exposed surface of the gate electrode by the CVD method at the following temperature:
(B) forming an insulating film; (c) performing anisotropic etching of the CVD insulating film to leave a side wall CVD insulating film on the side surface of the gate electrode; Forming a first conductivity type LDD diffusion layer in the semiconductor substrate by implanting impurity ions into the semiconductor substrate from above the CVD insulating film; and (d) before and after the step (d). (E) forming a diffusion layer serving as a punch-through stopper of the second conductivity type in the semiconductor substrate by implanting impurity ions into the semiconductor substrate; and ( d) forming a diffusion layer in the semiconductor substrate. Forming a side wall spacer on the side surface of the gate electrode with the side wall CVD insulating film interposed therebetween; and (f) after the step (f), forming a side wall spacer. And a step (g) forming source and drain diffusion layer of the first conductivity type in the body in a substrate, a semiconductor device in which the LDD diffusion layer is characterized in that it is formed so as to overlap with the gate electrode Manufacturing method.