JP2005191145A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent p-type dopants from entering a gate insulation film. <P>SOLUTION: A method of manufacturing a semiconductor device comprises processes of: forming the gate insulation film 103b and a gate electrode 104 in this order on a substrate 101; introducing nitrogen into the periphery of the gate insulation film 103b; forming a p-type dopant diffusion layer 105 at least in a region located in a lower part of the laminated structure of the substrate 101; and, after forming the p-type dopant diffusion layer 105, conducting a heat treatment. The thickness of the gate insulation film 103a is 2.4 nm or less. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a p-type transistor having a thin gate insulating film.

  In a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor structure, a silicon oxide film which is an oxide of silicon (= semiconductor) serving as a substrate has good insulating properties as a gate oxide film. Widely used in electronic devices. In order to improve the performance of this MOS transistor, it is effective to reduce the gate length of the transistor and thin the gate oxide film (scaling). In recent years, this scaling has been accelerated.

  Along with the thinning of the gate oxide film, in the PMOS transistor, the phenomenon that boron (p-type impurities) in the gate electrode diffuses into the gate oxide film or the silicon substrate (boron penetration) occurs due to the heat treatment during the semiconductor process. As a result, the transistor characteristics fluctuate. As a countermeasure against the boron penetration phenomenon, a gate oxynitride film formed by an oxynitride process in which nitrogen is introduced into the gate oxide film is widely used.

  In recent years, NBTI (Negative Bias Temperature Instability) has been pointed out as a phenomenon that causes fluctuations in characteristics of PMOS transistors. NBTI is a phenomenon in which transistor characteristics fluctuate when a negative voltage is applied to the gate electrode of a PMOS transistor at high temperatures due to the influence of positive fixed charges due to nitrogen existing near the interface between the gate insulating film and the substrate . As a measure against this NBTI, a plasma nitridation process in which the nitrogen concentration is peaked in a region on the gate electrode side instead of the substrate side in the gate insulating film is widely used.

  Hereinafter, a conventional process for manufacturing a p-type transistor using a plasma nitriding process will be described with reference to FIGS. 15 (a) to 15 (d).

  First, as shown in FIG. 15A, a gate oxide film 103 is formed on a semiconductor substrate 101.

  Next, as shown in FIG. 15B, the gate oxide film 103 is subjected to nitriding treatment with plasma 201, thereby introducing nitrogen 202 into the gate oxide film 103 to form a gate insulating film 103a.

  Next, as shown in FIG. 15C, after depositing a polysilicon film on the gate insulating film 103a, the polysilicon film is patterned using a lithography technique and a dry etching technique to form the gate electrode 104. Form.

  Next, as shown in FIG. 15 (d), B (boron) ions 203 are implanted to form an extension region (hereinafter referred to as an S / D extension region) 105 serving as a source region or a drain region.

  Next, as shown in FIG. 16A, after the sidewall 110 is formed, B ions 204 are implanted to form the source / drain diffusion layer 106. In this manner, a p-type transistor can be manufactured.

  In the conventional process for manufacturing a p-type transistor, a gate insulating film 103a having a peak N (nitrogen) atom concentration is formed in a region on the gate electrode 104 side of the gate insulating film 103a. Here, in general, B (boron) atoms introduced into the gate electrode penetrate through the gate insulating film during the activation annealing for forming the source region or the drain region, resulting in variations in device characteristics. However, in the conventional example, N atoms in the gate insulating film 103a prevent B atoms from penetrating. Thus, compared with the conventional oxynitride film in which the nitrogen concentration peak exists at the interface between the gate insulating film and the substrate in the gate insulating film, the oxynitride film formed by the nitrogen plasma treatment in the conventional example is NBTI. Excellent characteristics.

  As described above, the formation of the gate insulating film using the plasma nitriding process can suppress the penetration phenomenon of B (boron) introduced into the gate electrode and ensure the reliability of the NBTI characteristic. For this reason, the formation of the gate insulating film using the plasma nitriding process is expected to be widely used in the future.

According to the scaling rule, the gate length has been reduced to 65 nm in recent years, and the thickness of the gate insulating film has been reduced to 2 nm or less. Therefore, in recent years, attention has been focused on the electrical characteristics of the gate insulating film, that is, the gate leakage current value or long-term reliability.
Japanese Patent Laid-Open No. 10-209449

  However, when the gate insulating film is made thinner, B (boron) atoms existing in the S / D extension region 105 enter the gate insulating film 103a as shown in FIG. Deteriorating the reliability against. Although the mechanism by which B atoms existing in the S / D extension region 105 enter the gate insulating film 103a has not been completely elucidated, when the gate insulating film 103a is made of a radical nitride film, the gate insulating film 103a and silicon Due to the low N (nitrogen) concentration at the interface with the substrate 101 and the insulating film 107 used to define the silicide formation region in a later step, as shown in FIG. It is considered that the application of stress to the gate insulating film 103a promotes the penetration of B atoms existing in the S / D extension region 105 into the gate insulating film 103a.

  FIG. 17 is an enlarged cross-sectional view of the vicinity of the edge of the gate electrode of the p-type transistor using B (boron) as an impurity in the p-type impurity diffusion layer. As shown in FIG. 17, the entry of B atoms from the gate electrode can be prevented by a region having a high nitrogen density on the gate electrode side in the gate insulating film, but the S / D extension region formed in the silicon substrate. Of these, B atoms from the region located directly below the gate insulating film diffuse into the gate insulating film. As a result, defects occur in the network of silicon and oxygen in the gate insulating film, and the insulating characteristics deteriorate. As a result, the gate leakage current value in the gate insulating film increases, and the TDDB life (Time Dependent Dielectric Breakdown), which is one of the indicators of long-term reliability of the gate insulating film, is shortened.

  FIG. 18 is a graph showing an increase in the gate leakage current value of the gate insulating film, where the vertical axis shows the gate leakage current value per unit gate width and the horizontal axis shows the gate dimension.

  As is apparent from FIG. 18, in the case of an n-type MOS transistor, the gate leakage current value decreases linearly as the gate dimension becomes shorter. On the other hand, in the case of a p-type MOS transistor, the gate leakage current value has started to increase since the gate dimension has cut below 0.1 μm. This suggests that the gate leakage current value in the gate insulating film near the edge of the gate electrode occupies the total leakage current value, and supports the validity of the mechanism described above.

  As described above, in the p-type semiconductor device shown in the conventional example, B (boron) atoms enter the gate insulating film near the edge of the gate electrode, thereby increasing the gate leakage current value. There is a problem that the power consumption of the LSI increases, and further, the TDDB life is also deteriorated.

  In view of the above, an object of the present invention is to prevent p-type impurities from entering the gate insulating film, to prevent an increase in leakage current of the gate insulating film located near the edge of the gate electrode, and to improve the gate insulating film. It is an object of the present invention to provide a p-type semiconductor device that improves the lifetime and a manufacturing method thereof.

  In order to achieve the above object, a first method for manufacturing a semiconductor device according to the present invention includes: a step of forming a stacked structure including a gate insulating film and a gate electrode formed on a substrate in order from the bottom; A step of introducing nitrogen into the peripheral portion of the gate insulating film in the structure, a step of forming a p-type impurity diffusion layer in a region at least below the stacked structure in the substrate, and after forming the p-type impurity diffusion layer, And a step of performing a heat treatment, wherein the thickness of the gate insulating film is 2.4 nm or less.

  According to the first method for manufacturing a semiconductor device, the p-type formed in the region located below the gate insulating film in the stacked structure by introducing nitrogen into the peripheral portion of the gate insulating film in the stacked structure. The p-type impurity from the impurity diffusion layer can be prevented from entering the gate insulating film in the heat treatment step. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  The second method for manufacturing a semiconductor device according to the present invention includes a step of forming a laminated structure including a gate insulating film and a gate electrode formed in order from the bottom on a substrate, and a laminated structure on a peripheral portion and an upper portion of the laminated structure. Introducing nitrogen into the substrate surface where no substrate is formed forms a nitrogen-containing region in each of the peripheral portion of the laminated structure and the substrate surface, and at least in a region located below the laminated structure in the substrate a step of forming a p-type impurity diffusion layer, a step of forming a first sidewall having an L shape made of an oxide film on a side surface of a nitrogen-containing region formed in a peripheral portion of the stacked structure, and a first side A step of forming a second sidewall made of an insulating film so as to cover the surface of the wall; and a step of performing a heat treatment after the formation of the second sidewall. The thickness of the gate insulating film is 2 . Wherein the nm or less.

  According to the second method for manufacturing a semiconductor device, since the nitrogen-containing region is formed in the peripheral portion of the gate insulating film in the stacked structure, the p formed in the region located below the gate insulating film in the stacked structure. The p-type impurity from the type impurity diffusion layer can be prevented from entering the gate insulating film in the heat treatment step. Further, since the nitrogen-containing region is also formed on the gate electrode and the substrate surface in the stacked structure, the p-type impurity from the p-type impurity diffusion layer in the gate electrode and the p formed under the first sidewall. The p-type impurity from the type impurity diffusion layer can be prevented from entering the gate insulating film in the heat treatment step through the first sidewall. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  According to a third method of manufacturing a semiconductor device, a stacked structure is formed on a substrate, the stacked structure including a gate insulating film and a gate electrode formed in order from the bottom, and the stacked structure is formed on the periphery and the top of the stacked structure. Introducing nitrogen into the non-substrate surface, forming a nitrogen-containing region in each of the peripheral portion of the laminated structure and the substrate surface, and on the side surface of the nitrogen-containing region formed in the peripheral portion of the laminated structure, A step of forming a spacer layer made of an oxide film, a step of forming a p-type impurity diffusion layer in a region located at least on the lower side of the stacked structure in the substrate, and a step of performing a heat treatment after forming the p-type impurity diffusion layer And the thickness of the gate insulating film is 2.4 nm or less.

  According to the third method for manufacturing a semiconductor device, since the nitrogen-containing region is formed at the peripheral portion of the gate insulating film in the stacked structure, the p formed in the region located below the gate insulating film in the stacked structure. The p-type impurity from the type impurity diffusion layer can be prevented from entering the gate insulating film in the heat treatment step. Further, since the nitrogen-containing region is also formed on the gate electrode and the substrate surface in the laminated structure, the p-type impurity diffused from the p-type impurity from the p-type impurity diffusion layer in the gate electrode and the spacer layer is formed. P-type impurities from the layer can be prevented from entering the gate insulating film through the spacer layer in the heat treatment step. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  In the first to third semiconductor device manufacturing methods, the gate electrode contains p-type impurities, and it is preferable to perform nitriding treatment on the gate insulating film after forming the gate insulating film.

  In this case, since a region having a high nitrogen concentration is formed at the interface between the gate electrode and the gate insulating film in the gate insulating film, p-type impurities can be further prevented from entering the gate insulating film from the gate electrode. it can.

  In the first or second method for manufacturing a semiconductor device, it is preferable that a sidewall containing nitride is formed so as to cover a side surface of the gate electrode.

  In the first to third methods of manufacturing a semiconductor device, the gate insulating film includes nitrogen that has a concentration that decreases from an end of the gate insulating film constituting the stacked structure toward a lower portion of the center of the stacked structure. A concentration gradient exists.

  In the first to third semiconductor device manufacturing methods, it is preferable that after forming the source region and the drain region on the substrate, the source region and the drain region are covered with an insulating film and then annealed for activation. .

  A semiconductor device according to the present invention includes a stacked structure including a gate insulating film formed on a substrate in order from the bottom and a gate electrode containing a p-type impurity, and the gate insulating film and the gate electrode in the gate insulating film. A first nitrogen-containing region formed in the interface-side region and a second nitrogen-containing region that is formed in the peripheral portion of the gate insulating film in the stacked structure and has a peak nitrogen concentration near the peripheral edge of the peripheral portion And a p-type impurity diffusion layer formed in a region located at least on the lower side of the stacked structure in the substrate, and the thickness of the gate insulating film is 2.4 nm or less.

  According to the semiconductor device of the present invention, since the second nitrogen-containing region is formed at the peripheral portion of the gate insulating film in the stacked structure, it is formed in the region located below the gate insulating film in the stacked structure. It is possible to prevent p-type impurities from the p-type impurity diffusion layer from entering the gate insulating film. Further, since the first nitrogen-containing region is formed at the interface between the gate electrode and the gate insulating film in the gate insulating film, it is possible to prevent p-type impurities from entering the gate insulating film from the gate electrode. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  In the semiconductor device according to the present invention, the third nitrogen-containing region formed in the peripheral portion of the gate electrode in the stacked structure and the oxide formed on the substrate so as to be in contact with the third nitrogen-containing region A first sidewall having an L shape; and a second sidewall formed so as to cover the surface of the first sidewall. A p-type impurity diffusion layer is provided below the first sidewall. Is preferably formed.

  In this case, since the third nitrogen-containing region is formed in the peripheral portion of the gate electrode in the stacked structure, the p-type impurity from the p-type impurity diffusion layer in the gate electrode and the lower portion of the first sidewall are formed. P-type impurities from the formed p-type impurity diffusion layer can be further prevented from entering the gate insulating film through the first sidewall.

  In the semiconductor device according to the present invention, a third nitrogen-containing region formed in the peripheral portion of the gate electrode in the stacked structure, a spacer layer made of an oxide film formed so as to be in contact with the third nitrogen-containing region, A p-type impurity diffusion layer is preferably formed below the spacer layer.

  In this case, since the third nitrogen-containing region is formed in the peripheral portion of the gate electrode in the stacked structure, the p-type impurity from the p-type impurity diffusion layer in the gate electrode and the lower part of the spacer layer are formed. The p-type impurities from the p-type impurity diffusion layer can further be prevented from entering the gate insulating film through the spacer layer.

  In the semiconductor device according to the present invention, the gate insulating film has a nitrogen concentration gradient such that the concentration decreases from an end of the gate insulating film constituting the stacked structure toward a lower portion of the center of the stacked structure. doing.

  According to the first method for manufacturing a semiconductor device of the present invention, nitrogen is introduced into the peripheral portion of the gate insulating film in the stacked structure to form the region located below the gate insulating film in the stacked structure. It is possible to prevent p-type impurities from the p-type impurity diffusion region from entering the gate insulating film in the heat treatment step. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  According to the second method for manufacturing a semiconductor device according to the present invention, the nitrogen-containing region is formed in the peripheral portion of the gate insulating film in the stacked structure, and therefore formed in the region located below the gate insulating film in the stacked structure. The p-type impurity from the p-type impurity diffusion layer thus formed can be prevented from entering the gate insulating film in the heat treatment step. Further, since the nitrogen-containing region is also formed on the gate electrode and the substrate surface in the stacked structure, the p-type impurity from the gate electrode and the p-type impurity diffused layer formed below the first sidewall are formed. The type impurity can be prevented from entering the gate insulating film in the heat treatment step through the first sidewall. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  According to the third method for manufacturing a semiconductor device of the present invention, since the nitrogen-containing region is formed at the peripheral portion of the gate insulating film in the stacked structure, it is formed in the region located below the gate insulating film in the stacked structure. The p-type impurity from the p-type impurity diffusion layer thus formed can be prevented from entering the gate insulating film in the heat treatment step. Furthermore, since the nitrogen-containing region is also formed on the gate electrode and the substrate surface in the stacked structure, the p-type impurity from the gate electrode and the p-type impurity from the p-type impurity diffusion layer formed below the spacer layer are present. Through the spacer layer, the gate insulating film can be prevented from entering in the heat treatment step. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

  According to the semiconductor device of the present invention, since the second nitrogen-containing region is formed at the peripheral portion of the gate insulating film in the stacked structure, it is formed in the region located below the gate insulating film in the stacked structure. It is possible to prevent p-type impurities from the p-type impurity diffusion layer from entering the gate insulating film. Further, since the first nitrogen-containing region is formed at the interface between the gate electrode and the gate insulating film in the gate insulating film, it is possible to prevent p-type impurities from entering the gate insulating film from the gate electrode. Thereby, gate leakage current can be suppressed and reliability such as life deterioration of the gate insulating film can be secured.

(First embodiment)
Hereinafter, as an example of the method of manufacturing the semiconductor device according to the first embodiment of the present invention, a method of manufacturing a p-type MIS transistor will be described with reference to the drawings.

First, as shown in FIG. 1A, a gate oxide film 103 made of SiO ₂ having a thickness of 1.8 nm is formed on a semiconductor substrate 101 made of silicon.

  Next, as shown in FIG. 1B, the gate oxide film 103 is subjected to nitridation treatment (peak nitrogen concentration: 5 to 10%) with plasma 201, whereby nitrogen 202 is contained in the gate oxide film 103. Then, a gate insulating film 103a is formed. At this time, nitrogen introduced into the gate oxide film 103 by the plasma 201 exists in the vicinity of the upper surface of the gate insulating film 103a, that is, in the region of the gate insulating film 103a on the interface side between the gate insulating film and a gate electrode described later. Thus, diffusion of impurities from the gate electrode into the gate insulating film 103a can be prevented.

  Next, as shown in FIG. 1C, a polysilicon film doped with boron having a thickness of 160 nm is deposited on the gate insulating film 103a by a CVD method, and then a lithography technique and a dry etching technique. Then, the deposited polysilicon film is patterned to form a gate electrode 104 having a gate length of 70 nm made of a p-type polysilicon film to which boron is added.

  Next, as shown in FIG. 1D, plasma nitriding treatment (peak nitrogen concentration: 7 to 15%) is performed on the gate electrode 104 and the gate insulating film 103a, so that the gate electrode 104 and the gate insulating film 103a A high concentration nitrogen-containing region is formed in the local region 301a.

  Here, the high concentration nitrogen-containing region will be described with reference to FIG.

  FIG. 2A is an enlarged cross-sectional view near the local region 301 a at the end of the gate electrode 104.

  As shown in FIG. 2A, nitrogen is introduced into the gate insulating film 103a formed immediately below the gate electrode 104 and the peripheral portion of the gate electrode 104 by the plasma nitriding process. As a result, the gate insulating film 103b having a nitrogen concentration gradient in the channel direction, that is, in the horizontal direction, is formed in the film. The nitrogen concentration has a peak in a region that enters about 1 nm from the region located below the end of the gate electrode 104 in the gate insulating film 103b toward the region located below the center of the gate electrode 104. Thus, a nitrogen concentration gradient is formed in the horizontal direction of the gate insulating film 103b. In addition to the formation of the gate insulating film 103b, as shown in FIG. 2A, a gate insulating film 103c is formed in a region outside the gate electrode 104, which is a region where the gate electrode 104 is not formed on the upper portion. . Regarding the gate insulating film 103c, the gate insulating film 103b may not be formed in the region outside the gate electrode 104. That is, during the etching for forming the gate electrode 104, the gate insulating film 103c formed in the region outside the gate electrode 104 is etched, and the semiconductor substrate 101 is exposed in the region outside the gate electrode 104. It does not matter. In this case, nitrogen is introduced into the semiconductor substrate 101 exposed in the region outside the gate electrode 104 by plasma nitriding. In any case, nitrogen is introduced into a region of the gate insulating film 103b that exists below the end portion of the gate electrode 104, and the gate electrode 104 starts from a region that is located under the end portion of the gate electrode 104. A nitrogen concentration gradient is formed such that the nitrogen concentration decreases toward the region located in the lower part of the center of the.

  Although not shown in detail in FIG. 2A, nitrogen is also introduced into the peripheral portion of the gate electrode 104 by plasma nitriding to form a high-concentration nitrogen-containing region (see FIG. 8A described later). ) And FIG. 12 (a)).

Next, as shown in FIG. 2B, ion implantation of B (boron) ions 203 (energy: 1 keV or less, dose: 4 to 7 × 10 ¹⁴ cm ⁻² ) is performed using the gate electrode 104 as a mask. Thus, an S / D (source / drain) extension region 105 is formed.

Next, as shown in FIG. 2C, a sidewall 110 made of an insulating film made of silicon nitride (SiN) is formed on the sidewall of the gate electrode 104, and then ion implantation of B (boron) ions 204 ( (Energy: 2-4 keV, dose: 3-6 × 10 ¹⁵ cm ⁻² ) to form the source / drain diffusion layer 106.

  Next, as shown in FIG. 3A, activation annealing (temperature: 1050 ° C.) is applied to the source / drain diffusion layer 106 to form a source / drain structure.

  Alternatively, as shown in FIG. 3B, after forming an insulating film 107 made of silicon dioxide for defining a silicide region, activation annealing (temperature: 1050 ° C.) for the source / drain diffusion layer 106 is performed. You may give it. In this case, silicide is then formed.

  In any of the steps shown in FIG. 3 (a) and FIG. 3 (b), the S / D extension region 105 is removed by heat during activation annealing at a high temperature exceeding 1000 ° C. B (boron) atoms try to diffuse into the gate insulating film 103b. However, diffusion of B atoms from the S / D extension region 105 to the gate insulating film 103b can be suppressed by N (nitrogen) atoms introduced in advance into the gate insulating film 103a. As a result, it is possible to prevent deterioration of electrical characteristics.

  FIG. 4 shows an evaluation result of the TDDB life, which is a reliability index of the gate insulating film constituting the p-type MIS transistor according to the present embodiment.

  Note that the thickness of the gate insulating film of the p-type MIS transistor to be evaluated is 1.8 nm, the gate length is 65 nm, and the gate width is 1 μm. In addition, the evaluation results for those in which 10,000 p-type MIS transistors are arranged in an array are shown. Furthermore, the gate voltage to be applied is −3.0 V, and the substrate temperature is 125 ° C. FIG. 4 is a Weibull plot in these cases.

  The vertical axis indicates Weibull cumulative failure, and the horizontal axis indicates the time until gate insulating film breakdown. In FIG. 4, a conventional example (●), a present example (▲), and a comparative example (♦) are shown.

  As is apparent from FIG. 4, according to the present embodiment (▲), it can be seen that the TDDB life is improved by an order of magnitude or more compared to the conventional example (●).

  On the other hand, when the SiN film formed by raising the film forming temperature from the conventional low temperature condition (580 to 620 ° C.) to the high temperature condition (680 to 730 ° C.) is used as the sidewall 110, or an etching stopper film is formed at the time of contact formation Even when a SiN film formed under a high temperature condition is used as 108, it has been confirmed that the effect of improving the TDDB life can be obtained.

As shown in FIG. 3 (c), after the step of FIG. 3 (b), after removing the insulating film 107 made of SiO ₂ for defining the silicide region, the silicide 111 is formed and formed under high temperature conditions. An etching stopper film 108 made of the SiN film thus formed is formed.

  As is apparent from FIG. 4, the comparative example (HT Nitride (♦)) shows a case where the sidewall 110 made of the SiN film formed under the high temperature condition as described above is formed. Also in this comparative example, the TDDB life is improved by an order of magnitude. However, as shown in FIG. 5, it is known that device characteristics deteriorate when using a SiN film formed under high temperature conditions.

  That is, FIG. 5 shows the driving force (Ids) of the device on the horizontal axis and the TDDB life on the vertical axis. Further, in FIG. 5, similarly to FIG. 4, a conventional example (●), a present example (▲), and a comparative example (♦) are shown.

  As is clear from FIG. 5, when the sidewall 110 made of the SiN film formed under the high temperature condition shown in the comparative example (HT Nitride (♦)) is used, the driving force is as shown in this example (▲ It can be seen that it is lower than the case where the plasma nitriding treatment is performed after the formation of the gate electrode 104 shown in FIG. Further, as is clear from this figure, the p-type MIS transistor according to this example (●) can obtain good reliability without deterioration in characteristics, and the n-type MIS transistor can be used instead of the p-type MIS transistor. Even when the manufacturing method according to the embodiment is applied, the same characteristics as in the case of the p-type MIS transistor can be obtained.

  As described above, according to the first embodiment, a transistor having the following configuration can be realized. That is, the nitrogen concentration in the gate insulating film has a gradient in the channel direction. In particular, the gate insulating film has a high nitrogen concentration in a region (gate edge) located below the end of the gate electrode in the gate insulating film. Has a gradient.

  FIG. 6 is a conceptual diagram for explaining the prevention of diffusion of B (boron) atoms from the S / D extension region in the nitride-based single-layer sidewall structure according to the first embodiment. FIG. 4 is a diagram illustrating the prevention of diffusion of B atoms from the S / D extension region in a region (gate edge) located below the end of the gate electrode in the insulating film.

  As is apparent from FIG. 6, as described with reference to FIG. 17, the entry of B (boron) atoms from the gate electrode to the gate insulating film is caused by the region having a high nitrogen density on the gate electrode side in the gate insulating film. Can be blocked.

  Furthermore, in this embodiment, as shown in FIG. 6, the gate insulating film has a nitrogen concentration peak in the vicinity of the gate edge at the peripheral edge of the gate insulating film, and is positioned below the center of the gate electrode in the gate insulating film. The gradient of the nitrogen concentration is such that the nitrogen concentration becomes lower toward the region to be processed. Therefore, in a transistor whose gate insulating film is thinned to 2.4 nm or less, diffusion of B (boron) from the S / D extension region into the gate insulating film can be suppressed by nitrogen in the gate insulating film. Therefore, for example, even when an activation RTA process is performed at a high temperature exceeding 1000 ° C. in a state where an oxide film for protecting a silicide is deposited or in a normal state, boron in the gate insulating film Since diffusion can be suppressed, it is effective for suppressing gate leakage and suppressing deterioration of the TDDB life of the gate insulating film.

  Thus, for example, even when an activation RTA process is performed at a high temperature exceeding 1000 ° C. in a state where an oxide film for protecting a silicide is deposited or in a normal state, Since diffusion of B (boron) can be suppressed, gate leakage can be suppressed and deterioration of the TDDB life of the gate insulating film can be suppressed.

(Second Embodiment)
Hereinafter, as an example of a method for manufacturing a semiconductor device according to the second embodiment of the present invention, a method for manufacturing a p-type MIS transistor will be described with reference to the drawings.

First, as shown in FIG. 7A, a gate oxide film 103 made of SiO ₂ having a thickness of 1.8 nm is formed on a semiconductor substrate 101 made of silicon.

  Next, as shown in FIG. 7B, the gate oxide film 103 is subjected to nitridation treatment with plasma 201 (peak nitrogen concentration: 5 to 10%), whereby nitrogen 202 is contained in the gate oxide film 103. Then, a gate insulating film 103a is formed. At this time, nitrogen introduced into the gate oxide film 103 by the plasma 201 exists in the upper surface of the gate insulating film 103a, that is, in the region on the interface side between the gate insulating film and the gate electrode described later in the gate insulating film 103a. Therefore, diffusion of impurities from the gate electrode into the gate insulating film 103a can be prevented.

  Next, as shown in FIG. 7C, after depositing a polysilicon film to which boron having a thickness of 160 nm is added on the gate insulating film 103a by the CVD method, a lithography technique and a dry etching technique are performed. Then, the deposited polysilicon film is patterned to form a gate electrode 104 having a gate length of 70 nm made of a p-type polysilicon film to which boron is added. In FIG. 7C, the gate insulating film 103a is patterned in the same shape as the gate electrode 104.

  Next, as shown in FIG. 7D, plasma nitriding treatment (peak nitrogen concentration: 7 to 15%) is performed on the gate electrode 104, the gate insulating film 103a, and the semiconductor substrate 101 to thereby obtain the gate electrode 104. A high-concentration nitrogen-containing region is formed in a local region 301a at the end of the substrate.

  Here, the high concentration nitrogen-containing region will be described with reference to FIG.

  FIG. 8A is an enlarged cross-sectional view near the local region 301 a at the end of the gate electrode 104.

  As shown in FIG. 8A, nitrogen is introduced into the peripheral portion of the gate insulating film 103a and the peripheral portion of the gate electrode 104 formed immediately below the gate electrode 104 by the plasma nitriding process, The semiconductor substrate 101 is introduced into the exposed surface portion. As a result, the gate insulating film 103b having a nitrogen concentration gradient in the channel direction, that is, the horizontal direction in the film is formed, and the high concentration impurity-containing region 122 is formed in the vicinity of the end of the gate insulating film 103b. Specifically, the nitrogen concentration has a peak in a region that is about 1 nm from the region located below the end of the gate electrode 104 in the gate insulating film 103b toward the region located below the center of the gate electrode 104. Thus, a nitrogen concentration gradient is formed in the horizontal direction of the gate insulating film 103a.

  A high concentration nitrogen-containing region 121 is also formed at the peripheral edge of the gate electrode 104, and a high concentration nitrogen-containing region 120 is also formed on the exposed surface of the semiconductor substrate 101.

Next, as shown in FIG. 8B, ion implantation of B (boron) ions 203 (energy: 1 keV or less, dose amount: 4 to 7 × 10 ¹⁴ cm ⁻² ) is performed using the gate electrode 104a as a mask. Thus, an S / D (source / drain) extension region 105 is formed.

Next, as shown in FIG. 8C, a laminated sidewall made of an oxide film 110a made of SiO ₂ and an insulating film 110 made of SiN is formed on the sidewall of the gate electrode 104a. The oxide film 110a is an L-shaped sidewall formed on the side surface of the gate electrode 104a, and the insulating film 110 is formed on the L-shaped sidewall 110a so as to cover the L-shaped sidewall 110a. Is provided. At this time, the high-concentration nitrogen-containing region 120a remains in the region immediately below the stacked sidewall on the surface of the semiconductor substrate 101.

Next, ion implantation (energy: 2 to 4 keV, dose: 3 to 6 × 10 ¹⁵ cm ⁻² ) of B (boron) ions 204 is performed to form the source / drain diffusion layer 106.

  Next, as shown in FIG. 9A, activation annealing (temperature: 1050 ° C.) is applied to the source / drain diffusion layer 106 to form a source / drain structure.

Alternatively, as shown in FIG. 9B, after forming an insulating film 107 made of SiO ₂ for defining a silicide region, activation annealing (temperature: 1050 ° C.) is applied to the source / drain diffusion layer. May be. In this case, silicide is then formed.

  In any of the steps shown in FIGS. 9 (a) and 9 (b), the S / D extension region 105 is removed by heat during activation annealing at a high temperature exceeding 1000 ° C. B (boron) atoms try to diffuse into the gate insulating film 103b. However, diffusion of B (boron) atoms from the S / D extension region 105 to the gate insulating film 103b can be suppressed by N (nitrogen) atoms introduced in advance into the gate insulating film 103a. Further, the high-concentration nitrogen-containing region 122 in the peripheral portion of the gate insulating film 103a, the high-concentration nitrogen-containing region 121 formed on the side surface of the gate electrode 104a, and the high that exists immediately below the sidewall 110a on the surface of the semiconductor substrate 101. The concentration nitrogen-containing region 120a can suppress diffusion of B atoms from the gate electrode 104a and the S / D extension region 105 to the gate insulating film 103b through the L-type sidewall 110a. As a result, as in the first embodiment, it is possible to prevent deterioration of electrical characteristics.

As shown in FIG. 9 (c), after the step of FIG. 9 (b), after removing the insulating film 107 made of SiO ₂ for defining the silicide region, the silicide 111 is formed, and etching made of the SiN film is performed. The stopper film 108 can also be formed.

  As described above, according to the second embodiment, a semiconductor device having the following configuration can be realized. That is, the nitrogen concentration in the gate insulating film has a gradient in the channel direction. In particular, the gate insulating film has a high nitrogen concentration in a region (gate edge) located below the end of the gate electrode in the gate insulating film. Has a gradient. Further, the nitrogen concentration is high in the side surface of the gate electrode and the region existing directly under the sidewall in the semiconductor substrate.

  FIGS. 10A and 10B are conceptual diagrams illustrating the diffusion prevention of B atoms from the S / D extension region in the stacked sidewall structure according to the second embodiment. Specifically, FIG. FIG. 4 is a diagram illustrating the prevention of diffusion of B atoms from the S / D extension region in a region (gate edge) located below the end of the gate electrode in the insulating film.

  First, as shown in FIG. 10A, when a high nitrogen concentration region is formed only in the region on the gate electrode side in the gate insulating film, entry of B atoms from the gate electrode into the gate insulating film is prevented. Although it is possible, diffusion of boron from the S / D extension region into the gate insulating film cannot be suppressed.

  However, according to the present embodiment, as shown in FIG. 10B, the gate insulating film has a nitrogen concentration peak near the gate edge, and is directed to a region located below the center of the gate electrode in the gate insulating film. Thus, the nitrogen concentration gradient is such that the nitrogen concentration becomes low. Therefore, in a transistor whose gate insulating film is thinned to 2.4 nm or less, diffusion of B (boron) from the S / D extension region into the gate insulating film can be suppressed by nitrogen in the gate insulating film. In addition, the gate electrode to which B (boron) is added also has an L-type sidewall made of an oxide film formed from boron in the gate electrode because the high concentration nitrogen-containing region 121 is formed on the side surface of the gate electrode. Thus, diffusion to the gate insulating film can be prevented. Further, since the high-concentration impurity region 120a is also formed in the semiconductor substrate, it is possible to prevent boron in the S / D extension region from diffusing into the gate insulating film through the L-type sidewall made of an oxide film. it can.

  Thus, for example, even when an activation RTA process is performed at a high temperature exceeding 1000 ° C. in a state where an oxide film for protecting a silicide is deposited or in a normal state, Since boron diffusion can be suppressed, gate leakage can be suppressed and deterioration of the TDDB life of the gate insulating film can be suppressed.

(Third embodiment)
Hereinafter, as an example of a method for manufacturing a semiconductor device according to the third embodiment of the present invention, a method for manufacturing a p-type MIS transistor will be described with reference to the drawings.

First, as shown in FIG. 11A, a gate oxide film 103 made of SiO ₂ having a thickness of 1.8 nm is formed on a semiconductor substrate 101 made of silicon.

  Next, as shown in FIG. 11 (b), the gate oxide film 103 is subjected to nitridation treatment (peak nitrogen concentration: 5 to 10%) with plasma 201, whereby nitrogen 202 is contained in the gate oxide film 103. Then, a gate insulating film 103a is formed. At this time, nitrogen introduced into the gate oxide film 103 by the plasma 201 exists in the upper surface of the gate insulating film 103a, that is, in a region of the gate insulating film 103a on the interface side between the gate insulating film 103a and a gate electrode described later. Thus, diffusion of impurities from the gate electrode into the gate insulating film 103a can be prevented.

  Next, as shown in FIG. 11C, after depositing a polysilicon film doped with boron having a thickness of 160 nm on the gate insulating film 103a by CVD, lithography and dry etching techniques are performed. Then, the deposited polysilicon film is patterned to form a gate electrode 104 having a gate length of 70 nm made of a p-type polysilicon film to which boron is added. In FIG. 11C, the gate insulating film 10a is patterned in the same shape as the gate electrode 104.

  Next, as shown in FIG. 11D, plasma nitriding treatment (peak nitrogen concentration: 7 to 15%) is performed on the gate electrode 104, the gate insulating film 103a, and the semiconductor substrate 101 to thereby obtain the gate electrode 104. A high-concentration nitrogen-containing region is formed in a local region 301a at the end of the substrate.

  Here, the high concentration nitrogen-containing region will be described with reference to FIG.

  FIG. 12A is an enlarged cross-sectional view near the local region 301 a at the end of the gate electrode 104.

  As shown in FIG. 12 (a), nitrogen is introduced into the peripheral portion of the gate insulating film 103a and the peripheral portion of the gate electrode 104 formed immediately below the gate electrode 104 by the plasma nitriding process. The semiconductor substrate 101 is introduced into the exposed surface portion. As a result, the gate insulating film 103b having a nitrogen concentration gradient in the channel direction, that is, the horizontal direction is formed in the film, and the high concentration impurity-containing region 122 is formed at the end of the gate insulating film 103b. Specifically, the nitrogen concentration has a peak in a region that is about 1 nm from the region located below the end of the gate electrode 104 in the gate insulating film 103b toward the region located below the center of the gate electrode 104. Thus, a nitrogen concentration gradient is formed in the horizontal direction of the gate insulating film 103a. In addition, a high concentration nitrogen-containing region 121 is formed also on the peripheral portion of the gate electrode 104, and a high concentration nitrogen-containing region 120 a is also formed on the exposed surface of the semiconductor substrate 101.

Next, as shown in FIG. 12B, an oxide film 109 for offset spacer made of SiO ₂ is formed on the side wall of the gate electrode 104a made of p-type polysilicon doped with p-type impurities. At this time, a high-concentration nitrogen-containing region 120a formed by nitriding plasma treatment remains in a region of the semiconductor substrate 101 that exists immediately below the oxide film 109 for the offset spacer.

Next, ion implantation of B (boron) ions 203 (energy: 1 keV or less, dose: 4 to 7 × 10 ¹⁴ cm ⁻² ) is performed using the gate electrode 104a and the offset spacer oxide film 109 as a mask. An S / D extension region 105 is formed.

Next, as shown in FIG. 12C, after forming a sidewall made of the insulating film 110, ion implantation of B (boron) ions 204 (energy: 2-4 keV, dose: 3-6 × 10 ^15). cm ⁻² ) to form the source / drain diffusion layer 106.

  Next, as shown in FIG. 13A, activation annealing (temperature: 1050 ° C.) is applied to the source / drain diffusion layer 106 to form a source / drain structure.

Alternatively, as shown in FIG. 13B, after forming an insulating film 107 made of SiO ₂ for defining a silicide region, activation annealing (temperature: 1050 ° C.) is applied to the source / drain diffusion layer. May be. In this case, silicide is then formed.

  In any of the steps shown in FIGS. 13 (a) and 13 (b), the S / D extension region 105 is removed by heat during activation annealing at a high temperature exceeding 1000 ° C. B (boron) atoms try to diffuse into the gate insulating film 103b. However, diffusion of B (boron) atoms from the S / D extension region 105 to the gate insulating film 103b can be suppressed by N (nitrogen) atoms introduced in advance into the gate insulating film 103a. Further, the high-concentration nitrogen-containing region 122 at the end of the gate insulating film 103a, the high-concentration nitrogen-containing region 121 formed on the side surface of the gate electrode 104a, and the high-concentration nitrogen existing immediately below the sidewall on the surface of the semiconductor substrate 101 The inclusion region 120a can suppress the diffusion of B atoms from the gate electrode 104a and the S / D extension region 105 to the gate insulating film 103b. As a result, as in the first embodiment, it is possible to prevent deterioration of electrical characteristics.

As shown in FIG. 13C, after the step of FIG. 13B, after the insulating film 107 made of SiO ₂ for defining the silicide region is removed, the silicide 111 is formed, and etching made of the SiN film is performed. The stopper film 108 can also be formed.

  As described above, according to the third embodiment, a semiconductor device having the following configuration can be realized. That is, the nitrogen concentration in the gate insulating film has a gradient in the channel direction. In particular, the gate insulating film has a high nitrogen concentration in a region (gate edge) located below the end of the gate electrode in the gate insulating film. Has a gradient. Further, the nitrogen concentration is high in the peripheral portion of the gate electrode and in the region existing directly under the offset spacer in the semiconductor substrate.

  FIGS. 14A and 14B are conceptual diagrams for explaining the diffusion prevention of B atoms from the S / D extension region in the sidewall structure with an offset spacer made of an oxide film in the third embodiment. Specifically, a diagram for explaining diffusion prevention of B atoms from the S / D extension region in a region (gate edge) located under the end of the gate electrode in the gate insulating film is shown.

  First, as shown in FIG. 14A, when a high nitrogen concentration region is formed only in the region on the gate electrode side in the gate insulating film, entry of B atoms from the gate electrode into the gate insulating film is prevented. Although it is possible, diffusion of B (boron) from the S / D extension region into the gate insulating film cannot be suppressed.

  However, according to the present embodiment, as shown in FIG. 14B, the gate insulating film has a nitrogen concentration peak in the vicinity of the gate edge, and is directed to a region located below the center of the gate electrode in the gate insulating film. Thus, the nitrogen concentration gradient is such that the nitrogen concentration becomes low. For this reason, in a transistor whose gate insulating film is made thinner than 2.4 nm, diffusion of boron from the S / D extension region into the gate insulating film can be suppressed by nitrogen in the gate insulating film. In addition, the gate electrode to which B (boron) is added also has a high-concentration nitrogen-containing region 121 formed at the periphery of the gate electrode, so that boron in the gate electrode is interposed via an offset spacer made of an oxide film. Thus, diffusion into the gate insulating film can be prevented. Further, since the high concentration impurity region 120a is also formed in the semiconductor substrate, it is possible to prevent the boron in the S / D extension region from diffusing into the gate insulating film through the offset spacer made of the oxide film.

  Thus, for example, even when an activation RTA process is performed at a high temperature exceeding 1000 ° C. in a state where an oxide film for protecting a silicide is deposited or in a normal state, Since boron diffusion can be suppressed, gate leakage can be suppressed and deterioration of the TDDB life of the gate insulating film can be suppressed.

  As described above, according to the first to third embodiments, a nitrogen profile having a concentration gradient is formed in the gate insulating film by nitrogen introduced before the formation of the S / D extension region. Boron diffusion from the / D extension region into the gate insulating film can be suppressed.

  In addition to the diffusion of boron from the S / D extension region by the nitrogen introduced before the formation of the S / D extension region, it is formed at the peripheral portion of the gate electrode by the nitrogen introduced into the peripheral portion of the gate electrode. Boron diffusion from the gate electrode to the gate insulating film can be suppressed through the formed oxide film. As a result, an increase in gate leakage can be suppressed and a decrease in reliability with respect to the TDDB life can be suppressed.

  In addition, an increase in gate leakage can be suppressed and a decrease in TDDB life can be suppressed against an increase in mechanical stress associated with the formation of an insulating film for defining a silicide region formed in a later process.

  As described above, the present invention is useful for a semiconductor device and a manufacturing method thereof, and is particularly suitable for a p-type semiconductor device and a manufacturing method thereof.

(a)-(d) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows the process dependence of the gate insulating-film lifetime in 1st Embodiment. It is a graph which shows the relationship between the gate insulating-film lifetime in 1st Embodiment, and the driving force of a device. FIG. 5 is a conceptual diagram illustrating diffusion prevention of B atoms from an S / D extension region in the nitride-based single-layer sidewall structure according to the first embodiment. (a)-(d) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a) And (b) is a conceptual diagram for demonstrating the spreading | diffusion of B atom from a S / D extension area | region and a gate electrode in the lamination | stacking sidewall structure in 2nd Embodiment. (a)-(d) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (a) And (b) is a conceptual diagram for demonstrating the diffusion of B atom from an S / D extension region and a gate electrode in the sidewall structure with an oxide film offset spacer according to the third embodiment. . (a)-(d) is process sectional drawing of the conventional semiconductor device. (a)-(c) is process sectional drawing of the conventional semiconductor device. FIG. 5 is a conceptual diagram illustrating a state in which B atoms from an S / D extension region are diffused in a nitride-based single-layer sidewall structure. It is a graph which shows the relationship between the gate leakage current value and gate length about an n-type MOS transistor and a p-type MOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 103 Gate oxide film 103a, 103b, 103c Gate insulating film 104 containing nitrogen, 104a Gate polysilicon film 105 S / D extension 106 Source / drain diffusion layer 107 Insulating film 108 for defining silicide region Etching stopper Insulating film 109 as a film Oxide film 110 for offset spacer 110 Side wall 110a Lower layer oxide film 111 for laminated side wall CoSi 2
120, 120a Ni-containing silicon region 121 Nitrogen-containing polysilicon region 122 Nitrogen-containing gate insulating film 201 Nitrogen plasma 202 N ions, N radicals 203, 204 B ions 301 Regions at the end of the gate electrode

Claims (11)

Forming a laminated structure including a gate insulating film and a gate electrode formed in order from the bottom on the substrate;
Introducing nitrogen into a peripheral portion of the gate insulating film in the stacked structure;
Forming a p-type impurity diffusion layer at least in a region located on the lower side of the stacked structure in the substrate;
And a step of performing a heat treatment after forming the p-type impurity diffusion layer,
A method of manufacturing a semiconductor device, wherein the gate insulating film has a thickness of 2.4 nm or less. Forming a laminated structure including a gate insulating film and a gate electrode formed in order from the bottom on the substrate;
A step of forming a nitrogen-containing region in each of the peripheral edge of the multilayer structure and the substrate surface by introducing nitrogen into the peripheral edge of the multilayer structure and the substrate surface on which the multilayer structure is not formed; When,
Forming a p-type impurity diffusion layer in at least a region of the substrate located below the stacked structure;
Forming a first sidewall having an L shape made of an oxide film on a side surface of the nitrogen-containing region formed in a peripheral portion of the laminated structure;
Forming a second sidewall made of an insulating film so as to cover the surface of the first sidewall;
And a step of performing a heat treatment after forming the second sidewall,
A method of manufacturing a semiconductor device, wherein the gate insulating film has a thickness of 2.4 nm or less. Forming a laminated structure including a gate insulating film and a gate electrode formed in order from the bottom on the substrate;
A step of forming a nitrogen-containing region in each of the peripheral edge of the multilayer structure and the substrate surface by introducing nitrogen into the peripheral edge of the multilayer structure and the substrate surface on which the multilayer structure is not formed; When,
Forming a spacer layer made of an oxide film on a side surface of the nitrogen-containing region formed at the peripheral edge of the laminated structure;
Forming a p-type impurity diffusion layer in at least a region of the substrate located below the stacked structure;
And a step of performing a heat treatment after forming the p-type impurity diffusion layer,
A method of manufacturing a semiconductor device, wherein the gate insulating film has a thickness of 2.4 nm or less. The gate electrode contains p-type impurities,
4. The method of manufacturing a semiconductor device according to claim 1, wherein nitriding treatment is performed on the gate insulating film after forming the gate insulating film.   The method for manufacturing a semiconductor device according to claim 1, wherein a sidewall containing nitride is formed so as to cover a side surface of the gate electrode.   The gate insulating film has a nitrogen concentration gradient in which the concentration decreases from an end of the gate insulating film constituting the stacked structure toward a lower portion of the center of the stacked structure. The method of manufacturing a semiconductor device according to claim 1, 2, or 3.   The annealing process for activation is performed after forming the source region and the drain region on the substrate and then covering the source region and the drain region with an insulating film. The manufacturing method of the semiconductor device of description. A laminated structure comprising a gate insulating film formed in order from the bottom on the substrate and a gate electrode containing a p-type impurity;
A first nitrogen-containing region formed in a region of the gate insulating film on the interface side between the gate insulating film and the gate electrode;
A second nitrogen-containing region that is formed at a peripheral portion of the gate insulating film in the stacked structure and has a peak nitrogen concentration in the vicinity of the peripheral edge of the peripheral portion;
A p-type impurity diffusion layer formed in a region located at least on the lower side of the stacked structure in the substrate,
The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of 2.4 nm or less. A third nitrogen-containing region formed at the peripheral edge of the gate electrode in the stacked structure;
A first sidewall having an L shape made of an oxide formed on the substrate so as to be in contact with the third nitrogen-containing region;
A second sidewall formed so as to cover the surface of the first sidewall;
9. The semiconductor device according to claim 8, wherein the p-type impurity diffusion layer is formed below the first sidewall. A third nitrogen-containing region formed at the peripheral edge of the gate electrode in the stacked structure;
A spacer layer formed of an oxide film so as to be in contact with the third nitrogen-containing region;
9. The semiconductor device according to claim 8, wherein the p-type impurity diffusion layer is formed under the spacer layer.   The gate insulating film has a nitrogen concentration gradient in which the concentration decreases from an end of the gate insulating film constituting the stacked structure toward a lower portion of the center of the stacked structure. The semiconductor device according to claim 8, 9, or 10.

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