JP2000236088A - Mos transistor manufacture method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a possibility of particle generation on a gate oxide film by heat processing in ammonium gas circumstance and heat processing in oxygen circumstance after machining of the gate oxide film and a gate electrode. SOLUTION: A gate oxide film 2 is formed on a P type semiconductor substrate 1 and a polycrystalline silicon film 3 to become a gate electrode 4 is piled thereon. The gate electrode 4 is formed by photolithography and etching of the polycrystalline silicon film 3 on the gate oxide film 2. Next a region 5 where nitrogen in the ammonia gate is defused is formed on the exposed gate oxide film 2 and in the gate oxide film 2 which is near both terminals under the gate electrode 4. Also the surface of the gate electrode 4 is oxidized by hear processing in the circumstance including oxygen. Next in case of an NMOS type, an N type element such as arsenic is implanted into the gate electrode 4 and into an N type source 7 and an N type drain 6 regions by ion infusion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the quality of a MOS transistor.

[0002]

2. Description of the Related Art In a MOS transistor, when heat treatment is performed in an ammonia atmosphere to improve hot carrier characteristics at an interface between a gate oxide film and a semiconductor, a second method is used.
As shown in the figure, after forming a gate oxide film in a diffusion furnace, heat treatment is performed in an ammonia gas atmosphere using a lamp heating device, and then a gate electrode film is deposited and processed into a gate electrode by photolithography and etching. It is known.

[0003]

Generally, in order to minimize particles on a gate oxide film which cause a defect of a MOS transistor, a gate electrode film is formed by a CVD apparatus immediately after the gate oxide film is formed. Should be deposited. When a step is inserted between the gate oxide film forming step and the gate electrode forming step, particles adhering in the interposed step are removed to some extent by cleaning using a mixture of an ammonia solution and a hydrogen peroxide solution such as RCA cleaning. However, these cleaning methods cannot remove particles without damaging the gate oxide film, such as scraping the gate oxide film. In the related art, after forming the gate oxide film, it is necessary to perform the treatment in the ammonia atmosphere in the lamp heating device, and there is a possibility that particles may be generated on the gate oxide film which causes a defect.

[0004]

In the present invention, a heat treatment in an ammonia gas atmosphere and a heat treatment in an oxygen atmosphere are performed after processing the gate electrode. As a result, since no step is inserted between the gate oxide film forming step and the gate electrode film depositing step, there is a small possibility of generating particles on the gate oxide film which cause a defect.

[0005]

(Embodiment 1) FIG. 1 shows a method of manufacturing a polycrystalline silicon gate NMOS transistor according to the present invention in the order of steps. FIG. 1A shows that a gate oxide film 2 such as a silicon thermal oxide film having a film thickness of 50 to 500 Å is formed on a P-type silicon substrate 1 and a polycrystalline silicon film 3 serving as a gate electrode is thermally formed thereon. CVD
This shows a process deposited by a method or the like. Polycrystalline silicon film 3
Has a thickness of 2000 to 5000 angstroms. The polycrystalline silicon film 3 is made of P mixed with nitrogen gas.
An N-type impurity may be doped by treatment using OCl 3, but a crystal step becomes large due to a heat process step using a lamp heating device after gate electrode processing, and the shape of the gate electrode becomes uneven, which adversely affects transistor characteristics. In this step, it is preferable not to dope impurities. FIG. 1 (b) shows a process of forming a gate electrode 4 by photolithography and etching of the polycrystalline silicon film 3 on the gate oxide film. FIG. 1 (c) shows a heat treatment step in an atmosphere containing ammonia gas and a heat treatment step in an atmosphere containing oxygen. Although these heat treatment steps may be performed in a normal diffusion furnace, rapid heating by a lamp heating device that can further suppress impurity diffusion in the semiconductor substrate is more suitable. 1000 to 1200 ° C for lamp heating
It is better within the range. By performing the heat treatment in an atmosphere containing an ammonia gas, a region 5 in which nitrogen in the ammonia gas is diffused is also formed in the exposed gate oxide film and the gate oxide film near both ends under the gate electrode 4. Further, the surface of the gate electrode is oxidized by the heat treatment in an atmosphere containing oxygen. The heat treatment in an atmosphere containing oxygen may be performed in a normal diffusion furnace, but rapid heating by a lamp heating device is more suitable. FIG. 1D shows a case where an N-type element such as arsenic is implanted into the gate electrode and the source and drain regions of the transistor by ion implantation in the case of NMOS. In the case of a PMOS, a P-type element such as BF2 may be implanted into the gate electrode and the source and drain regions of the transistor by ion implantation.

(Embodiment 2) FIG. 3 shows a method of manufacturing a polycide gate NMOS transistor according to the present invention in which a gate electrode has a laminated structure of polycrystalline silicon and a silicide film. FIG. 3 (a) shows a gate oxide film 2 having a thickness of 50 to 500 angstroms formed on a P-type silicon substrate 1, a polycrystalline silicon film 3 formed thereon, and a silicide such as WSix or TiSix formed thereon. This shows a step of forming the film 8.

The polycrystalline silicon film 3 has a thickness of 1000 to 300.
The thickness is 0 Å, and the silicide film 8 has a thickness of 1000 to 3000 Å. Since the crystal grains of the polycrystalline silicon film 3 become large in the subsequent heat treatment step and the shape of the gate electrode 4 deteriorates, it is preferable not to dope impurities in this step. FIG. 3B shows a step of forming a gate electrode 4 by photolithography and etching of the polycrystalline silicon film 3 and the silicide film 8 on the gate oxide film. FIG. 3 (c) shows a heat treatment step in an atmosphere containing ammonia gas and a heat treatment step in an atmosphere containing oxygen. These heat treatment steps may be performed in a usual diffusion furnace, but rapid heating by lamp heating is more suitable. In case of lamp heating, 700 ° C. for crystal stabilization and stress relaxation of silicide film
After heating once, it is preferable to diffuse the ammonia into the gate oxide film by heating to a temperature in the range of 1000 to 1200 ° C. By performing the heat treatment in an atmosphere containing an ammonia gas, a region 5 in which nitrogen in the ammonia gas is diffused is formed in the gate oxide film near both ends under the gate electrode 4.
In addition, only the exposed portions of the gate electrode 4 where the polycrystalline silicon film is easily oxidized are oxidized by the heat treatment in an atmosphere containing oxygen. This heat treatment in an atmosphere containing oxygen may be performed in a normal diffusion furnace, but rapid heating by lamp heating is more suitable. FIG. 3 (d) shows that in the case of NMOS, an N-type element such as arsenic (As) is implanted into the gate electrode made of polycrystalline silicon and silicide and the source and drain regions of the transistor by ion implantation. In the case of a PMOS, a P-type element such as BF2 may be implanted into the gate electrode and the source and drain regions of the transistor by ion implantation. (Embodiment 3) FIG. 4 shows the case where the present invention is applied to an EEPROM. The EEPROM has two states, ie, the state in which electrons are accumulated in the floating gate 10 from the semiconductor substrate and the state in which electrons are extracted from the floating gate to the semiconductor substrate through the gate oxide film 9 having a thin oxide film region. Store by threshold. Generally, the interface between the polycrystalline floating gate electrode and the gate oxide film is significantly deteriorated compared to the interface between the semiconductor substrate and the gate oxide film which are single crystals. Therefore, the number of times of rewriting of the EEPROM is determined by the deterioration characteristic of the interface between the floating gate electrode which is a crystal and the gate oxide film. In the present invention, since the ammonia treatment is performed after the formation of the floating gate electrode, the characteristics of the interface between the floating gate electrode and the gate oxide film are also improved. EEPROM and Flash
In the case of a device such as an EEPROM in which a current is positively applied to the gate oxide film, it is more effective to use the conventional ammonia treatment before forming the gate electrode.

[0008]

When a MOS transistor is deteriorated by hot carriers, hot carriers are trapped in an oxide film near an interface between a semiconductor substrate near a drain electrode and a gate oxide film, and a trap level is generated at the interface. This causes an increase in the threshold value of the MOS transistor and a decrease in the driving capability. MOS formed as in the present invention
In the type transistor, the entire surface of the gate oxide film is not exposed to ammonia gas as in the prior art. However, as described above, the vicinity of the drain electrode, which is a deteriorated portion of the MOS transistor due to hot carriers, is subjected to heat treatment in an ammonia gas atmosphere. Since the characteristics of the gate oxide film and the interface near the interface between the oxide film and the semiconductor substrate are improved, deterioration due to hot carriers can be reduced. In addition, since there is no process from the formation of the gate oxide film to the formation of the gate electrode, quality deterioration due to particles can be minimized. Also, devices such as EEPROMs and Flash EEPROMs that accumulate and release charges from the floating gate electrode are exposed to an ammonia gas atmosphere after the formation of the gate electrode, so that not only the interface between the gate oxide film and the semiconductor substrate but also the gate oxide film The characteristics of the gate electrode interface are also improved, and the number of times of rewriting is improved.

[Brief description of the drawings]

FIG. 1 shows a polysilicon gate NMOS according to the present invention.
FIG. 4 is a diagram showing a method of manufacturing a type transistor in the order of steps.

FIG. 2 illustrates a prior art transistor.

FIG. 3 is a diagram showing a method of manufacturing a polycide gate NMOS transistor having a laminated structure of a polycrystalline silicon and a silicide film according to the present invention in the order of steps.

FIG. 4 is a cross-sectional view when the present invention is applied to an EEPROM.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 Gate oxide film 3 Polycrystalline silicon film 4 Gate electrode 5 Region in which nitrogen is diffused 6 N-type drain 7 N-type source 8 Silicide film 9 Gate oxide film having thin oxide film region 10 Floating gate electrode 11 Control gate electrode

Claims (1)

[Claims] In a method for manufacturing a MOS transistor, a step of forming a gate oxide film, a step of depositing a gate electrode film on the gate oxide film, and processing the gate electrode film by photolithography and etching to form a gate. A method of manufacturing a MOS transistor, comprising: a step of forming an electrode; a step of heat-treating in an ammonia gas atmosphere; a step of heat-treating in an oxygen atmosphere; and a step of doping impurities into source, drain and gate electrodes by ion implantation. .