JP2003282473A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the depth of a junction by suppressing excessively rate- increased diffusion when a shallow junction is formed in the manufacturing process of a MOSFET. <P>SOLUTION: A semiconductor substrate after ion implantation is exposed to high-density plasma and then subjected to heat treatment for activation. When the semiconductor substrate is exposed to the high-density plasma, a temperature becomes high only on the extreme surface of the substrate and quickly drops along the thickness of the substrate, so that this property is used to repair a spot defect with heat generated on the surface without advancing diffusion. Activating heat treatment is carried out after the spot defect is repaired, and since the diffusion along the thickness is not advanced by the excessively rate-increased diffusion, the junction which has exact desired thickness can be formed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a shallow junction (shallow junction) of an impurity diffusion layer which constitutes a semiconductor element.

[0002]

2. Description of the Related Art MOSFET (Metal Oxide Semiconducer)
With the miniaturization of the tor field-effect transistor, the source / drain diffusion layer is shallow in the region near the gate electrode,
"Double drain structure" that deeply forms other regions
Is being considered. In this structure, the shallow diffusion layer region near the gate electrode is called an extension region. In order to suppress the short channel effect and prevent the driving ability from decreasing, the extension region must be as shallow as possible and the resistance value between the source and the drain must be kept low.

As a method for forming the diffusion layer region, an impurity is generally introduced into the region to be the diffusion layer region by ion implantation, and then heat treatment is performed to activate the impurity. However, it is known that in ion implantation, various crystal defects such as vacancies and interstitial silicon atoms are generated in a silicon substrate due to nuclear collision between ions and a crystal lattice. In particular, interstitial silicon atoms combine with the introduced impurities, and when heat treatment is performed, they diffuse with a diffusion coefficient that is thousands to tens of thousands times the equilibrium diffusion coefficient. Therefore, even if impurities are introduced only in a relatively shallow region at the stage of ion implantation, diffusion may deepen during heat treatment. This phenomenon is caused by excessively enhanced diffusion (TED).
It is known as Enhanced Diffusion) and is known as a problem in shallow junction formation.

As a method for solving this problem,
Japanese Patent Laid-Open No. 11-176765 discloses a method of recovering a damaged substrate by irradiating the substrate after ion implantation with an electron beam. However, introducing a new apparatus for electron beam irradiation into the manufacturing line and adding a new step to the manufacturing process leads to an increase in manufacturing cost and production period, and is not a realistic solution. .

Another problem at the time of forming the shallow junction is outward diffusion of impurities. When forming a shallow junction, impurities are introduced only into the surface layer of silicon in the ion implantation process. When high-temperature heat treatment for activating the impurities in such a distribution state is performed, outward diffusion of the impurities in the surface layer occurs, and the impurity concentration decreases. Conventionally, this problem is
This has been solved by forming a protective insulating film on the wafer for the purpose of preventing outward diffusion.

[0006]

DISCLOSURE OF THE INVENTION The present invention provides a MOSFE
It is an object of the present invention to suppress excessive accelerated diffusion when a shallow junction is formed in the manufacturing process of T so that the depth of the junction can be controlled. As a result, a shallow junction forming technology, that is, a core technology of a fine MOSFET forming technology is established, and a high-performance semiconductor device with stable operation can be supplied.

[0007]

SUMMARY OF THE INVENTION The present invention introduces an ion implantation step of introducing impurities into a predetermined region of a semiconductor substrate by ion implantation, and a high density plasma treatment step of exposing the semiconductor substrate to high density plasma. And a heat treatment step for activating the impurities. The density of high density plasma is 1
It is preferably x10 ¹² or more.

When a semiconductor substrate is exposed to high-density plasma, only the extreme surface of the substrate becomes hot, and the temperature rapidly drops in the depth direction of the substrate. By utilizing this property, the point defect can be repaired by the heat generated on the surface without promoting the diffusion inside the substrate. If the activation heat treatment is performed thereafter, excessive accelerated diffusion does not occur and the junction depth can be controlled as desired.

Further, in the high-density plasma processing step, if an insulating film is formed on the surface of the semiconductor substrate using a high-density plasma CVD apparatus or the like, it is possible to prevent outward diffusion during heat treatment. For example, silane gas is used as a reaction gas, and an insulating film mainly containing silicon oxide is formed.

Further, in the ion implantation step, if the acceleration voltage at the time of ion implantation is set to 1 KeV or less, the impurities are relatively shallowly implanted and a shallow junction can be formed. In the present invention, since the point defects are removed by the high-density plasma treatment, there is no concern that the junction will be deepened by the heat treatment even if the ion implantation is performed with low energy.

In the ion implantation step, the dose of impurities is 1 × 10 ¹³ / cm ² to 1 × 10 ¹⁶ / c.
It is preferable to carry out the ion implantation so that it is within the range of m ² . This is because it is necessary to increase the impurity concentration to some extent to keep the resistance value low, but on the other hand, too high a concentration is not enough to keep the junction shallow.

By using the manufacturing method described above, even when the junction depth of the impurity-doped region is 0.1 μm or less,
The depth can be freely controlled, and a high quality and high performance semiconductor device can be manufactured relatively easily.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A to 1D show stepwise cross-sections of the semiconductor substrate in the shallow junction forming step. In the present embodiment, the shallow junction is formed as follows.

First, as shown in FIG. 1A, an oxide film 2 for element isolation is formed on an N-type silicon substrate 1. Next, a 4 nm gate oxide film 3 is formed in each element region, and channel doping is performed. After that, 200n of polysilicon
Then, the gate electrode 4 is formed by dry etching. After that, an oxide film is deposited and the sidewalls 5 are formed by etching back. Since the above is the same as the conventional one, detailed description will be omitted.

Next, after removing the natural oxide film (not shown) using an HF-based etching solution, the sidewall 5 is formed.
Ion implantation is performed on the regions to be the source / drain regions by using the gate electrode 4 with the mask formed as a mask. As a result, as shown in FIG. 1B, the impurity introduction regions 6 to be the source / drain regions are formed. In the present embodiment, the ion implantation is performed by using a low energy ion implanter, and a low molecular weight molecule containing boron (for example, BF ₃ molecule).
The ionized B ⁺ ions are accelerated with an energy of 500 eV and implanted. The elemental ions to be implanted are arsenic (A
s ⁺ ), phosphorus (P ⁺ ), boron fluoride (BF ₂ ⁺ ) and the like may be used. Further, the ion implantation is performed on the impurity introduction region 6,
1 × 10 ¹³ to 1 × 10 ¹⁶ per unit area [cm ² ]
This is done so that individual ions are implanted.

In the conventional method, an oxide film (hereinafter referred to as a cap oxide film) is formed on the surface of the silicon substrate to prevent outward diffusion. When the ion implantation is performed at a low energy of 1 KeV or less, the implantation depth is 50n.
Since it is relatively shallow as about m, impurities are diffused outward during the heat treatment as described above. This is because if the impurity concentration of the surface layer of the silicon substrate decreases due to the out-diffusion, the resistance of the diffusion layer increases, which is to be prevented. For forming the oxide film, an apparatus capable of forming a film at a low temperature, for example, a parallel plate type plasma CVD apparatus or a normal pressure / quasi-normal pressure type thermal CVD apparatus is usually used. The film forming temperature is generally about 400 ° C. The heating is performed using a resistance heater built in the susceptor of the CVD device. As a result, the wafer surface temperature during film formation can be maintained at 400 ° C. or lower.

On the other hand, in this embodiment, the parallel plate type plasma CVD apparatus and the normal pressure
High-density plasma CV instead of the quasi-atmospheric pressure type thermal CVD device
Use device D. The high-density plasma CVD apparatus is an apparatus for converting a gas introduced into a chamber into a high-density plasma and reacting with a wafer to deposit a film.
ductively Coupled Plasma) method,
Various devices such as an ECR (Electron Cyclotron Resonance) system and a system using a special magnetic field are known.

Since the feature of the method of the present invention is that the surface of the wafer after ion implantation is exposed to high-density plasma, it is not always necessary to use a CVD apparatus to generate high-density plasma. However, as in this embodiment,
If a high density plasma CVD apparatus is used, point defects can be removed and a cap oxide film can be formed at the same time.

First, the mechanism of removing point defects by the high density plasma CVD apparatus will be described. The high density plasma CVD process is generally a process that combines chemical reaction and physical sputtering. For example I
In the CP type apparatus, first, inductively coupled plasma is generated, and radio frequency (RF) energy (bias) is applied to the reaction region near the surface of the wafer to accelerate the dissociation of the reaction gas to generate highly reactive ion species. Generate plasma. This plasma reacts with the wafer to deposit a film (chemical reaction). These treatments are performed in vacuum or in an inert gas such as argon (Ar) or helium (He). Relatively inactive ionic components such as argon and helium are given high momentum (electric field) by applying RF bias, and the thin film material to be deposited is selected from a specific region along the cross-sectional shape of the thin film based on the sputtering rate curve. It (physical sputtering). This provides in situ sputtering and / or ion directionality during processing. The application of the RF bias is not essential for forming the thin film, but the RF bias may be applied in order to improve the step coverage of the formed thin film.

Here, when an RF bias is applied, the ions collide with the surface of the wafer to generate heat. Therefore, high-density plasma CVD is used in the general wiring process.
When using a process, cooling helium may be flowed to the wafer interface in order to suppress the heat generated. On the other hand, when the RF bias is made extremely weak or not applied, collision of relatively inert ion components such as argon and helium with the wafer is reduced.

In this embodiment, the plasma density is set to 1 × 1.
The high density plasma CVD process is performed in a vacuum under the conditions of 0 ¹² or more, no RF bias is applied, and no positive cooling by He is performed. The wafer temperature in this case was about 400 ° C. as measured by a radiation thermometer on the back surface. The temperature measured on the back surface is not necessarily the same as the temperature on the outermost surface, because the heat generated on the outermost surface is diffused and the entire wafer is heated and can be observed. It is clear that the temperature will rise.

The point defects caused by the ion implantation are considered to be repaired by the heat of this high density plasma. However, this heat does not cause diffusion in the thickness direction of the wafer. This is presumably because the heat of the high-density plasma is generated only on the extreme surface of the wafer, and the temperature rapidly decreases in the thickness direction of the wafer. If you take advantage of this property,
The point defect can be repaired without promoting diffusion in the thickness direction.

In the present embodiment, silane gas (SiH ₄ , Si ₂ H ₆ , Si ₃ H _8, etc.) is used as the reaction gas.
To use. As a result, as shown in FIG. 1C, a 200-nm-thick cap oxide film 7 mainly composed of silicon oxide is formed on the wafer, and as in the prior art, it is possible to prevent outward diffusion of impurities during heat treatment. it can.

In this embodiment, the oxide film is formed without applying the RF bias. However, after forming the oxide film to a certain thickness, the RF bias is applied to incorporate the sputtering effect. May be. When the sputtering is performed, the substrate surface temperature becomes higher, so that the annealing effect can be expected.

By the high-density plasma CVD process described above, it is possible to remove the point defects of the wafer generated at the time of ion implantation and to form the cap oxide film for outward diffusion.

Next, in order to activate the impurities introduced into the wafer, in an inert gas (or in vacuum),
Heat treatment is performed using a lamp. The mainstream in recent years is to increase the temperature to a maximum temperature by using a rapid thermal processing (RTP: Rapid Thermal Processing) apparatus while keeping the temperature of the wafer surface uniform and at a maximum applicable heating rate. It is a method of lowering the temperature as soon as it reaches. This heat treatment is shown in a graph of temperature change with time on the horizontal axis and temperature on the vertical axis as shown in FIG.
It is called “spike annealing” because it has a wedge shape as shown in FIG. Maximum heat treatment temperature is 1050
Set to ℃. As a result, P-type source / drain regions 8 are formed as shown in FIG.
A transistor is formed.

FIG. 2 shows the total amount of boron after boron injection is S
It is the result of measurement using IMS (Secondary Ion Mass Spectrometry). The position on the wafer surface where the measurement shown in the figure is performed is the central portion of the wafer. In the figure, III is a SIMS depth profile immediately after boron implantation and before heat treatment. Graph I shows the case where the heat treatment is performed after forming the cap oxide film using this method. For comparison, II shows the distribution when the cap oxide film is formed by using the parallel plate type plasma CVD method. From the figure, in the distribution of carrier concentration in a conventional manner, the concentration is the depth to be 1.0 × 10 ^{1 8} was about 53 nm, by using the present method, the formation of about 46 nm, a shallower junction I know that I can do it.

FIG. 3 is a diagram showing the result of measurement of the layer resistance distribution after heat treatment using the four-short needle method. Figure 3
3A shows a case where a cap oxide film is formed using a high density plasma CVD apparatus, and FIG. 3B shows a resistance distribution when a cap oxide film is formed using a parallel plate type plasma CVD apparatus. Shows. Parallel plate type plasma C
When the cap oxide film is formed by using the VD apparatus, the layer resistance is poor in the in-plane uniformity of the wafer, and the layer resistance tends to increase toward the peripheral portion of the wafer. When compared in terms of absolute value, it is about half that in the case of using high density plasma CVD. That is, even if the plasma density is high, the annealing effect on the surface of the semiconductor substrate cannot be obtained in the parallel plate type plasma CVD apparatus in which the plasma density is at most 1 × 10 ¹¹ or less. On the other hand, according to the high density plasma CVD process, the uniform diffusion layer resistance can be obtained as described above.

Further, the method of the present embodiment can be realized only by replacing the parallel plate type plasma CVD apparatus conventionally used for forming the cap oxide film with a high density plasma CVD apparatus. Since there is no need to develop a new device or add a new process, it is possible to supply high-performance and high-quality semiconductor devices at lower cost than before without increasing cost and construction period. You can

In the present embodiment, the plasma density is set to 1 × 10 ¹² or more, but this value is merely a guideline, and it may be possible for a person skilled in the art to remove point defects even if the value is slightly lower. Is obvious to In addition, the above-described embodiment is called a high density plasma CVD process.
It is particularly excellent in that the point defect can be removed by one process and the insulating film (cap oxide film) can be formed at the same time (the number of steps does not increase compared to the conventional method), but the feature of the present invention is that the high density plasma treatment The insulating film may be formed by another process because it is to remove defects. In addition, the type of the insulating film and the type of the reaction gas for forming the insulating film are not limited to the silane gas, and various other types may be considered.

[0031]

In the method of the present invention, the semiconductor substrate after ion implantation is exposed to high density plasma to remove the point defects on the substrate surface. As a result, the TED phenomenon can be suppressed, the depth of the junction to be formed can be controlled as desired, and the shallow junction can be easily formed.

[Brief description of drawings]

FIG. 1 is a diagram showing, step by step, a cross section of a semiconductor substrate in a shallow junction forming step.

FIG. 2 is a diagram showing a boron distribution of an impurity introduced layer after activation heat treatment.

FIG. 3 is a diagram showing a resistance distribution of an impurity introduced layer after activation heat treatment.

FIG. 4 is a diagram showing an example of a temperature profile of spike annealing.

[Explanation of symbols]

1 silicon substrate, 2 oxide film, 3 gate oxide film, 4 gate electrode, 5 sidewall, 6 impurity introduction region, 7 cap oxide film, 8 source / drain region.

Claims (7)

[Claims] 1. An ion implantation step of introducing impurities into a predetermined region of a semiconductor substrate by ion implantation; a high-density plasma treatment step of exposing the semiconductor substrate to high-density plasma; and activating the introduced impurities. The method for manufacturing a semiconductor device, comprising: 2. The density of the high density plasma is 1 × 10.
^The method for manufacturing a semiconductor device according to claim 1, wherein the number is ¹² or more. 3. In the high density plasma processing step,
3. The method of manufacturing a semiconductor device according to claim 1, wherein an insulating film is formed on the surface of the semiconductor substrate. 4. In the high density plasma processing step,
4. The method for manufacturing a semiconductor device according to claim 1, wherein silane gas is used as the reaction gas. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the ion implantation step, an acceleration voltage during ion implantation is set to 1 KeV or less. 6. In the ion implantation step, impurities of
Dose amount is 1 × 10 ^ThirteenPieces / cm^TwoFrom 1 × 10¹⁶Individual
/ Cm^TwoIon implantation should be performed within the range of
The semiconductor device according to any one of claims 1 to 5, which is characterized in that
Manufacturing method. 7. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1, wherein the junction depth is 0.1.
A semiconductor device having an impurity introduction region of μm or less.