CN101620995A - Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof - Google Patents
Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a method for forming a gate dielectric layer, which comprises the following steps: providing a substrate which is provided with a silicon oxide layer; and executing nitriding process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer, wherein the nitriding process at least comprises a step of ion implantation nitriding process. The invention also provides the gate dielectric layer, a semiconductor device and a manufacturing method thereof. The method can adjust the distribution of nitrogen in the gate dielectric layer according to requirements.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a grid dielectric layer and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.
Background
Since the invention of metal oxide semiconductor transistor, silicon oxide has been used as the most important material of gate dielectric layer due to its good integration characteristics with silicon and polysilicon. With the improvement of integration level, the size of the gate electrode is smaller and smaller, correspondingly, the thickness of the silicon oxide layer serving as the gate dielectric layer also needs to be thinned continuously, and the requirements on film layer characteristics such as thickness uniformity, defect control, breakdown resistance and the like of the formed silicon oxide layer are higher and higher, so that higher requirements are provided for the manufacturing process of the silicon oxide layer, and the gate dielectric layer formed by the existing method for manufacturing the silicon oxide cannot meet the requirements of technical nodes at 90nm and below on the electrical characteristics of the gate dielectric layer.
U.S. patent No. US 6555485B 1 discloses a method of forming a gate dielectric layer. Fig. 1 to fig. 3 are schematic cross-sectional views corresponding to the steps of the method for forming a gate dielectric layer disclosed in the U.S. patent.
Referring to fig. 1, a semiconductor substrate 100 is provided, and a silicon oxide layer 200 is formed on the semiconductor substrate 100.
Next, referring to fig. 2, a Nitridation process is performed on the surface of the silicon oxide 200 to dope nitrogen into the silicon oxide layer 200 to form a silicon oxynitride layer 300, wherein the Nitridation process performed on the surface of the silicon oxide 200 is Plasma Nitridation (Plasma Nitridation).
Then, a high temperature annealing process is performed on the silicon oxynitride layer 300, as shown in fig. 3, the silicon oxynitride layer 300 is exposed to an oxygen or nitric oxide 400 atmosphere, and an annealing process is performed at a high temperature of 600 to 1000 degrees.
According to the method, the gate dielectric layer is formed through an oxidation process, a nitridation process and an annealing process, and the formed silicon oxide layer contains nitrogen, so that the breakdown resistance of the silicon oxide layer can be improved.
In the method, nitrogen is doped into the silicon oxide layer by plasma nitridation to form a nitrogen-containing silicon oxide layer. However, the plasma nitridation process cannot control the distribution of nitrogen incorporated into the silicon oxide layer, and thus cannot purposefully form a distribution of nitrogen-containing silicon oxide. And thus semiconductor devices having different characteristics cannot be formed.
Disclosure of Invention
The invention provides a grid dielectric layer and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof.
The invention provides a method for forming a grid dielectric layer, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a silicon oxide layer;
performing a nitridation process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer;
wherein,
the nitridation process at least comprises one step of ion implantation nitridation process.
Optionally, before performing the ion implantation nitridation process, a buffer layer is formed on the silicon oxide layer; and removing the buffer layer after performing the ion implantation nitridation process.
Optionally, the buffer layer is silicon nitride or silicon carbide or other dielectric layers.
Optionally, the nitridation process is performed in two steps, wherein the second step is the ion implantation nitridation.
Optionally, the first step nitridation process is one of high temperature furnace tube nitridation, rapid thermal processing nitridation, low temperature plasma nitridation or decoupled plasma nitridation.
Optionally, the ion implantation nitridation process is performed in multiple steps.
Optionally, the energy of the ion implantation nitridation process during implantation is less than 10 eV.
Optionally, the energy of implantation in the ion implantation nitridation process is 4 eV.
Optionally, further comprising: and performing an annealing process on the silicon oxide layer subjected to the nitridation process.
Optionally, the annealing process is high-temperature furnace tube annealing or rapid thermal annealing.
The present invention also provides a method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a silicon oxide layer on the substrate;
performing a nitridation process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer;
forming a gate electrode on the nitrogen-containing silicon oxide layer;
forming a side wall layer on the side wall of the grid electrode, and forming a source electrode and a drain electrode in the substrate on the side wall of the grid electrode; wherein,
the nitridation process at least comprises one step of ion implantation nitridation process.
Optionally, before the ion implantation nitridation process is performed, a buffer layer is formed on the silicon oxide layer, and after the ion implantation nitridation process is performed, the buffer layer is removed.
Optionally, the energy of the ion implantation process during implantation is less than 10 eV.
The invention also provides a grid dielectric layer which comprises a silicon oxide layer, wherein impurity nitrogen is doped in the silicon oxide layer, and the silicon oxide layer is subjected to at least one time of ion implantation nitridation treatment.
The invention also provides a semiconductor device comprising the grid dielectric layer.
Compared with the prior art, one of the technical schemes has the following advantages:
by the ion implantation nitridation process, the concentration of doped nitrogen can be flexibly controlled, and the concentration distribution of nitrogen can be controlled, so that films with different electrical characteristics can be formed as gate dielectric layers as required; the film characteristics of the formed grid dielectric layer are improved, and the electrical characteristics of the formed device are improved;
another of the above technical solutions has the following advantages:
when the ion implantation nitridation process is carried out, in order to prevent implanted nitrogen ions from penetrating through the silicon oxide layer and influencing the film layer characteristics of the formed grid dielectric layer, the buffer layer is formed as a protective layer before the ion implantation process is carried out, so that the speed of the implanted ions is reduced, the phenomenon that the ions penetrate through the silicon oxide layer is avoided or reduced, and the grid dielectric layer with more stable electrical performance is formed; removing the buffer layer after the ion implantation nitridation process is completed; the formed gate dielectric layer is not affected;
another of the above technical solutions has the following advantages:
before the ion implantation nitridation process is carried out, a first step of nitridation process is carried out to form a silicon oxynitride layer as a buffer layer, the silicon oxynitride layer is used for slowing down the speed of ions implanted in the ion implantation process, the phenomenon that the ions penetrate through the silicon oxide layer is avoided or reduced, and a grid dielectric layer with more stable electrical performance is formed; moreover, the silicon oxynitride layer is used as a buffer layer, and is not required to be removed after the ion implantation nitridation process is performed, and the silicon oxynitride layer can be used as a part of a gate dielectric layer after being annealed, so that the process is simplified;
another of the above technical solutions has the following advantages:
in order to prevent ions injected during ion implantation from penetrating through the silicon oxide layer, the energy during the ion implantation nitridation process can be less than 10eV, so that the phenomenon that the ions penetrate through the silicon oxide layer is avoided or reduced, and the formation of a grid dielectric layer with more stable electrical properties is facilitated.
Drawings
FIGS. 1 to 3 are schematic cross-sectional views illustrating the corresponding structure of the steps of a conventional method for forming a gate dielectric layer;
FIGS. 4 to 5 are schematic cross-sectional views illustrating the corresponding structures of the steps of the method for forming a gate dielectric layer according to the first embodiment of the present invention;
FIGS. 6 to 8 are schematic cross-sectional views illustrating the corresponding structures of the steps of the method for forming a gate dielectric layer according to the third embodiment of the present invention;
FIGS. 9 to 11 are schematic cross-sectional views illustrating the corresponding structures of the steps in the fourth embodiment of the method for forming a gate dielectric layer according to the present invention;
fig. 12 is a flowchart of an embodiment of a method of manufacturing a semiconductor device of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
With the increasing development of semiconductor integrated circuit manufacturing processes, the size of a grid electrode is smaller, the thickness of a grid electrode dielectric layer is thinner, the requirements on the thickness uniformity and the electrical characteristics of the grid electrode dielectric layer are higher, and the requirement on the increasing improvement of the device performance cannot be met by using single silicon oxide as a grid electrode dielectric layer material. The invention provides a method for manufacturing a silicon oxide layer containing nitrogen as a grid dielectric layer, and the content and distribution of nitrogen in the silicon oxide layer can be adjusted and controlled according to requirements.
The invention also provides a grid dielectric layer which is obtained by the manufacturing method of the nitrogen-containing silicon oxide.
The invention also provides a manufacturing method of the semiconductor device, wherein in the manufacturing method of the semiconductor device, the grid dielectric layer is obtained by the manufacturing method of the nitrogen-containing silicon oxide.
The invention also provides a semiconductor device which comprises the grid dielectric layer provided by the invention.
The method for fabricating the gate dielectric layer according to the present invention will be described in detail with reference to the following embodiments.
Example one
Fig. 4 to 5 are schematic cross-sectional views of structures corresponding to steps of the method for manufacturing a gate dielectric layer according to the first embodiment of the present invention.
Referring to fig. 4, first, a substrate 10 is provided, and a silicon oxide layer 12 is formed on the substrate 10.
The substrate 10 may be a semiconductor material, such as one of monocrystalline Silicon, polycrystalline Silicon, or amorphous Silicon, and may also be a Silicon On Insulator (SOI) structure or an epitaxial layer On Silicon (epi) structure. An N-type impurity or a P-type impurity may be doped in the substrate 10.
The silicon oxide layer 12 may be formed by a method including, but not limited to, high temperature furnace oxidation, rapid thermal annealing oxidation, or in-situ steam-generated oxidation (ISSG) process.
Before the silicon oxide layer 12 is formed on the substrate 10, optionally, the surface of the substrate 10 may be pre-cleaned to remove a native oxide layer or other contaminants, impurities, particles, etc. on the surface of the substrate 10. This is because the substrate 10 is exposed to air to form a native oxide layer on the surface, the native oxide layer has poor thickness uniformity and film properties, and the native oxide layer needs to be removed to avoid the influence of the native oxide layer on the film properties of the subsequently formed gate dielectric layer and the adhesion of the gate dielectric layer to the substrate 10. Typical removal methods are wet etching, such as BOE or HF or RCA cleaning, etc.
After the cleaning is performed, an oxidation process is performed to form the silicon oxide layer 12. In one embodiment, the process of forming the silicon oxide layer 12 is an ISSG process.
The ISSG is a wet oxidation process which is different from the existing wet oxidation process that hydrogen is combusted in oxygen to generate water vapor and the water vapor is introduced into a reaction chamber;
ISSG converts hydrogen and oxygen (or N)2O) is led into a reaction chamber according to a certain proportion and reacts on the high-temperature surface of the substrate in the reaction chamber to generate H2O, OH and oxygen atoms that react with the substrate surface to form the silicon oxide layer 12.
The oxidation rate of the ISSG has a large relation with the content of oxygen atoms in the reaction chamber, the oxidation rate of the ISSG can be controlled by controlling the content of the oxygen atoms, and nitrogen or other inert gases can be introduced into the ISSG oxidation process to be used as a diluent gas, and gases containing Cl can also be introduced into the ISSG oxidation process to be used as an auxiliary gas, so that the reaction rate is relatively increased. The ISSG process can form a silicon oxide layer with uniform thickness and good film layer characteristics.
It should be noted that the silicon oxide layer 12 may also be formed by other processes, including an oxidation process or a deposition process, which are not described herein again.
Next, the silicon oxide layer 12 is nitrided to form a silicon oxide layer 13 containing nitrogen, as shown in fig. 5.
The nitrogen impurity is doped into the silicon oxide layer 12 to serve as a gate dielectric layer, so that the tunnel leakage current from a subsequently formed gate to the substrate 10 can be reduced, doped ions in the gate are prevented from penetrating through the gate dielectric layer, and the breakdown voltage of the formed gate dielectric layer is improved, so that the performance and the stability of a formed device are improved.
In the conventional method, the nitridation process for the silicon oxide layer 12 is generally performed by high temperature furnace tube nitridation or rapid thermal annealing nitridation, or plasma nitridation. None of the nitridation processes described herein controls the distribution of nitrogen in the silicon oxide layer 12, which affects the electrical characteristics of the gate dielectric layer formed.
In this embodiment, an ion implantation nitridation process is adopted, that is, nitrogen is doped into the silicon oxide layer by the ion implantation process, as shown in fig. 5, a nitrogen-containing silicon oxide layer 13 is formed, and the nitrogen-containing silicon oxide layer 13 is a gate dielectric layer of a device to be formed subsequently. The ion implantation process can adjust and control the concentration profile incorporated into the silicon oxide layer by adjusting the energy and dose at the time of ion implantation.
In an ion implantation process, the substrate 10 is placed in a reaction chamber of an ion implantation apparatus, and a reaction gas, for example, N2 or other nitrogen-containing gas, is introduced into the reaction chamber. The reaction gas is ionized by excitation of radio frequency or microwave to generate plasma, and the plasma is accelerated and injected into the silicon oxide layer 12.
Therefore, the concentration of doped nitrogen can be flexibly controlled through the ion implantation nitridation process, the concentration distribution of the nitrogen can be controlled, and films with different electrical characteristics can be formed as gate dielectric layers according to requirements. The method is beneficial to improving the film characteristics of the formed grid dielectric layer and the electrical characteristics of the formed device.
After the ion implantation process is finished, performing an annealing process on the nitrogen-containing silicon oxide layer to redistribute nitrogen in the silicon oxide layer and combine the nitrogen and silicon or oxygen into Si-N or O-N bonds; next, ion implantation damage to the silicon oxide layer 12 caused in the ion implantation process is repaired. The annealing process may be a high temperature furnace annealing process or a rapid thermal annealing process known to those skilled in the art, and will not be described herein.
Example two
The nitrogen in the silicon oxide layer may not reach the required distribution through one ion implantation nitridation process, which may be performed in multiple steps in this embodiment. Optionally, in each ion implantation nitridation process, the implantation energy or the implantation dose is different, or both the implantation energy and the implantation dose are different, so as to form a silicon oxide layer with a nitrogen concentration profile meeting requirements. And will not be described in detail herein.
EXAMPLE III
With the continuous progress of the semiconductor manufacturing process, the thickness of the grid dielectric layer is thinner and thinner; accordingly, the thickness of the silicon oxide layer is also reduced when forming the gate dielectric layer of the nitrogen-containing silicon oxide layer, for example, at a technology node of 65nm, the thickness of the silicon oxide layer is only 12A, and at 45nm, the thickness of the silicon oxide layer is thinner. When the thin silicon oxide layer is subjected to an ion implantation nitridation process, implanted nitrogen ions penetrate through the silicon oxide layer, thereby affecting the film characteristics of the formed gate dielectric layer. In this embodiment, a buffer layer (buffer layer) is formed on the silicon oxide layer to be doped to improve the problem of nitrogen ions penetrating the silicon oxide layer.
Fig. 6 to 8 are schematic cross-sectional views illustrating respective structures of steps of a method for manufacturing a gate dielectric layer according to a third embodiment of the present invention.
Referring to fig. 6, a buffer layer 16 is formed on a substrate 10 having a silicon oxide layer 12.
The buffer layer 16 is used to slow down the velocity of the implanted ions when the silicon oxide layer 12 is subjected to ion implantation nitridation, so as to prevent the implanted ions from penetrating through the silicon oxide layer 12 and reduce the damage to the silicon oxide layer 12 caused by the implanted ions.
When selecting the material and thickness of the buffer layer 16, it is first ensured that the implanted ions can penetrate or a part of the ions can penetrate the buffer layer 16 and reach the silicon oxide layer 12; secondly, it is also ensured that the velocity of the ions can be slowed down, so that the energy of the implanted ions is reduced.
In one embodiment, the buffer layer 16 may be a silicon nitride layer. The silicon nitride layer may be formed by a deposition process, and in particular, may be formed by a chemical vapor deposition or atomic layer deposition process.
In further embodiments, the buffer layer 16 may be silicon carbide.
It should be noted that, although the buffer layer is described by using silicon nitride or silicon carbide as a specific example, it is not limited to that the buffer layer may be made of only the above two materials, but it should be understood that the material of the buffer layer 16 may be any material capable of slowing down the velocity of the implanted ions and ensuring penetration of the ions.
After the buffer layer 16 is formed, an ion implantation nitridation process is performed on the silicon oxide layer 12, referring to fig. 7, a nitrogen-containing silicon oxide layer 13 is formed, where the nitrogen-containing silicon oxide layer 13 is a gate dielectric layer of a device to be formed later. And adjusting the energy and dosage during implantation according to the requirement to form the silicon oxide layer containing nitrogen with the concentration and distribution meeting the requirement.
Optionally, the ion implantation nitridation process may be performed in multiple steps, which is not described herein again.
After the ion implantation process is completed, the buffer layer 16 is removed, please refer to fig. 8. The method of removing the buffer layer 16 may be dry etchingOr wet etching. For example, when the buffer layer 16 is silicon nitride, dry etching may be used, and the etching gas may be a fluorine-containing gas such as CF4、SiF4、NF3、CHF3Or C2F6(ii) a Wet etching may also be used, the etching solution being phosphoric acid.
When the buffer layer 16 is removed by the above-described method, the nitrogen-containing silicon oxide layer 13 under the buffer layer 16 is prevented from being damaged as much as possible.
After the buffer layer 16 is removed, an annealing process is carried out, the nitrogen-containing silicon oxide layer 13 is subjected to the annealing process, so that nitrogen in the silicon oxide layer is redistributed, and the nitrogen and silicon or oxygen are combined into Si-N or O-N bonds; second, ion implantation damage to the silicon oxide layer 12 caused in the ion implantation process may also be repaired by the annealing process. The annealing process may be a high temperature furnace annealing process or a rapid thermal annealing process known to those skilled in the art.
In one embodiment, the annealing is performed in nitrogen and the temperature of the annealing may be 800 to 1100 degrees.
In other embodiments, the process of removing the buffer layer 16 may also be performed after annealing, and is not described herein again.
By the ion implantation nitridation process, the concentration of doped nitrogen can be flexibly controlled, the concentration distribution of the nitrogen can be controlled, and film layers with different electrical characteristics can be formed as a grid dielectric layer as required; the method is beneficial to improving the film characteristics of the formed grid dielectric layer and the electrical characteristics of the formed device.
In addition, in the ion implantation nitridation process, in order to prevent implanted nitrogen ions from penetrating through the silicon oxide layer and affecting the film characteristics of the formed gate dielectric layer, the buffer layer is formed as a protective layer before the ion implantation process is performed, the speed of the implanted ions is reduced, and the buffer layer is removed after the ion implantation nitridation process is completed.
Example four
In order to prevent the silicon oxide layer from being penetrated by the ions during the ion implantation nitridation due to the thin silicon oxide layer, before the ion implantation nitridation is performed, another nitridation process, such as a high temperature furnace nitridation process, a rapid thermal annealing nitridation process or a plasma nitridation process, may be performed on the silicon oxide layer, so as to form a silicon oxynitride layer on the surface of the silicon oxide layer, and then perform the plasma nitridation process.
In addition, in the method for forming the silicon oxide layer containing nitrogen by combining the two-step nitridation process, the plasma nitridation process is also used for further adjusting the content and distribution of nitrogen in the film layer formed by the first-step nitridation process so as to form the silicon oxide layer containing nitrogen, which meets the requirements.
This is described in detail below in conjunction with fig. 9 and 11.
Referring to fig. 9, a substrate 10 having a silicon oxide layer 12 is provided, and a first nitridation process is performed on the silicon oxide layer 12 to form a thin silicon oxynitride layer 18 on the surface of the silicon oxide layer 12.
Wherein the nitridation process includes, but is not limited to, a high temperature furnace nitridation process, a rapid thermal anneal nitridation process, or a plasma nitridation process. The Plasma Nitridation includes, but is not limited to, Low Temperature Plasma Nitridation (Low Temperature Plasma Nitridation) or Decoupled Plasma Nitridation (DPN). The low temperature Plasma Nitridation process may also be Remote Plasma Nitridation (RPN).
The first nitridation process is described below by taking DPN as an example.
In the DPN process, nitrogen-containing gas is introduced into a process chamber, wherein the nitrogen-containing gas is N2Or N is2Mixed gas with He; radio frequency is then applied to the gas to ionize it, producing nitrogen-containing ions in the process chamber.
The nitrogen-containing ions in the process chamber collide with the surface of the silicon oxide layer 12, and are implanted into the surface of the silicon oxide layer 12 or below the surface, and the implanted nitrogen reacts with oxygen or silicon in the silicon oxide layer 12 after annealing, thereby forming the silicon oxynitride layer 18.
In one embodiment, the power of the DPN RF source is 0 to 2000W, the pressure of the process chamber is 5 to 200mTorr, N2The flow rate is 100sccm to 1slm, and the time for decoupled plasma nitridation is about 1 to 120 s.
After the silicon oxynitride layer 18 is formed, referring to fig. 10, an ion implantation nitridation process is performed to implant nitrogen ions into the silicon oxide layer 12, and the content and distribution of the implanted nitrogen in the silicon oxide layer 12 are adjusted by the energy and dosage of the ion implantation, so as to form a nitrogen-containing silicon oxide layer 13 meeting the requirements, where the nitrogen-containing silicon oxide layer 13 is a gate dielectric layer of a device to be formed subsequently.
Optionally, the ion implantation nitridation process may be performed in multiple steps, which is not described herein again.
Because the silicon oxynitride layer 18 is formed before the ion implantation nitridation process is performed, the silicon oxynitride layer 18 can slow down the implantation rate during the ion implantation process, thereby avoiding or reducing the phenomenon that ions penetrate through the silicon oxide layer 12, and facilitating the formation of a gate dielectric layer with more stable electrical properties. In addition, with the silicon oxynitride layer 18 as a buffer layer, after the ion implantation nitridation process is performed, the silicon oxynitride layer 18 does not have to be removed, but is used as a part of the gate dielectric layer. Compared with the third embodiment, the process is simplified.
In addition, in the method of combining two nitridation processes in this embodiment, the ion implantation process in the second step may be considered as a supplement to the nitridation process in the first step and further adjust the content and distribution of nitrogen in the film layer formed by the nitridation process in the first step, so as to form the nitrogen-containing silicon oxide layer meeting the requirement by combining the two processes.
Next, referring to fig. 11, an annealing process is performed on the nitrogen-containing silicon oxide layer 13 to redistribute nitrogen in the silicon oxide layer and combine nitrogen with silicon or oxygen to form Si-N or O-N bonds; second, ion implantation damage to the silicon oxide layer 12 caused during the ion implantation process can also be repaired by the annealing process. The annealing process may be a high temperature furnace annealing process or a rapid thermal annealing process known to those skilled in the art.
By the ion implantation nitridation process, the concentration of doped nitrogen can be flexibly controlled, and the concentration distribution of nitrogen can be controlled, so that films with different electrical characteristics can be formed as gate dielectric layers as required; the method is beneficial to improving the film characteristics of the formed grid dielectric layer and the electrical characteristics of the formed device.
In addition, before the ion implantation nitridation process is performed, a first step nitridation process is performed to form a silicon oxynitride layer as a buffer layer, so that the implantation rate in the ion implantation process is reduced, the phenomenon that ions penetrate through the silicon oxide layer is avoided or reduced, and the formation of a gate dielectric layer with more stable electrical properties is facilitated. Moreover, the silicon oxynitride layer is used as a buffer layer, and the silicon oxynitride layer does not need to be removed after the ion implantation nitridation process is performed, and can be used as a part of the gate dielectric layer after annealing. So that the process is simplified.
In the above embodiments, in order to prevent ions implanted during ion implantation from penetrating through the silicon oxide layer, the energy during implantation in the ion implantation nitridation process may be less than 10 eV. In one embodiment, the implantation energy in the ion implantation nitridation process is 4 eV. Generally, when the density of ions in the plasma changes, the energy of the ions also changes, and the energy of the ions during implantation can be changed by a conventional method of changing the density of the plasma. Other methods of reducing the energy of the implanted ions may be used and are not described in detail herein.
The invention also provides a manufacturing method of the semiconductor device, and FIG. 12 is a flow chart of an embodiment of the manufacturing method of the semiconductor device of the invention.
Referring to fig. 12, step S100 is to provide a substrate.
Step S110 is to form a silicon oxide layer on the substrate.
Step S120 is to perform a nitridation process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer.
The nitridation process at least comprises one step of ion implantation nitridation process. The plasma nitridation process includes, but is not limited to, the processes of the first to fourth embodiments, which are not described herein again.
Step S130 is to form a gate on the nitrogen-containing silicon oxide layer.
Step S140 is to form a sidewall layer on the gate sidewall, and form a source and a drain in the substrate on the gate sidewall.
The invention further provides a gate dielectric layer, which is a nitrogen-containing silicon oxide layer, wherein the gate dielectric layer is subjected to at least one plasma nitridation, and the plasma nitridation process includes, but is not limited to, the processes in the first to fourth embodiments, and details are not repeated here.
The present invention further provides a semiconductor device, where the semiconductor device includes a nitrogen-containing silicon oxide layer as a gate dielectric layer, where the gate dielectric layer is subjected to at least one plasma nitridation, and the plasma nitridation process includes, but is not limited to, the processes in the first to fourth embodiments, for example, the semiconductor device may be a metal silicon oxide semiconductor transistor, which is not described herein again.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto, and variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.
Claims (15)
1. A method for forming a gate dielectric layer is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a silicon oxide layer;
performing a nitridation process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer;
wherein,
the nitridation process at least comprises one step of ion implantation nitridation process.
2. The method of claim 1, wherein: forming a buffer layer on the silicon oxide layer before performing the ion implantation nitridation process; and removing the buffer layer after performing the ion implantation nitridation process.
3. The method of claim 2, wherein: the buffer layer is silicon nitride or silicon carbide or other dielectric layers.
4. The method of claim 1, wherein: the nitridation process is carried out in two steps, wherein the second step is the ion implantation nitridation.
5. The method of claim 4, wherein: the first step of nitridation process is one of high-temperature furnace tube nitridation, rapid thermal processing nitridation, low-temperature plasma nitridation or decoupling plasma nitridation.
6. The method of forming a gate dielectric layer of any of claims 1 to 5, wherein: the ion implantation nitridation process is performed for multiple times.
7. The method of forming a gate dielectric layer of any of claims 1 to 5, wherein: the energy of the ion implantation nitridation process during implantation is less than 10 eV.
8. The method of claim 1, wherein: the implantation energy in the ion implantation nitridation process is 4 eV.
9. The method of forming a gate dielectric layer of any of claims 1 to 5, further comprising: and performing an annealing process on the silicon oxide layer subjected to the nitridation process.
10. The method of claim 9, wherein: the annealing process is high-temperature furnace tube annealing or rapid thermal annealing.
11. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a silicon oxide layer on the substrate;
performing a nitridation process on the silicon oxide layer to form a nitrogen-containing silicon oxide layer;
forming a gate electrode on the nitrogen-containing silicon oxide layer;
forming a side wall layer on the side wall of the grid electrode, and forming a source electrode and a drain electrode in the substrate on the side wall of the grid electrode; wherein,
the nitridation process at least comprises one step of ion implantation nitridation process.
12. The method of claim 11, wherein: before the ion implantation nitridation process is executed, a buffer layer is formed on the silicon oxide layer, and after the ion implantation nitridation process is executed, the buffer layer is removed.
13. The method of claim 11, wherein: the energy of the ion implantation process during implantation is less than 10 eV.
14. A gate dielectric layer comprising a silicon oxide layer, said silicon oxide layer being doped with impurity nitrogen, characterized in that: and the silicon oxide layer is subjected to ion implantation nitridation treatment at least once.
15. A semiconductor device, characterized in that: comprising the gate dielectric layer of claim 14.
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