CN103839983B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
- Publication number
- CN103839983B CN103839983B CN201210492757.8A CN201210492757A CN103839983B CN 103839983 B CN103839983 B CN 103839983B CN 201210492757 A CN201210492757 A CN 201210492757A CN 103839983 B CN103839983 B CN 103839983B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- gate dielectric
- nitrogen
- gate
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000007669 thermal treatment Methods 0.000 claims description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 6
- 238000010348 incorporation Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims 2
- BAXXTXHNVWVKTF-UHFFFAOYSA-N [Ge]=O.[N] Chemical compound [Ge]=O.[N] BAXXTXHNVWVKTF-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 239000004408 titanium dioxide Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 121
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 239000003085 diluting agent Substances 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XDCUQYOMECICEW-UHFFFAOYSA-N [N].O=O Chemical compound [N].O=O XDCUQYOMECICEW-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000009545 invasion Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of semiconductor devices and preparation method thereof.The semiconductor devices includes：Semiconductor substrate；Gate dielectric layer in Semiconductor substrate, the material of the gate dielectric layer is oxynitrides；Grid on the gate dielectric layer；The oxide layer of the gate lateral wall is located at least in, the material of the oxide layer is silicon oxynitride.The preparation method of the semiconductor devices includes：Semiconductor substrate is provided；The gate dielectric layer of oxynitride material is formed on the semiconductor substrate；Polysilicon gate is formed on the gate dielectric layer；The oxide layer of silicon oxy-nitride material is formed at least on the wall of the polysilicon gate side.The present invention can avoid the dielectric constant of gate dielectric layer from shifting, the final performance for improving semiconductor devices.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
The main devices of integrated circuit especially super large-scale integration are Metal-oxide-semicondutor field effect transistors
Pipe（MOS transistor）, the Key Performance Indicator of MOS transistor is driving current, and the size of driving current depends on grid capacitance,
And grid capacitance and gate surface product are directly proportional, it is inversely proportional with gate dielectric layer thickness, and with the dielectric constant of gate dielectric layer into just
Than.Gate dielectric layer thickness can not be too small, and the impurity such as boron ion otherwise mixed in grid can be from gate diffusions to Semiconductor substrate
In or be fixed in gate dielectric layer, so as to influence the threshold voltage of device.With continuing to develop for ic manufacturing technology,
The characteristic size of MOS transistor is also less and less, accordingly, and gate surface product is less and less, and the thickness of gate dielectric layer is also
Through very thin, now, grid capacitance and reduction equivalent oxide thickness are only improved by improving the dielectric constant of gate dielectric layer
Degree（EOT）.
Although can be directly using the material of high-k as gate dielectric layer, it has larger difference with existing process
Different, cost is higher, therefore in the prior art typically still using silica as gate dielectric layer, before the gate is formed, leads to
Incorporation nitrogen in silica is crossed to make fine and close silicon oxynitride to improve the dielectric constant of gate dielectric layer, and nitrogen-atoms
Incorporation can also effectively suppress diffusion of the grid doping atom such as boron in gate dielectric layer, while the technique has good with existing process
Good continuity and compatibility.
With reference to shown in Fig. 1, semiconductor devices is generally comprised in the prior art：
Semiconductor substrate 10；
Gate dielectric layer 20 in the Semiconductor substrate 10, the material of the gate dielectric layer 20 is silicon oxynitride；
Polysilicon gate 30 on the gate dielectric layer 20.
The polysilicon gate more than 30 is formed using dry etch process, can inevitably damage many in etching process
The surface of crystal silicon grid 30, therefore rapid thermal oxidation can be used（Rapid Thermal Oxidation, RTO）Processing or vapor
Oxidation（ISSG）Oxide layer 40 can be formed on the surface of polysilicon gate 30 and the upper surface of gate dielectric layer 20, the oxide layer 40
Material is silica, and it is used for the surface for repairing the polysilicon gate 30, while polysilicon gate 30 can be protected not oxidized.
But, the dielectric constant of the gate dielectric layer 20 of above-mentioned semiconductor device easily shifts（shift）, accordingly,
Threshold voltage can also shift, the performance of final influence semiconductor devices.
More technologies on oxide layer refer to Publication No. CN101290880A Chinese patent application.
Therefore, how to prevent the dielectric constant of gate dielectric layer from shifting with regard to urgently to be resolved hurrily as those skilled in the art
One of problem.
The content of the invention
The problem of present invention is solved is to provide a kind of semiconductor devices and preparation method thereof, can avoid Jie of gate dielectric layer
Electric constant shifts, the final performance for improving semiconductor devices.
To solve the above problems, the invention provides a kind of semiconductor devices, including：
Semiconductor substrate；
Gate dielectric layer in the Semiconductor substrate, the material of the gate dielectric layer is oxynitrides；
Grid on the gate dielectric layer；
The oxide layer of the gate lateral wall is located at least in, the material of the oxide layer is silicon oxynitride.
To solve the above problems, present invention also offers a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided；
The gate dielectric layer of oxynitride material is formed on the semiconductor substrate；
Polysilicon gate is formed on the gate dielectric layer；
The oxide layer of silicon oxy-nitride material is formed at least on the wall of the polysilicon gate side.
Compared with prior art, technical solution of the present invention has advantages below：At least in gate lateral wall formation silicon oxynitride
Oxide layer, so as to not interfere with the dielectric constant with the gate dielectric layer of oxide layer contact position, and then gate medium can be ensured
The dielectric constant of layer will not shift, and the threshold voltage of device will not shift, and may finally improve semiconductor devices
Performance.Further, since silicon oxynitride is finer and close compared to silica, therefore oxide layer is also used as protective layer, preferably
Anti- oxidation invasion.
Brief description of the drawings
Fig. 1 is the structural representation of semiconductor devices in the prior art；
Fig. 2 is the schematic flow sheet of the preparation method of semiconductor devices in the embodiment of the present invention；
Fig. 3 to Fig. 5 is the structural representation of the preparation method of semiconductor devices in the embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
It is different from other manner described here to implement using other, therefore the present invention is not limited by following public specific embodiment
System.
Just as described in the background section, the dielectric constant of gate dielectric layer easily shifts in the prior art, so as to drop
The low performance of semiconductor devices.
Inventor has found that：With continued reference to shown in Fig. 1, in order to which the dielectric constant for improving gate dielectric layer 20 is K1,
Nitrogen-atoms is mixed with the gate dielectric layer 20 of earth silicon material, the material of gate dielectric layer 20 is changed into silicon oxynitride, i.e. nitrogen
The dielectric constant of silica is K1.When on the surface of polysilicon gate 30 and the upper surface of gate dielectric layer 20 formation earth silicon material
Oxide layer 40 when, it is necessary at high temperature the surface of polysilicon gate 30 and the upper surface of gate dielectric layer 20 incorporation oxygen atom, because
The be in contact content of oxygen in the gate dielectric layer 20 of position of this polysilicon gate 30, gate dielectric layer 20 and the three of oxide layer 40 is improved, nitrogen
Content reduction, or even the material of the gate dielectric layer 20 of the position may be changed into the middle of silica, polysilicon gate 30 again
The material of the corresponding gate dielectric layer 20 in position is unaffected, so as to cause the dielectric constant of the gate dielectric layer 20 of the position can be from K1
K2 is reduced to, and the dielectric constant in the centre position of gate dielectric layer 20 is still K1, ultimately results in the gate medium of the lower section of polysilicon gate 30
The dielectric constant of 20 each position of layer is different, i.e., dielectric constant shifts, correspondingly, and the threshold voltage of semiconductor devices also occurs
Skew.
In view of the above-mentioned problems, the invention provides a kind of semiconductor devices and preparation method thereof, to the surface of grid and grid
The upper surface of dielectric layer is passed through nitrogen-atoms and oxygen atom, and the material of oxide layer in the prior art is changed into nitrogen oxidation from silica
Silicon, now the material of gate dielectric layer is unaffected, and then the dielectric constant of gate dielectric layer does not shift, accordingly,
The threshold voltage of semiconductor devices will not also shift, and finally ensure that the stability of performance of semiconductor device.Further, since
The presence of nitrogen-atoms, silicon oxynitride is finer and close relative to silica, so that oxide layer can preferably play protection grid
Effect.
It is described in detail below in conjunction with the accompanying drawings.
With reference to shown in Fig. 2, present embodiments provide for a kind of preparation method of semiconductor devices, including：
There is provided Semiconductor substrate by step S1；
Step S2, forms gate dielectric layer on the semiconductor substrate；
Step S3, nitrogen-atoms is mixed in the gate dielectric layer；
Step S4, polysilicon gate is formed on the gate dielectric layer；
Step S5, the oxide layer of silicon oxy-nitride material is formed on the surface of the polysilicon gate.
Because the material of oxide layer is silicon oxynitride, therefore during oxide layer is formed, nitrogen-atoms and oxygen atom meeting
Enter simultaneously in the gate dielectric layer of exposure outside, so that the dielectric constant of gate dielectric layer is unaffected, whole gate dielectric layer
Dielectric constant remain to be consistent, will not shift.
There is provided Semiconductor substrate 100 with reference to shown in Fig. 3.
The Semiconductor substrate 100 is used to provide workbench for subsequent technique, and its material can be silicon, SiGe, carbonization
Silicon, silicon-on-insulator or III-V（Silicon nitride or GaAs etc.）.In addition, can be with the Semiconductor substrate 100
Including device, such as：Resistance etc.；Isolation structure can also be included, such as：Fleet plough groove isolation structure etc..
Then, gate dielectric layer 200a is formed in the Semiconductor substrate 100.
The material of the gate dielectric layer 200 can be silica, germanium dioxide or aluminum oxide.
The material of Semiconductor substrate 100 described in the present embodiment is silicon, and gate dielectric layer 200a material is silica, from
And the method for steam oxidation in situ can be used to form gate dielectric layer 200 in the upper surface of Semiconductor substrate 100.
It should be noted that in other embodiments of the invention, the gate dielectric layer 200a can also use its other party
Method is formed, what it was well known to those skilled in the art, will not be repeated here.
With reference to shown in reference to Fig. 3 and Fig. 4, in order to improve gate dielectric layer 200a dielectric constant, using plasma technique
Nitrogen-atoms is mixed into gate dielectric layer 200a, now gate dielectric layer 200b material is changed into silicon oxynitride.Specifically, first using nitrogen
Gas plasma adulterates nitrogen into the gate dielectric layer 200a of silica（Decoupled Plasma Nitridation, DPN）,
Again using the plasma damage in the stable N doping of high-temperature annealing process and reparation gate dielectric layer 200b（Post
Nitridation Anneal, PNA）.
The nitrogen atom concentration of the gate dielectric layer 200b incorporations of the silicon oxy-nitride material of aforesaid way formation is higher, in depth
Be mainly distributed on gate dielectric layer 200b upper surface and away from gate dielectric layer 200b and channel interface, so as to not change semiconductor
On the premise of device performance, gate dielectric layer 200b dielectric constant can be effectively improved.
Then, with continued reference to shown in Fig. 4, polysilicon gate 300 is formed on gate dielectric layer 200b.
Specifically, forming polysilicon gate 300 includes：
Polysilicon layer is formed on whole gate dielectric layer 200b；
Being formed on the polysilicon layer includes the photoresist layer of gate pattern；
Using the photoresist layer as mask, the polysilicon layer is performed etching using dry etch process, polycrystalline is formed
Si-gate 300；
Remove the photoresist layer.
During etches polycrystalline silicon layer, the surface of the polysilicon gate 300（Especially sideways）Inevitably by
To damage, in order to ensure the performance of semiconductor devices, it is necessary to be repaired to the surface of polysilicon gate 300；In addition, in order to ensure
The performance of polysilicon gate 300 is not by external influence, in addition it is also necessary to is protected, therefore then existed on the surface of polysilicon gate 300
The surface of the polysilicon gate 300 forms the oxide layer 400 of silicon oxy-nitride material.
In first specific example, forming the oxide layer 400 can include：Using rapid thermal treatment mode to described
The surface of polysilicon gate 300 first mixes nitrogen-atoms, then mixes oxygen atom.Specifically, the temperature range of rapid thermal treatment includes：
500 DEG C ~ 1100 DEG C, pressure range includes：5torr ~ 780torr, time range includes：5s ~ 180s, each gas flow scope
Including：500mL~50L.Wherein, the gas used when mixing nitrogen-atoms can be ammonia NH3And nitrogen N2In one or more,
Further, it is also possible to add hydrogen H2, one or more in argon Ar and helium He to be to be used as diluent gas or carrier gas, it is ensured that shape
Into oxide layer 400 in nitrogen-atoms content range be 0.5E15/cm2To 8E15/cm2；The gas used during incorporation oxygen atom can
To be oxygen O2, nitric oxide NO and nitrogen dioxide N2One or more in O, can also now add hydrogen H2, argon Ar and
One or more in helium He are to be used as diluent gas or carrier gas.Due to first mixing nitrogen-atoms, nitrogen-atoms thereby may be ensured that
Well into and influence and the gate dielectric layer 200b of the contact position of oxide layer 400 dielectric constant can be avoided；After mix oxygen
Atom, so as to repair the surface of polysilicon gate 300.Further, since silicon oxynitride is dense, therefore oxide layer 400 can
Preferably to protect polysilicon gate 300 not polluted by the external world.
In second specific example, forming the oxide layer 400 can include：Using rapid thermal treatment mode to described
The surface of polysilicon gate 300 mixes nitrogen-atoms and oxygen atom simultaneously.Specifically, the temperature range of rapid thermal treatment includes：500℃
~ 1100 DEG C, pressure range includes：5torr ~ 780torr, time range includes：5s ~ 180s, each gas flow scope includes：
500mL~50L.Wherein, the gas used when mixing nitrogen-atoms and oxygen atom can be nitric oxide NO or nitrogen dioxide N2In O
One or two, further, it is also possible to add hydrogen H2, one or more in argon Ar and helium He to be to be used as diluent gas
Or carrier gas, it is ensured that the content range of nitrogen-atoms is 0.5E15/cm in the oxide layer 400 of formation2To 8E15/cm2.Due to only with
One step mixes nitrogen-atoms and oxygen atom simultaneously, therefore technique is simple, and cost is low.
In the 3rd specific example, forming the oxide layer 400 can include：First in the surface shape of polysilicon gate 300
Into silicon dioxide layer, then nitrogen-atoms is mixed in silicon dioxide layer, concrete technology may be referred to gate dielectric layer 200b, herein no longer
Repeat.
The thickness range of oxide layer 400 described in the present embodiment can include 5 angstroms ~ 50 angstroms.
It should be noted that while forming oxide layer 400 on the surface of polysilicon gate 300, silicon oxy-nitride material may
It can be formed on the upper surface for exposing outside in gate dielectric layer 200b（Not shown in figure）, but be situated between because silicon oxynitride does not interfere with grid
Matter layer 200b performance, therefore do not interfere with the performance of semiconductor devices yet.
Then, with reference to shown in Fig. 5, isolated side wall 500 can also be formed in the side of oxide layer 400；Then with side of isolation
Wall 500 and polysilicon gate 300 are mask, and Doped ions are injected into Semiconductor substrate 100, form heavily doped region 600；And institute
State and interlayer dielectric layer 700 is formed on gate dielectric layer 200b, and make by planarization process upper surface and the oxygen of interlayer dielectric layer 700
Change the upper surface flush of layer 400.
Further, the polysilicon gate 300 can also be replaced with metal gates, specifically：Remove positioned at described many
The oxide layer 400 of the upper surface of crystal silicon grid 300, and retain the oxide layer 400 positioned at the side of polysilicon gate 300；Remove the polycrystalline
Si-gate 300, forms groove；Full metal material is filled in the trench, forms metal gates, its concrete technology and prior art
Compatibility, will not be repeated here.
In addition, when the grid of semiconductor devices is polysilicon gate 300, the oxide layer of the upper surface of polysilicon gate 300
400 can be removed during subsequently metal plug is formed in the upper surface of polysilicon gate 300, its technology for this area
Personnel are well known, be will not be repeated here.
Correspondingly, present embodiment additionally provides a kind of semiconductor devices, including：
Semiconductor substrate；
Gate dielectric layer in the Semiconductor substrate, the material of the gate dielectric layer is oxynitrides；
Grid on the gate dielectric layer；
The oxide layer of the gate lateral wall is located at least in, the material of the oxide layer is silicon oxynitride.
Wherein, the thickness range of the oxide layer includes 5 angstroms ~ 50 angstroms, and the wherein content range of nitrogen-atoms includes 0.5E15/
cm2~8E15/cm2, such as：0.5E15/cm2、2E15/cm2、4.5E15/cm2Or 8E15/cm2。
Wherein, the material of the gate dielectric layer is silicon oxynitride or germanium oxynitride.
Wherein, the material of the grid is polysilicon or metal.
The concrete structure of the semiconductor devices may be referred to above-mentioned preparation method, will not be repeated here.
At least contacted in the present embodiment in the oxide layer of gate lateral wall formation silicon oxynitride so as to not interfere with oxide layer
The dielectric constant of the gate dielectric layer of position, and then can ensure that the dielectric constant of gate dielectric layer will not shift, the threshold of device
Threshold voltage will not shift, and may finally improve the performance of semiconductor devices.Further, since silicon oxynitride is compared to titanium dioxide
Silicon is finer and close, therefore oxide layer is also used as protective layer, is better protected from oxidation invasion.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible variations and modification to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, the technical spirit according to the present invention is to made for any of the above embodiments any simple
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (10)
1. a kind of semiconductor devices, it is characterised in that including：
Semiconductor substrate；
Gate dielectric layer in the Semiconductor substrate, the material of the gate dielectric layer is oxynitrides；
The nitrogen-atoms of the gate dielectric layer is mainly distributed on the upper surface of the gate dielectric layer in depth and is situated between away from the grid
The interface of matter layer and raceway groove；
Grid on the gate dielectric layer；
The oxide layer of the gate lateral wall is located at least in, the material of the oxide layer is silicon oxynitride；
The oxide layer is first to mix nitrogen-atoms to the surface of the grid using rapid thermal treatment mode, then mixes oxygen atom shape
Into.
2. semiconductor devices as claimed in claim 1, it is characterised in that the thickness range of the oxide layer includes：5 angstroms~50
Angstrom.
3. semiconductor devices as claimed in claim 1, it is characterised in that the material of the gate dielectric layer is silicon oxynitride or nitrogen
Germanium oxide.
4. semiconductor devices as claimed in claim 1, it is characterised in that the material of the grid is polysilicon or metal.
5. semiconductor devices as claimed in claim 1, it is characterised in that the content range of nitrogen-atoms includes in the oxide layer
0.5E15/cm2~8E15/cm2。
6. a kind of preparation method of semiconductor devices, it is characterised in that including：
Semiconductor substrate is provided；
The gate dielectric layer of oxynitride material is formed on the semiconductor substrate；
Nitrogen-atoms in the gate dielectric layer is mainly distributed on the upper surface of the gate dielectric layer and the remote grid in depth
The interface of dielectric layer and raceway groove；
Polysilicon gate is formed on the gate dielectric layer；
The oxide layer of silicon oxy-nitride material is formed at least on the wall of the polysilicon gate side；
Forming the oxide layer includes：Nitrogen-atoms is first mixed to the surface of the polysilicon gate using rapid thermal treatment mode, then
Mix oxygen atom.
7. the preparation method of semiconductor devices as claimed in claim 6, it is characterised in that the material of the gate dielectric layer is nitrogen
Silica；Forming the gate dielectric layer includes：
Silica is formed on the semiconductor substrate；
Adulterated using nitrogen gas plasma into the silica nitrogen；
Using the plasma damage in the stable N doping of high-temperature annealing process and the reparation gate dielectric layer.
8. the preparation method of semiconductor devices as claimed in claim 6, it is characterised in that first to the surface of the polysilicon gate
The nitrogen-atoms of incorporation comes from one or both of ammonia and nitrogen；The oxygen atom comes from oxygen, nitric oxide and titanium dioxide
One or more in nitrogen.
9. the preparation method of semiconductor devices as claimed in claim 6, it is characterised in that the temperature model of the rapid thermal treatment
Enclose including：500 DEG C~1100 DEG C, pressure range includes：5torr~780torr, time range includes：5s~180s, gas stream
Amount scope includes：500mL/min~50L/min.
10. the preparation method of semiconductor devices as claimed in claim 6, it is characterised in that also include：
The polysilicon gate is removed, groove is formed；
Full metal is filled in the trench, forms metal gates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210492757.8A CN103839983B (en) | 2012-11-27 | 2012-11-27 | Semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210492757.8A CN103839983B (en) | 2012-11-27 | 2012-11-27 | Semiconductor devices and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103839983A CN103839983A (en) | 2014-06-04 |
| CN103839983B true CN103839983B (en) | 2017-08-25 |
Family
ID=50803304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210492757.8A Active CN103839983B (en) | 2012-11-27 | 2012-11-27 | Semiconductor devices and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103839983B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223769A (en) * | 2018-11-27 | 2020-06-02 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620995A (en) * | 2008-06-30 | 2010-01-06 | 中芯国际集成电路制造(北京)有限公司 | Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof |
| CN102339736A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Interface optimized germanium-based semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007063814A1 (en) * | 2005-12-02 | 2007-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device, and electronic device |
-
2012
- 2012-11-27 CN CN201210492757.8A patent/CN103839983B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620995A (en) * | 2008-06-30 | 2010-01-06 | 中芯国际集成电路制造(北京)有限公司 | Gate dielectric layer, manufacturing method thereof, semiconductor device and manufacturing method thereof |
| CN102339736A (en) * | 2010-07-16 | 2012-02-01 | 中国科学院微电子研究所 | Interface optimized germanium-based semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103839983A (en) | 2014-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100844933B1 (en) | Transistor in semiconductor device and method for manufacturing the same | |
| JP6027531B2 (en) | MOS transistor including SiON gate dielectric with increased nitrogen concentration at its sidewall | |
| TWI543232B (en) | Transistor device and method for forming the same | |
| TWI641085B (en) | Differential sg/eg spacer integration with equivalent nfet/pfet spacer widths & dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage eg device on fdsoi | |
| CN105428238B (en) | A kind of FinFET and preparation method thereof and electronic device | |
| CN107706112B (en) | Method for forming semiconductor device | |
| TW201436027A (en) | Method for clean of oxide layer | |
| CN103390556B (en) | Semiconductor device manufacturing method | |
| CN104616980B (en) | The forming method of metal gates | |
| CN104517901B (en) | The forming method of CMOS transistor | |
| WO2005083795A8 (en) | Method for manufacturing semiconductor device and plasma oxidation method | |
| CN105575815B (en) | The forming method of semiconductor devices | |
| CN104681490A (en) | Forming method of CMOS (complementary metal-oxide-semiconductor) transistor | |
| CN103839983B (en) | Semiconductor devices and preparation method thereof | |
| CN106816414B (en) | The forming method of fin formula field effect transistor | |
| CN104681440A (en) | Semiconductor device and preparation method thereof | |
| CN104752175B (en) | A kind of method for making semiconductor devices | |
| CN105845573A (en) | FinFET device and manufacturing method thereof, and electronic apparatus | |
| CN104332406A (en) | Semiconductor device and method for manufacturing the same | |
| CN104658899B (en) | A kind of method for etching gate dielectric | |
| CN109216256A (en) | Groove isolation construction and its manufacturing method | |
| CN104779146B (en) | A kind of method for making semiconductor devices | |
| CN107799421B (en) | Method for forming semiconductor device | |
| US8530328B1 (en) | Method for manufacturing semiconductor device | |
| CN103165453B (en) | High dielectric metal gate MOS and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |