KR100840702B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100840702B1 KR100840702B1 KR1020070031145A KR20070031145A KR100840702B1 KR 100840702 B1 KR100840702 B1 KR 100840702B1 KR 1020070031145 A KR1020070031145 A KR 1020070031145A KR 20070031145 A KR20070031145 A KR 20070031145A KR 100840702 B1 KR100840702 B1 KR 100840702B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 45
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 45
- 238000000663 remote plasma-enhanced chemical vapour deposition Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 46
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 30
- 230000007547 defect Effects 0.000 abstract description 21
- 230000007423 decrease Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 62
- 239000000758 substrate Substances 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 11
- 238000009826 distribution Methods 0.000 description 11
- 239000010409 thin film Substances 0.000 description 10
- 229910020776 SixNy Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000001272 nitrous oxide Substances 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021431 alpha silicon carbide Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- NCMHKCKGHRPLCM-UHFFFAOYSA-N caesium(1+) Chemical compound [Cs+] NCMHKCKGHRPLCM-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 102000054765 polymorphisms of proteins Human genes 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- -1 silicon carbide metal oxide Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002042 time-of-flight secondary ion mass spectrometry Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체 소자 제조과정을 나타낸 도면,1A to 1C illustrate a semiconductor device manufacturing process according to an embodiment of the present invention;
도 2는 본 발명에 따른 실리콘 나이트라이드의 건식산화를 이용한 4H-탄화규소 산화막과 반도체 구조의 전류밀도(A/cm2)에 대한 산화막 임계 파괴전계 (MV/cm)를 종래와 비교하여 나타낸 도면, FIG. 2 is a graph illustrating oxide critical breakdown electric field (MV / cm) of current density (A / cm 2 ) of 4H-silicon carbide oxide film and semiconductor structure using dry oxidation of silicon nitride according to the present invention. ,
도 3은 본 발명에 따른 실리콘 나이트라이드의 건식산화를 이용한 4H-탄화규소 산화막과 반도체 구조의 전체계면결함준위 (Nit,cm-2)와 유효산화막전하량(Qeff,cm-2)을 종래와 비교하여 나타낸 도면,3 is a graph showing the total interface defect levels (N it , cm -2 ) and effective oxide charges (Q eff , cm -2 ) of a 4H-silicon carbide oxide film and a semiconductor structure using dry oxidation of silicon nitride according to the present invention. Drawing shown in comparison with
도 4a는 본 발명에 따른 실리콘 나이트라이드의 건식산화를 이용한 4H-탄화규소 산화막과 반도체 구조의 산화막과 탄화규소 표면에서 깊이방향에 따른 질소의 분포 및 세기(intensity)를 나타낸 도면, 4A is a view showing the distribution and intensity of nitrogen in the depth direction on the 4H-silicon carbide oxide film, the oxide film of the semiconductor structure and the silicon carbide surface using dry oxidation of silicon nitride according to the present invention;
도 4b는 종래 기술에 따라 질화 처리된 산화막과 반도체 구조의 산화막과 탄화규소 표면에서 깊이방향에 따른 질소의 분포 및 세기(intensity)를 나타낸 도면.4B is a diagram showing the distribution and intensity of nitrogen in the depth direction in the oxide film and the silicon carbide surface of the nitride film and the semiconductor structure according to the prior art;
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 탄화규소(SiC) 기판 위에 질화된 산화막을 구비하는 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a nitrided oxide film on a silicon carbide (SiC) substrate.
정보화 사회의 발전이 더욱 가속화됨에 따라 현재의 실리콘게 반도체 기술로는 에너지, 산업전자, 정보통신, 광전자 또는 극한전자분야를 충분히 뒷받침 할 수 없게 되었으며, 실리콘은 그 물리적인 한계를 드러내고 있다. As the development of the information society accelerates, current silicon crab semiconductor technology cannot fully support the energy, industrial electronics, telecommunications, optoelectronic or extreme electronic fields, and silicon is showing its physical limitations.
이와 같이 실리콘계 반도체 기술의 문제점을 해결하기 위하여 광역 에너지 금지대역을 갖는 새로운 반도체 재료에 대한 연구가 활발히 진행되고 있으며, 여러 물질들 중에서도 탄화규소는 고전압, 고출력 및 고주파 응용분야에 적합한 차세대 전력소자로서 이를 적극 개발하고 있다. In order to solve the problems of silicon-based semiconductor technology, research is being actively conducted on new semiconductor materials having wide energy restriction bands. Among other materials, silicon carbide is a next-generation power device suitable for high voltage, high power, and high frequency applications. We are actively developing.
탄화규소로 제조된 반도체 소자는 실리콘계에 비하여 허용 전계강도가 10배, 동작온도가 4배 정도나 높아 대전력 고온에서의 동작이 가능할 뿐만 아니라 전력계통의 수송변환장치로 이용하면 송전손실을 1/3정도로 낮출 수 있어 에너지 절약효과가 크다. 따라서 향후 고속전철, 전기자동차의 전력제어기, 이동통신 기지국의 고주파 증폭기 등은 물론 발전과 송배전 분야에서의 전력제어에 광범위하게 응용됨으로써 이들 운영 시스템의 크기를 획기적으로 줄이는 동시에 전력손실도 줄일 수 있을 것으로 예상되고 있다. The semiconductor device made of silicon carbide has 10 times the allowable electric field strength and 4 times the operating temperature than silicon system, so it can operate at high temperature and high power. It can be lowered to about 3, which greatly saves energy. Therefore, it will be able to dramatically reduce the size of these operating systems and reduce power loss by being widely applied to power control in power generation and transmission and distribution fields as well as high-speed trains, electric vehicle power controllers, and high frequency amplifiers of mobile communication base stations. It is expected.
현재, 탄화규소는 전계효과트랜지스터(Field Effect Transistor; FET), 발광 다이오드(Light Emitting Diode; LED), 압력센서, 이종접합 바이폴라트랜지스터(Hetero-junction Bipolar Transistor; HBT), 쇼트키 장벽 다이오드(Schottky Barrier Diode) 등으로의 응용이 연구되고 있으며 일부는 실제 상용화되어 가고 있는 추세이다.Currently, silicon carbide has Field Effect Transistors (FETs), Light Emitting Diodes (LEDs), Pressure Sensors, Hetero-junction Bipolar Transistors (HBTs), Schottky Barrier Diodes. Application to diodes, etc. is being studied, and some of them are actually being commercialized.
탄화규소는, 탄소와 실리콘의 강력한 공유 결합력에 의해 기계적 성질이 매우 우수하여 연마재료, 절삭재료 등으로 오래 전부터 사용되어 왔으며, 높은 파괴전압 (5×106Vcm-1), 높은 열전도도 (4.9Wcm-1K-1) 등과 같은 우수한 전기적 특성을 가지고 있기 때문에 Si나 GaAs로 구현하기 힘든 고온, 고전압 전자 소자로서의 응용이 모색되고 있다.Silicon carbide has been used for a long time as an abrasive material and cutting material because of its excellent covalent bond between carbon and silicon. It has high breakdown voltage (5 × 10 6 Vcm -1 ) and high thermal conductivity (4.9). Because of its excellent electrical properties such as Wcm -1 K -1 ), applications as high-temperature, high-voltage electronic devices that are difficult to realize with Si or GaAs are being sought.
탄화규소는 최밀 충진면의 적층순서에 따라 많은 결정다형이 보고 되고 있으며, 유일하게 입방정상을 가지는 징크블렌드(zincblend) 구조의 탄화규소를 베타 탄화규소(β-SiC) 라 하고, 나머지 결정다형을 알파 탄화규소(α-SiC) 라고 지칭한다. 현재, 4-에이치(4-H) 탄화규소와 6-에이치(6-H) 탄화규소는 3인치 구경을 갖는 단결정 기판의 상용화 및 고품질의 동종박막 성장이 가능하게 되어 활발한 연구가 진행되고 있으며, 특히, 4-에이치(4-H) 탄화규소는 전자이동도 등이 가장 우수한 특성을 갖기 때문에 중점 연구 대상이 되고 있다.Silicon carbide has been reported in many crystal polymorphisms according to the lamination order of the closest packing surface, the only cubic blended zinc carbide (zincblend) structure is called beta silicon carbide (β-SiC), and the remaining crystal polymorphism Referred to as alpha silicon carbide (α-SiC). Currently, 4-H (4-H) silicon carbide and 6-H (6-H) silicon carbide enable the commercialization of single-crystal substrates having a 3-inch diameter and high-quality homogeneous thin film growth. In particular, 4-H (4-H) silicon carbide has been the subject of research because it has the best characteristics such as electron mobility.
또한 실리콘의 가장 큰 장점 중의 하나인 자연적 산화막을 형성할 수 있는 특징을 탄화규소 또한 갖고 있기 때문에 고속 스위칭이 가능한 금속산화물반도체 전계효과트랜지스터(MOSFET, Metal-Oxide-Semiconductor Field Effect Transistor) 에 응용 가능성이 높다.In addition, silicon carbide has the characteristic of forming a natural oxide film, which is one of the biggest advantages of silicon, and thus it is likely to be applied to a metal-oxide-semiconductor field effect transistor (MOSFET) capable of high-speed switching. high.
전술한 바와 같이 우수한 특성을 갖는 탄화규소를 전자소자에 응용하기 위해서는 소자 제작에 필요한 단결정 박막 성장, 박막의 도핑 컨트롤, 산화막 형성, 금속접합, 선택적 도핑, 식각기술 등 제반 공정기술이 확립되어야 하며, 그 중에서도 가장 중요한 기술 중의 하나는 산화막와 탄화규소 사이의 고품위 계면을 갖는 구조를 제조하는 기술이다. As described above, in order to apply silicon carbide having excellent properties to electronic devices, various process technologies such as single crystal thin film growth, doping control of thin films, oxide film formation, metal bonding, selective doping, and etching techniques required for device manufacturing should be established. One of the most important techniques is a technique for producing a structure having a high quality interface between an oxide film and silicon carbide.
특히, 최근의 탄화규소를 기본으로 하여 제작된 소자인 탄화규소 금속산화물 전계효과 트랜지스터(SiC MOSFET) 소자들의 스위칭 속도를 높여야 하며, 이를 달성하기 위해서는 산화막과 탄화규소 사이의 고품위 계면 형성 기술이 매우 중요하다.In particular, the switching speed of the silicon carbide metal oxide field effect transistor (SiC MOSFET) devices manufactured based on the recent silicon carbide must be increased, and a high quality interface formation technology between the oxide film and the silicon carbide is very important to achieve this. Do.
종래에는 주로 탄화규소 산화막 형성기술의 경우 나이트릭 옥사이드(NO) 또는 나이트러스 옥사이드(N2O) 가스 등을 이용하여 직접 산화 또는 후열처리(post annealing)를 통하여 제작한다. 이때 계면에 존재하는 질소는 산화막과 탄화규소의 계면에서 탄소들 끼리 뭉치는 현상을 억제하고 실리콘, 탄소, 산소 등의 연결되지 못한 빈 자리를 채우는 등 그 결함들의 에너지 상태를 탄화규소 밴드갭 외의 에너지 상태로 이동, 즉 계면에 존재하는 결함을 줄여줌으로써 채널에서 전자 이동도를 크게 향상시키게 된다.Conventionally, silicon carbide oxide film formation technology is mainly manufactured through direct oxidation or post annealing using nitrous oxide (NO) or nitrous oxide (N 2 O) gas or the like. At this time, the nitrogen present at the interface suppresses the aggregation of carbons at the interface between the oxide film and the silicon carbide and fills the unconnected voids such as silicon, carbon, and oxygen. By moving to a state, that is, reducing defects at the interface, the electron mobility in the channel is greatly improved.
그러나, 상기 종래와 같이 나이트릭 옥사이드(NO) 또는 나이트러스 옥사이드(N2O) 가스 등을 이용하여 산화 또는 후열처리 할 경우, 산소분압이 낮기 때문에 산화막 형성시 산화막 성장속도가 상당히 느려지고 또한 계면에 질소를 위치시키기 위한 산화막 두께 (≥ 8 nm)도 제한되어 있다. 또한 후열처리의 경우 소자 적용을 위한 적정 두께의 산화막(
따라서, 본 발명은 산화막 성장속도 및 탄화규소와 산화막 계면에서의 질소의 양을 높일 수 있는 반도체 소자의 제조방법을 제공하고자 한다. Accordingly, the present invention is to provide a method for manufacturing a semiconductor device capable of increasing the oxide film growth rate and the amount of nitrogen at the silicon carbide and oxide interface.
또한, 본 발명은 충분한 질소를 빠른 시간에 공급함으로써 계면결함을 감소시킬 수 있는 반도체 소자의 제조방법을 제공하고자 한다. In addition, the present invention is to provide a method for manufacturing a semiconductor device that can reduce the interface defects by supplying sufficient nitrogen in a short time.
이를 위해 본 발명은 탄화규소막 위에 실리콘 나이트라이드막을 형성하는 과정과; 상기 실리콘 나이트라이드막을 산화시켜 질화처리된 산화막을 형성하는 과정을 포함함을 특징으로 한다. To this end, the present invention comprises the steps of forming a silicon nitride film on the silicon carbide film; And oxidizing the silicon nitride film to form a nitrided oxide film.
또한 본 발명은 실리콘 나이트라이드막 형성시 탄화규소막에 가해지는 충격을 줄이기 위해 리모트-플라즈마보조 화학기상증착(remote-PECVD)법으로 제조함을 특징으로 한다. In another aspect, the present invention is characterized by manufacturing by a remote-plasma assisted chemical vapor deposition (remote-PECVD) method to reduce the impact on the silicon carbide film when forming the silicon nitride film.
이하, 본 발명에 따른 바람직한 실시 예를 첨부한 도면을 참조하여 상세히 설명한다. 도면에서 동일한 구성요소들에 대해서는 비록 다른 도면상에 표시되더라 도 가능한 동일한 참조번호 및 부호로 나타내고 있음에 유의해야 한다. 또한, 본 발명을 설명함에 있어서, 관련된 공지기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the same components in the drawings are denoted by the same reference numerals and symbols as possible even if shown on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체 소자 제조과정을 나타낸 도면으로, 본 실시예는 질화된 산화막이 금속산화물반도체 전계효과트랜지스터(MOSFET, Metal-Oxide-Semiconductor Field Effect Transistor)의 게이트산화막으로 적용된 경우이다. 1A to 1C are diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present invention. The present embodiment shows a nitrided oxide film of a metal oxide semiconductor field effect transistor (MOSFET). This is the case when the gate oxide film is applied.
먼저, 도 1a는 탄화규소(예를 들면 4-H) 기판(1) 위에 SixNy막(2)을 증착한 상태를 나타낸 단면도이다. 기판(1)은 8°의 오프축(off-axis)을 갖는 탄화규소 단결정 기판으로 SixNy막(2)을 증착하기 전에 아세톤-에틸알콜-표준알씨에이(RCA)-불산(탈이온수에 7:1로 희석)-탈이온수의 순서로 세정한다. 또한, SixNy막(2) 증착시에 하부의 탄화규소(예를 들면 4-H) 기판(1)에 충격이 가해지는 것을 줄일 수 있도록 리모트-플라즈마보조 화학기상증착(remote PECVD)법에 의해 증착하며, 7nm 내지 80nm 정도 두께로 형성한다. 리모트-플라즈마보조 화학기상증착법에 의하면 박막이 성장되는 영역과 플라즈마가 형성되는 영역을 분리함으로써 플라즈마에 의한 기판의 충격을 최소화하고 플라즈마에 의해 생성된 기(spieces)와 사일렌(SiH4)이 기판 위에서 반응하는 메카니즘은 저온에서 고품질의 박막을 형성할 수 있다. 본 실시예에서는 4-H SiC 기판을 사용하였으나, 4-H SiC, 6-H SiC, 3C SiC, Si, GaN, GaAs 등을 포함하는 반도체 물질로 된 기판도 가능하다. First, FIG. 1A is a cross-sectional view showing a state in which a SixNy
이어서, 산화로(oxidation furnace)를 이용한 산화공정을 진행하여 SixNy막(2)을 건식산화시킴으로써 도 1b에 도시된 바와 같이 탄화규소 기판(1) 위에 질화된 산화막(3)을 형성한다. 산화막(3)은 7.5nm 내지 90nm 정도 두께로 형성하며, 이를 위해 1100 내지 1300℃의 온도하에서 1 내지 4 SLM(standard liter per minute) 범위의 산소를 주입한다. SixNy막(2)의 건식산화에 의해 다량의 질소가 산화막(3)과 탄화규소 기판(1)의 계면에 위치하게 되면 밴드갭 내에 위치한 탄소와 연관된 결함들은 질소와 반응 또는 결합하여 공기중으로 빠져나가거나 에너지 밴드갭 외 준위의 에너지 상태를 띄게 되어 계면결함을 개선하게 된다. Subsequently, an oxidation process using an oxidation furnace is performed to dry oxidize the
도 1c는 산화막(3) 위에 금속을 증착하여 게이트전극(4)을 형성한 상태를 나타낸 단면도이다. FIG. 1C is a cross-sectional view illustrating a state in which a
산화막과 탄화규소 사이의 계면상태를 평가하기 위하여 알루미늄을 사용하여 질화된 산화막 위에 게이트전극을 형성하고, 탄화규소 기판의 배면에 하부전극을 형성하여 금속산화물반도체 캐패시터(MOS capacitor)를 제작한 후 이의 전기적 특성을 평가하였다. 전기적 특성은 키슬리장비(Keithely 590 C-V analyzer, 595 Quasistatic C-V meter, Semiconductor Parameter Analyzer)를 이용하여 캐패시턴스 및 전류밀도(current density)-전압(voltage)을 측정함으로써 평가할 수 있다. In order to evaluate the interface state between the oxide film and silicon carbide, a gate electrode is formed on the nitrided oxide film using aluminum, and a lower electrode is formed on the back surface of the silicon carbide substrate to fabricate a metal oxide semiconductor capacitor (MOS capacitor). The electrical properties were evaluated. Electrical characteristics can be assessed by measuring capacitance and current density-voltage using Keithley's (Keithely 590 C-V analyzer, 595 Quasistatic C-V meter, Semiconductor Parameter Analyzer).
도 2는 본 발명과 종래기술에 따라 성장된 산화막 구조에서 산화막과 탄화규소의 계면 및 산화막 전류밀도-전압(j-v) 특성을 비교하여 나타낸 도면이다. 이때, 산화막 파괴를 전류밀도 10-6A/cm2 이상으로 정의한다. 2 is a view showing a comparison between the interface between the oxide film and silicon carbide and oxide current density-voltage (jv) in the oxide film structure grown according to the present invention and the prior art. At this time, the oxide film breakage is defined as a current density of 10 −6 A / cm 2 or more.
도 2를 참조하면, 본 발명에 따라 실리콘 나이트라이드박막의 건식산화에 의해 성장된 산화막(oxidized-SixNy)의 임계파괴전계(①)는 8MV/cm로 종래 10% N2O에 의해 질화처리된 산화막의 임계파괴전계(②)와 거의 차이가 없거나 종래 일반적인 열산화막(dry SiO2)의 임계파괴전계(③)보다 우수한 파괴전계를 나타내며, 이는 실리콘 나이트라이드막의 건식산화 시에 생성되는 질소가 계면결함을 억제 또는 보상하여 극복할 수 있음을 보여준다. Referring to FIG. 2, the
도 3은 본 발명과 종래기술에 따라 성장된 산화막의 전체 계면결함과 유효산화막 전하량(effective oxide change; Qeff)을 비교하여 나타낸 도면이다. 산화막 구조의 계면결함 상태는 전체 계면결함밀도로 나타내었다. 이때 계면결함은 하이-로우(high-low) 주파수 캐패시턴스-전압 측정법으로 계산되었으며, 에너지 밴드갭 내에서 전도대(conduction energy band) 아래 0.2 내지 0.7eV 사이의 계면결함 준위 값을 전부 더하여 전체 계면결함준위를 나타낸 것이다. 3 is a view showing a comparison between the total interfacial defects of the oxide film grown according to the present invention and the prior art and the effective oxide change (Q eff ). The interfacial defect state of the oxide film structure is represented by the total interfacial defect density. At this time, the interface defect was calculated by high-low frequency capacitance-voltage measurement, and the total interface defect level was added by adding all the interface defect level values between 0.2 and 0.7 eV below the conduction band in the energy band gap. It is shown.
도 3을 참조하면, 전체 계면결함의 경우 본 발명에 따라 실리콘 나이트라이드박막의 건식산화에 의해 성장된 산화막(oxidized-SixNy)과 종래 10% N2O에 의해 질화처리된 산화막(10% N2O)은 거의 유사하고 종래 순수한 건식산화막(dry SiO2)의 경우보다 9배 이상 억제됨을 알 수 있다. 이는 계면에 존재하는 다량의 질소가 계면결함을 줄이는 역할을 하기 때문으로 이해된다. 유효산화막 전하량의 경우 본 발 명에 따라 실리콘 나이트라이드박막의 건식산화에 의해 성장된 산화막(oxidized-SixNy)이 계면 근처에 존재하는 전하를 갖는 결함들을 억제함으로써 그 값이 종래 순수한 건식산화막(dry SiO2)의 경우보다 2배 이상 감소함을 확인할 수 있다. 또한 종래 10% N2O에 의해 질화처리된 산화막(10% N2O)과 비교해도 더 작은 유효산화막을 나타내며, 이는 산화막과 탄화규소 구조 내의 질소의 분포를 확인함으로써 설명할 수 있다. Referring to FIG. 3, in the case of total interfacial defects, an oxide film (oxidized-SixNy) grown by dry oxidation of a silicon nitride thin film according to the present invention and an oxide film nitrided by a conventional 10% N 2 O (10% N 2) It can be seen that O) is almost similar and is suppressed 9 times or more than in the case of the conventional pure dry oxide (dry SiO 2 ). This is understood because a large amount of nitrogen present at the interface serves to reduce interfacial defects. In the case of the effective oxide charge amount, according to the present invention, an oxide film (oxidized-SixNy) grown by dry oxidation of a silicon nitride thin film suppresses defects having charges present near an interface, and thus the value thereof is conventionally pure dry oxide (dry SiO). It can be seen that the reduction is more than twice than in the case 2 ). It also shows a smaller effective oxide film compared to the oxide film (10% N 2 O) nitrided by the conventional 10% N 2 O, which can be explained by confirming the distribution of nitrogen in the oxide film and the silicon carbide structure.
도 4a 및 도 4b는 산화막과 탄화규소 구조 내의 질소의 분포를 나타낸 도면으로, 산화막과 탄화규소의 표면에서 깊이방향에 따른(depth profile) 질소의 분포를 확인하기 위하여 토프심스(ToF-SIMS, Time of Flight Secondary Ion mass spectroscopy)를 이용하여 측정한 것이다. 참고로, 도프심스 정보는 8keV 에너지를 갖는 세슘이온(Cs+)을 사용하여 샘플을 스퍼터링하여 만들어지는 M+Cs 형태의 2차종을 분석하여 질소의 분포를 확인할 수 있다. 이때 성분분석장비(monchrometer)의 상태가 조금씩 달라져 원소마다 측정되는 세기(intensity)가 달라질 수 있기 때문에 탄화규소의 양으로 다른 원소의 양을 보정하여 나타내었고 산소 세기의 50%가 되는 지점을 산화막과 탄화규소의 계면으로 정의한다. 4A and 4B are diagrams showing the distribution of nitrogen in the oxide film and the silicon carbide structure. To confirm the distribution of nitrogen in the depth profile on the surfaces of the oxide film and silicon carbide (ToF-SIMS, Time) Measured using of Flight Secondary Ion mass spectroscopy. For reference, the dope sims information can confirm the distribution of nitrogen by analyzing the secondary species of M + Cs produced by sputtering the sample using cesium ion (Cs +) having 8 keV energy. At this time, since the state of the element analysis device (monchrometer) may change slightly, the intensity measured for each element may vary, so the amount of other elements is corrected by the amount of silicon carbide. It is defined as the interface of silicon carbide.
도 4a는 본 발명에 따라 실리콘 나이트라이드박막의 건식산화에 의해 성장된 산화막(oxidized-SixNy)과 탄화규소 구조 내의 질소의 분포를 나타낸 것이고, 도 4b는 종래 10% N2O에 의해 질화처리된 산화막과 탄화규소 구조 내의 질소의 분포를 나타낸 것이다. 도 4a와 도 4b를 비교하면, 도 4a에서의 질소의 분포가 도 4b에서 의 질소의 분포에 비해 2배 이상으로 집중적인 분포를 나타낸다. 이는 계면에 집중되어 있는 다량의 질소들이 계면에 존재하는 결함과 게면 근처에 존재하는 전하를 갖는 결함들을 제거하는 요소로 작용함을 알 수 있다. 또한 종래 10% N2O에 의해 질화처리된 산화막의 경우 산화막과 탄화규소 구조의 계면 외에도 산화막 전체에 질소가 분포함을 알 수 있다. Figure 4a shows the distribution of nitrogen in the oxide film (oxidized-SixNy) and silicon carbide grown by dry oxidation of the silicon nitride thin film according to the present invention, Figure 4b is conventionally nitrided by 10% N 2 O The distribution of nitrogen in the oxide film and silicon carbide structure is shown. Comparing FIG. 4A and FIG. 4B, the distribution of nitrogen in FIG. 4A is more intensive than the distribution of nitrogen in FIG. 4B. It can be seen that a large amount of nitrogen concentrated at the interface serves as an element for removing defects at the interface and defects with charges present near the surface. In addition, in the case of the oxide film nitrided by the conventional 10% N 2 O, in addition to the interface between the oxide film and the silicon carbide structure, it can be seen that nitrogen is distributed throughout the oxide film.
한편 본 발명의 상세한 설명에서는 구체적인 실시 예에 관해 설명하였으나, 본 발명의 범위를 초과하지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다. 그러므로 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니 되며 후술하는 특허청구의 범위뿐만 아니라 이 특허청구의 범위와 균등한 것들에 의해 정해져야 한다.Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.
전술한 바와 같이, 본 발명에 의하면 탄화규소 기판 위에 증착된 실리콘 나이트라이드박막을 건식산화 시키는 것에 의해 질화된 산화막을 형성함으로써 생산 가격을 획기적으로 낮추며, 계면결함을 감소시키는 충분한 질소를 빠른 시간에 공급함으로써 계면결함을 효과적으로 감소시킬 수 있다. As described above, according to the present invention, by forming a nitrided oxide film by dry oxidizing a silicon nitride thin film deposited on a silicon carbide substrate, the nitrogen oxide film is drastically lowered in production cost, and a sufficient time is supplied with sufficient nitrogen to reduce interfacial defects. By doing so, the interface defect can be effectively reduced.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101581690B1 (en) * | 2013-12-30 | 2015-12-31 | 서강대학교산학협력단 | Lateral diffusion MOS device and method for manufacturing the device |
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