WO2024051493A1

WO2024051493A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2024051493A1
Application number: PCT/CN2023/114358
Authority: WO
Inventors: 彭志高; 柴亚玲; 顾子琨
Original assignee: 厦门市三安集成电路有限公司
Priority date: 2022-09-08
Filing date: 2023-08-23
Publication date: 2024-03-14
Also published as: CN115425073A

Abstract

The present application relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate; an epitaxial layer located on a surface of the substrate; a gate oxide layer located on the side of the epitaxial layer distant from the substrate; a first doped polysilicon layer located on the side of the gate oxide layer distant from the substrate; a second doped polysilicon layer located on the side of the first doped polysilicon layer distant from the substrate; and a third doped polysilicon layer located on the side of the second doped polysilicon layer distant from the substrate. Doping elements in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer comprise phosphorus; the gate oxide layer comprises a doping element, and the doping element comprises phosphorus.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present application relates to the field of semiconductor technology, specifically, to a semiconductor device and a manufacturing method thereof.

Background technique

As an important third-generation semiconductor material, silicon carbide has advantages such as high bandgap width, high critical breakdown electric field, and high thermal conductivity. Therefore, silicon carbide power devices have higher breakdown voltage than traditional silicon-based power devices, and switch With the advantages of faster speed and higher operating temperature, it has very broad application prospects in new energy vehicles, photovoltaic power generation, tram traction and other fields.

The polysilicon layer is an important component of SiC MOSFET devices. It mainly plays the role of connecting the gate oxide layer and the gate metal. Growing a high-quality doped polysilicon layer is the basis for preparing high-performance power devices.

Contents of the invention

Some embodiments of the present application provide a semiconductor device, which includes: a substrate. An epitaxial layer located on the surface of the substrate. A gate oxide layer located on a side of the epitaxial layer away from the substrate. A first doped polysilicon layer located on a side of the gate oxide layer away from the substrate. a second doped polysilicon layer located on a side of the first doped polysilicon layer away from the substrate. a third doped polysilicon layer located on a side of the second doped polysilicon layer away from the substrate. The doping elements in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer include phosphorus, the gate oxide layer includes doping elements, and the doping elements Includes phosphorus.

Some embodiments of the present application also provide a method for manufacturing a semiconductor device. The method includes the following steps: providing a substrate. An epitaxial layer is formed on the substrate. A gate oxide layer is formed on the epitaxial layer. An intrinsic polysilicon gate layer is formed on the gate oxide layer. A second polysilicon layer is formed on the intrinsic polysilicon gate layer. A third polysilicon layer is formed on the second polysilicon layer; wherein the doping elements in the second polysilicon layer and the third polysilicon layer include phosphorus, and the second polysilicon layer The doping concentration of phosphorus element in the crystalline silicon layer is greater than the doping concentration of phosphorus element in the third polysilicon layer.

The implementation of the present application can obtain a doped polysilicon layer with better quality, thereby promoting the improvement of power device performance.

Description of the drawings

In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, therefore This should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a schematic diagram of the hierarchical structure of a semiconductor device in the prior art.

FIG. 2 is a first exemplary flow chart of a semiconductor device manufacturing method provided by some embodiments of the present application.

Figure 3 is a hierarchical structure diagram corresponding to S104 provided by some embodiments of the present application.

Figure 4 is a hierarchical structure diagram corresponding to S106 provided by some embodiments of the present application.

Figure 5 is a hierarchical structure diagram corresponding to S108 provided by some embodiments of the present application.

Figure 6 is a hierarchical structure diagram corresponding to S112 provided by some embodiments of the present application.

Figure 7 is a second exemplary flow chart of a semiconductor device manufacturing method provided by some embodiments of the present application.

Figure 8 is a corresponding hierarchical structure diagram after annealing provided by some embodiments of the present application.

In the picture:

110-substrate; 120-epitaxial layer; 130-gate oxide layer; 140-intrinsic polysilicon gate layer; 151-first doped polysilicon layer; 152-second doped polysilicon layer. 153-Third doped polysilicon layer. .

Embodiments of the invention

In order to make the purpose, technical solutions and advantages of some embodiments of the present application clearer, the technical solutions in some embodiments of the present application will be clearly and completely described below in conjunction with the drawings in some embodiments of the present application. Obviously, the description The embodiments are part of the embodiments of this application, rather than all the embodiments. The components of some embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Therefore, the following detailed description of the embodiments of the application provided in the appended drawings is not intended to limit the scope of the claimed application, but rather to represent selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to differentiate the description and cannot be understood as indicating or implying relative importance.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments may be combined with each other without conflict.

As mentioned in the background art, the polysilicon layer is an important part of the SiC MOSFET device and mainly plays the role of connecting the gate oxide layer and the gate metal. Among them, the size of the polysilicon square resistor will seriously limit the switching speed of the power device, making it impossible to exert the high-frequency characteristics of the silicon carbide device.

Figure 1 shows a schematic diagram of the hierarchical structure of an existing MOSFET device, in which the substrate, epitaxial layer, gate oxide layer and polysilicon layer are connected layer by layer. Of course, the polysilicon layer is also connected to other hierarchical structures, such as gate metal. layer, which will not be described in detail here.

Some embodiments of the present application provide a method for manufacturing a semiconductor device by first growing a thin layer of intrinsic polysilicon to change the surface characteristics, and then growing the polysilicon through an in-situ doping process to increase the overall growth rate of the polysilicon.

The following is an exemplary description of the semiconductor device manufacturing method provided by this application:

As some optional implementation methods, please refer to Figure 2. The semiconductor device manufacturing method provided by this application includes:

S102, provide a substrate;

S104, form an epitaxial layer on the substrate.

S106: Form a gate oxide layer on the epitaxial layer.

S108: Form an intrinsic polysilicon gate layer on the gate oxide layer.

S110: Form a second polysilicon layer on the intrinsic polysilicon gate layer.

S112, form a third polysilicon layer on the second polysilicon layer; wherein, the doping elements in the second polysilicon layer and the third polysilicon layer include phosphorus, and the phosphorus element in the second polysilicon layer The doping concentration is greater than the doping concentration of phosphorus element in the third polysilicon layer.

The term "forming layer B on layer A" means that A includes two sides, the front and the back, with the back facing the substrate and the front facing the opposite direction of the substrate, and B connected to the front of A.

For example, with reference to Figure 1, for the oxide layer, its back side faces the substrate and is connected to the epitaxial layer, and its front side faces the opposite direction of the substrate, and its front side is connected to the polysilicon layer. Polysilicon grown on one side of the substrate" is described.

Through this implementation, on the one hand, when growing the doped polysilicon layer, a thin layer of intrinsic polysilicon is first grown to change the surface properties. Therefore, when the doped polysilicon layer is grown, the growth of the in-situ doped polysilicon is improved. rate. And because the thickness of the first polysilicon is thinner and the thickness of the doped polysilicon layer is thicker, the growth rate of the polysilicon layer is strongly related to the growth rate of the doped polysilicon layer. When the growth rate of the doped polysilicon layer is increased, the polysilicon The overall growth rate of the layer is increased. On the other hand, this application still uses an in-situ doping process to grow the doped polysilicon layer, so the polysilicon doping has better uniformity and lower cost.

The present application does not limit the materials of the substrate 110 and the epitaxial layer 120. For example, the substrate 110 can be SiC substrate 110, Si substrate 110, sapphire substrate 110, etc., and the epitaxial layer 120 can be homoepitaxial or epitaxial. In heteroepitaxy, for example, the epitaxial layer 120 adopts SiC epitaxy. The structure after growing the epitaxial layer 120 is shown in Figure 3 . Since the epitaxial growth process is relatively mature, the epitaxial growth process will not be described in detail. For example, the epitaxial layer 120 may be grown using a vapor phase epitaxial process.

After growing the epitaxial layer 120 with a target thickness, please refer to FIG. 4 . It is necessary to continue growing the gate oxide layer 130 on the surface of the epitaxial layer 120 . In some embodiments, in order to remove impurities on the surface of the epitaxial layer 120, after growing the epitaxial layer 120, a standard RCA cleaning process needs to be performed on the epitaxial layer 120. Moreover, the gate oxide layer 130 provided in this application is gate oxide, which may be a SiO ₂ gate oxide layer.

On this basis, as some implementation methods, when growing the gate oxide layer 130, it can be thermally oxidized at a high temperature of 1300°C, then annealed at 1250°C in a nitrogen-doped atmosphere for 30 minutes, and annealed in an atmosphere of argon or other inert gases. In 90 minutes, SiO ₂ gate oxide layer 130 is formed. The nitrogen-doped atmosphere includes but is not limited to nitrogen, nitric oxide, dinitrogen oxide, etc., and the thickness of the gate oxide layer 130 ranges from 40 nm to 60 nm.

As another implementation method, it is also possible to oxidize wet oxygen (such as water vapor) for 90 minutes under high temperature conditions of 950°C-1100°C, and then anneal in a nitrogen-doped atmosphere at 1250°C for 30 minutes, and then anneal in an inert gas atmosphere such as argon for 90 minutes to form For the SiO ₂ gate oxide layer 130, the nitrogen-doped atmosphere includes but is not limited to nitrogen, nitric oxide or dinitrogen oxide, etc., and the thickness ranges from 40nm to 60nm. The SiO ₂ dielectric film oxidized by wet oxygen is looser than high-temperature hot oxygen, which is more conducive to the diffusion of nitrogen or phosphorus.

Referring to FIG. 5 , after the gate oxide layer 130 is grown, intrinsic polysilicon is continued to be grown on the surface of the gate oxide layer 130 to form the intrinsic polysilicon gate layer 140 . Among them, this application does not limit the growth process of the intrinsic polysilicon gate layer 140. For example, a non-doped layer can be grown by LPCVD (Low Pressure Chemical Vapor Deposition) under a high temperature condition of 620°C. And thin intrinsic polysilicon. Of course, other processes may also be used to grow the intrinsic polysilicon gate layer 140, for example, a CVD process or a molecular beam epitaxy process, which is not limited here.

By growing the intrinsic polysilicon gate layer on the silicon oxide layer, the surface properties can be changed through the intrinsic polysilicon gate layer, and then when the doped polysilicon layer is grown, the growth rate of the in-situ doped polysilicon can be increased, making the doped polysilicon The growth rate of the layer is greatly increased.

In order to ensure that the intrinsic polysilicon gate layer 140 does not affect the growth rate and does not affect the performance of the device, it is necessary to ensure that the thickness of the intrinsic polysilicon gate layer 140 is relatively thin. In some embodiments, the intrinsic polysilicon gate layer 140 The thickness range is 10~30nm.

Of course, in an optional implementation, after the growth of the intrinsic polysilicon gate layer 140 is completed, impurity elements may also be injected through an ion implantation process to form doped polysilicon, for example, P elements or B elements may be implanted. A layer of doped polysilicon is then grown.

Among them, in order to further improve the growth rate of the doped polysilicon layer, please refer to FIG. 6. The doped polysilicon layer includes a second polysilicon layer 152 and a third polysilicon layer 153, and the doping of the second polysilicon layer 152 is The concentration is greater than the doping concentration of the third polysilicon layer 153 .

In an optional implementation manner, the impurity source doped in the second polysilicon layer 152 and the third polysilicon layer 153 can be a P source or a B source. Of course, it can also be other impurity sources. , no limitation is made here. Taking the P source as an example, PH ₃ can be used as the P source. On this basis, the second polysilicon layer 152 can be deposited by in-situ doping with PH ₃ through LPCVD at 620°C, and the gas atmosphere is SiH ₄ . Mixed gas of PH ₃ and N ₂ , the flow ratio of SiH ₄ and PH ₃ is 2:1, so that the phosphorus doping concentration reaches 3E20cm-1 to 1E21cm-1, and the resistivity reaches 5E-4Ω·cm to 1E-3Ω· cm. In this implementation, the second polysilicon layer 152 and the third polysilicon layer 153 are doped with P and N impurity sources.

Of course, the process can also adopt CVD, molecular beam epitaxy and other processes, and there is no limitation on this. At the same time, other gases may also be used for the gas separation, such as inert gases, which are not limited.

It should be noted that in order to meet the requirements of the diffusion process and further increase the growth rate of the polysilicon layer, the thickness of the second polysilicon layer 152 is relatively thin. Optional, the thickness of the second polysilicon layer ranges from 10 to 30 nm. .

In an optional implementation, after the second polysilicon layer 152 is grown, the flow rate of PH ₃ can be reduced, and the third polysilicon layer 153 can be deposited by in-situ doping with PH ₃ at 620° C. through LPCVD. By reducing the PH3 flow rate, the competition between surface _PH3 and _SiH4 can be reduced, thereby further increasing the growth rate and obtaining a polysilicon layer that meets the thickness requirements.

Among them, this application does not limit the specific value of reducing the flow rate of PH _3. For example, when growing the second polysilicon layer 152, the flow ratio of SiH ₄ and PH ₃ is 2:1, and when growing the third polysilicon layer 152, the flow ratio of SiH 4 to PH 3 is 2:1. When the crystalline silicon layer is 153, the flow ratio of SiH ₄ and PH ₃ is 4:1, thus reducing the flow rate of PH ₃ .

At the same time, in some embodiments, the sum of the thicknesses of the intrinsic polysilicon gate layer 140 and the doped polysilicon layer (ie, 1 includes the first doped polysilicon layer and the second doped polysilicon layer) is 400~800 nm. On this basis , since the thicknesses of the intrinsic polysilicon gate layer 140 and the second polysilicon layer 152 are both relatively thin, the thickness of the third polysilicon layer 153 is relatively large. By increasing the growth rate of the third polysilicon layer 153 , which can greatly increase the growth rate of the entire polysilicon layer.

For example, the total thickness of the polysilicon layer is 400 nm, the thickness of the intrinsic polysilicon gate layer 140 is 30 nm, the thickness of the second polysilicon layer 152 is 30 nm, and the thickness of the third polysilicon layer 153 is 340 nm. Since the intrinsic polysilicon gate layer 140 is made using a traditional process, its growth rate is relatively low, which is consistent with the growth rate of the polysilicon layer in the prior art. When the second polysilicon layer 152 is grown, the surface characteristics are changed due to the action of the intrinsic polysilicon gate layer 140, so that the growth efficiency of the second polysilicon layer 152 is improved. When growing the third polysilicon layer 153, the growth rate is maximized by changing the surface characteristics and reducing the flow rate of PH _3. Therefore, the fastest growth rate is used to grow the thickest third polysilicon layer 153. The crystalline silicon layer 153 takes the shortest time to grow among the three, thereby increasing the growth rate of the entire polysilicon layer.

In some embodiments, after S112, in order to improve the performance of the semiconductor device, please refer to Figure 7. The manufacturing method also includes:

S112, anneal the semiconductor device to diffuse impurity elements into the gate oxide layer. The intrinsic polysilicon gate layer is transformed into a first doped polysilicon layer, the second polysilicon layer is transformed into a second doped polysilicon layer, and the third polysilicon layer 153 may be renamed the third Doped polysilicon layer.

Among them, through high-temperature annealing, the doping elements in the second polysilicon layer 152 can be pushed into the interface between the gate oxide layer 130 and the epitaxial layer 120. For example, when the doping element is P, P is removed through the annealing process. The elements are pushed into the gate oxide layer 130 . In some embodiments, diffusion occurs to the interface between the gate oxide layer 130 and the epitaxial layer 120 . Improve the channel mobility of semiconductor devices. The structure after annealing is shown in Figure 8.

As some implementation methods, the semiconductor device can be annealed at a high temperature of 1000°C for 90 minutes. It should be noted that when wet oxygen oxidation is used to form the gate oxide layer 130, wet oxygen oxidation is more conducive to the diffusion of nitrogen or phosphorus, and when high-temperature annealing is performed, the high-temperature annealing process can further reduce the humidity. Defects in the oxygen oxidation process, thereby improving gate oxide quality.

In addition, it should be noted that since the intrinsic polysilicon gate layer 140 uses intrinsic polysilicon, and the doping concentration of the second doped polysilicon layer 152 is greater than the doping concentration of the third doped polysilicon layer 153, for the entire polysilicon For each layer, the barrier distribution first increases and then decreases. This barrier distribution method is more conducive to the diffusion of impurity elements. The doping element P is added to the interface between the gate oxide layer 130 and the epitaxial layer 120 to improve the performance of the device. Channel mobility.

In some embodiments, along the direction from the third doped polysilicon layer to the gate oxide layer, the concentration of phosphorus doping in the first doped polysilicon layer gradually decreases. In some embodiments, the interface with the gate oxide layer and the epitaxial layer contains phosphorus element, and the epitaxial layer is a silicon carbide epitaxial layer. The thickness of the gate oxide layer is 40nm-60nm. The doping concentration of phosphorus in the gate oxide layer is 5E15/cm ² ~1E17/cm ² ; the doping concentration of phosphorus in the first doped polysilicon layer is 1E17/cm ² ~1E18/cm ² ; the second doping polysilicon The doping concentration of phosphorus element in the layer is 1E20/cm ² ~1E21/cm ² ; the doping concentration of phosphorus element in the third polysilicon layer is 1E18/cm ² ~1E20/cm ² . Since the intrinsic polysilicon gate layer 140 is intrinsic polysilicon, it can change the surface characteristics and increase the growth rate of in-situ doped polysilicon. Of course, an in-situ doping process may also be used to form the third doped polysilicon layer on the second doped polysilicon layer.

In some embodiments, based on the above implementation, please refer to FIG. 6. The present application also provides a semiconductor device, which is characterized in that the semiconductor device includes a substrate; an epitaxial layer located on the surface of the substrate; and an epitaxial layer located far away from the substrate. A gate oxide layer on one side, the gate oxide layer includes doping elements, and the doping elements include phosphorus; an intrinsic polysilicon layer located on the side of the gate oxide layer away from the substrate; a third layer of the intrinsic polysilicon layer located on the side away from the substrate A sub-polysilicon layer and a second sub-polysilicon layer located on the side of the first sub-crystalline silicon layer away from the substrate, the first sub-crystalline silicon layer and the second sub-crystalline silicon layer include doping elements, and the doping elements include phosphorus; wherein , the doping concentration of the first sub-polysilicon layer is greater than the doping concentration of the second sub-polysilicon layer. By controlling the concentration and thickness, a better quality doped polysilicon layer is obtained, thereby promoting the improvement of power device performance.

In some embodiments, the doping concentration of phosphorus in the first sub-polysilicon layer is 1E20/cm ² ~1E21/cm ² ; the doping concentration of phosphorus in the second sub-polysilicon layer is 1E18/cm ² ~1E20/cm ² .

In some embodiments, the thickness of the second sub-polysilicon layer is greater than the thickness of the first sub-polysilicon layer.

In some embodiments, the thickness of the gate oxide layer is 40nm-60nm.

As another implementation manner, some embodiments of the present application also provide another semiconductor device, which includes: a substrate; an epitaxial layer located on the surface of the substrate; a gate oxide layer located on the side of the epitaxial layer away from the substrate; The first doped polysilicon layer located on the side of the gate oxide layer away from the substrate; the second doped polysilicon layer located on the side of the first doped polysilicon layer away from the substrate; the second doped polysilicon layer located on the side away from the substrate The third doped polysilicon layer on one side; the doping elements in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer include phosphorus, the gate oxide layer includes doping elements, and the doping elements Including phosphorus; wherein the doping concentration of phosphorus element in the second doped polysilicon layer is greater than the doping concentration of phosphorus element in the third doped polysilicon layer. By controlling the concentration and thickness, a better quality doped polysilicon layer is obtained, thereby promoting the improvement of power device performance.

In some embodiments, the thickness of the third doped polysilicon layer is greater than the thickness of the second doped polysilicon layer.

In some embodiments, the thickness of the first doped polysilicon layer is 10~30nm; the thickness of the second doped polysilicon layer is 10~30nm; and the thickness of the third doped polysilicon layer is 350nm-750nm.

In some embodiments, the phosphorus element doping concentration in the second doped polysilicon layer is greater than the phosphorus element doping concentration in the first doped polysilicon layer.

In some embodiments, the doping concentration of the second doped polysilicon layer 152 is greater than the doping concentration of the third doped polysilicon layer 153 .

By arranging the second doped polysilicon layer 152 and the third doped polysilicon layer 153, the flow rate of the impurity source of the third doped polysilicon layer 153 can be reduced during the manufacturing process, thereby increasing the growth rate. For the entire polysilicon layer, the potential barrier distribution first increases and then decreases. This barrier distribution method is more conducive to the diffusion of impurity elements and the improvement of the overall performance of the polysilicon layer.

In some embodiments, along the direction from the third doped polysilicon layer to the gate oxide layer, the concentration of phosphorus doping in the first doped polysilicon layer gradually decreases. In some embodiments, the interface with the gate oxide layer and the epitaxial layer contains phosphorus element to improve the channel mobility of the device. In some embodiments, the epitaxial layer material is preferably a silicon carbide epitaxial layer. The thickness of the gate oxide layer is 40nm-60nm. The doping concentration of phosphorus in the gate oxide layer is 5E15/cm ² ~1E17/cm ² ; the doping concentration of phosphorus in the first doped polysilicon layer is 1E17/cm ² ~1E18/cm ² ; the second doping polysilicon The doping concentration of phosphorus element in the layer is 1E20/cm ² ~1E21/cm ² ; the doping concentration of phosphorus element in the third doped polysilicon layer is 1E18/cm ² ~1E20/cm ² .

In some embodiments, the thickness of the second doped polysilicon layer 152 is 10~30 nm, the thickness of the intrinsic polysilicon gate layer 140 is 10~30 nm, and the sum of the thicknesses of the intrinsic polysilicon gate layer 140 and the doped polysilicon layer is 400~800nm.

Through the above thickness setting, the thickness of the intrinsic polysilicon gate layer 140 and the second doped polysilicon layer 152 is relatively thin, while the thickness of the third doped polysilicon layer 153 is thicker, and the growth of the third doped polysilicon layer 153 The fastest speed, thus increasing the overall speed of the polysilicon layer.

The above descriptions are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included in the protection scope of this application.

It is obvious to those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as illustrative and non-restrictive from any point of view, and the scope of the application is defined by the appended claims rather than the above description, and it is therefore intended that all claims falling within the claims All changes within the meaning and scope of the equivalent elements are included in this application. Any reference signs in the claims shall not be construed as limiting the claim in question.

Claims

A semiconductor device, characterized in that the semiconductor device includes:

substrate;

an epitaxial layer located on the surface of the substrate;

a gate oxide layer located on the side of the epitaxial layer away from the substrate;

a first doped polysilicon layer located on the side of the gate oxide layer away from the substrate;

a second doped polysilicon layer located on the side of the first doped polysilicon layer away from the substrate; a third doped polysilicon layer located on the side of the second doped polysilicon layer away from the substrate;

The doping elements in the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer include phosphorus, the gate oxide layer includes doping elements, and the doping elements Includes phosphorus.
The semiconductor device according to claim 1, wherein the doping concentration of phosphorus element in the second doped polysilicon layer is greater than the doping concentration of phosphorus element in the third doped polysilicon layer.
The semiconductor device according to claim 1, wherein the doping concentration of phosphorus element in the second doped polysilicon layer is greater than the doping concentration of phosphorus element in the first doped polysilicon layer.
The semiconductor device according to claim 1, wherein along the direction from the third doped polysilicon layer to the gate oxide layer, the concentration of phosphorus doping in the first doped polysilicon layer gradually decreases. .
The semiconductor device according to claim 4, wherein the gate oxide layer contains phosphorus at an interface with the gate oxide layer and the epitaxial layer, and the epitaxial layer material is silicon carbide.
The semiconductor device according to claim 1, wherein the doping concentration of phosphorus element in the gate oxide layer is 5E15/cm 2 ~1E17/cm 2 , and the doping concentration of phosphorus element in the first doped polysilicon layer is The impurity concentration is 1E17/cm 2 ~1E18/cm 2 , the doping concentration of phosphorus element in the second doped polysilicon layer is 1E20/cm 2 ~1E21/cm 2 , the phosphorus element in the third doped polysilicon layer The doping concentration is 1E18/cm 2 ~1E20/cm 2 .
The semiconductor device according to claim 1, wherein the doping in the gate oxide layer, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer Elements include phosphorus and nitrogen.
The semiconductor device according to claim 7, wherein the doping in the gate oxide layer, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer The elements are phosphorus and nitrogen.
The semiconductor device of claim 1, wherein the thickness of the third doped polysilicon layer is greater than the thickness of the second doped polysilicon layer.
The semiconductor device according to claim 9, wherein the thickness of the first doped polysilicon layer is 10~30nm,

The thickness of the second doped polysilicon layer is 10~30nm,

The thickness of the third doped polysilicon layer is 350nm-750nm.
The semiconductor device of claim 1, wherein the second doped polysilicon layer is fabricated through an in-situ doping process.
A method for manufacturing a semiconductor device, characterized in that the method includes the following steps:

provide a substrate;

forming an epitaxial layer on the substrate;

forming a gate oxide layer on the epitaxial layer;

forming an intrinsic polysilicon gate layer on the gate oxide layer;

forming a second polysilicon layer on the intrinsic polysilicon gate layer;

A third polysilicon layer is formed on the second polysilicon layer; wherein the doping elements in the second polysilicon layer and the third polysilicon layer include phosphorus, and the second polysilicon layer The doping concentration of phosphorus element in the crystalline silicon layer is greater than the doping concentration of phosphorus element in the third polysilicon layer;

The phosphorus element in the second polysilicon layer is diffused into the intrinsic polysilicon layer and the gate oxide layer, so that the intrinsic polysilicon gate layer is transformed into a first doped polysilicon layer, and the second polysilicon layer is The silicon layer transforms into a second doped polysilicon layer.
The method of manufacturing a semiconductor device according to claim 12, wherein the thickness of the third polysilicon layer is greater than the thickness of the second polysilicon layer.
The method of manufacturing a semiconductor device according to claim 12, wherein the thickness of the intrinsic polysilicon layer is 10 to 30 nm.
The semiconductor device manufacturing method according to claim 13, characterized in that:

The thickness of the second polysilicon layer is 10~30nm,

The thickness of the third polysilicon layer is 350nm-750nm.
The method of manufacturing a semiconductor device according to claim 12, wherein the doping concentration of phosphorus element in the gate oxide layer is 5E15/cm 2 ~1E17/cm 2 , and the phosphorus element in the first doped polysilicon layer The doping concentration of the phosphorus element in the second doped polysilicon layer is 1E17/cm 2 ~1E18/cm 2 , the doping concentration of the phosphorus element in the second doped polysilicon layer is 1E20/cm 2 ~1E21/cm 2 , and the doping concentration of the phosphorus element in the third polysilicon layer The doping concentration of phosphorus element is 1E18/cm 2 ~1E20/cm 2 .
The semiconductor device manufacturing method as claimed in claim 12, characterized in that,

An in-situ doping process is used to form the second polysilicon layer on the intrinsic polysilicon gate layer, and an in-situ doping process is used to form a third polysilicon layer on the second doped polysilicon layer.
The semiconductor device manufacturing method according to claim 12, characterized in that:

An annealing process is used to diffuse the phosphorus element in the second doped polysilicon layer into the intrinsic polysilicon layer and the gate oxide layer.
The method of manufacturing a semiconductor device according to claim 12, wherein a wet oxygen oxidation process is used to form the gate oxide layer on the epitaxial layer.
The method of manufacturing a semiconductor device according to claim 12, wherein the gate oxide layer contains phosphorus at an interface with the gate oxide layer and the epitaxial layer, and the epitaxial layer material is silicon carbide.