JP4052622B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a fine gate length, and more particularly to a semiconductor device having a highly integrated field effect transistor and a manufacturing method thereof.
[0002]
[Prior art]
With the high integration and miniaturization of semiconductor integrated circuits, it is necessary to form devices with a smaller area and higher density. However, as the transistor gate length of a semiconductor having a field effect transistor becomes shorter, Deterioration of transistors due to the short channel effect and hot carrier injection has become prominent, and has become a major problem in increasing the integration and miniaturization of semiconductor devices.
[0003]
For example, in a field effect transistor used at a normal voltage, the short channel effect is not a particularly significant problem when the gate length is about 0.4 μm.
[0004]
Here, the short channel effect is a phenomenon in which the threshold voltage decreases as the gate length of the field effect transistor decreases. For example, when the gate length is shorter than 0.25 μm, the threshold value is drastically lowered. In this case, the leakage current of the transistor increases rapidly, the function as a switch is lost, and normal operation as a semiconductor device cannot be obtained.
[0005]
In addition, the deterioration of the transistor due to hot carrier injection becomes significant when the gate length is shortened and the operating voltage is not lowered. That is, the threshold is lowered by injecting carriers into the gate oxide film.
[0006]
That is, when the operating voltage is high, the time until the threshold decreases by 10% is shortened. Even with the same gate length, as the operating voltage increases, the time until the threshold value decreases rapidly decreases.
[0007]
However, in a DRAM or the like, it is difficult to lower the operating voltage, and in order to realize a large storage capacity in a small area, it is necessary to achieve high integration, so the gate length must be shortened. Therefore, the transistor deteriorates due to the short channel effect and hot carrier injection.
[0008]
In order to solve this problem, various ingenuity has been made such as reducing the junction depth of the electrode part or reducing the temperature of the thermal process after the electrode is formed.
[0009]
In other words, the junction depth of the source / drain is made shallow, an electrode is formed in a range in which on / off of the transistor can be controlled by the gate, and the junction depth of the electrode portion is made shallow.
[0010]
In addition, after forming the source / drain junction, the temperature is lowered to 900 ° C. or lower in a normal heat treatment step to lower the temperature of the heat treatment step. Note that heat treatment is performed for a short time of about 950 ° C. for 10 seconds or 1000 ° C. for about 5 seconds even at high temperature and high temperature in the activation process.
[0011]
Thus, by lowering the temperature of the heat treatment step after forming the electrode, the junction depth of the shallowly formed source / drain is not further extended after the formation. For example, the thermal process after electrode formation is performed by RTA (Rapid Thermal Anneal), the temperature is raised to a temperature sufficient to move the impurities to the lattice position, and no unnecessary heat is applied. To.
[0012]
For example, in order to prevent transistor deterioration due to hot carrier injection, as shown in FIG. 23, an LDD (Lightly Doped Drain) structure is employed to reduce the electric field, and a silicon nitride film or the like is used as a spacer material to form a wiring contact in the electrode lead portion. The device is highly self-aligned and highly integrated.
[0013]
That is, as shown in FIG. 23, the gate electrode 102 is formed on the semiconductor substrate 100 with the gate oxide film 101 interposed. A silicon nitride film 103 is formed on the gate electrode 102. Further, a post-gate oxide film 104 is formed on the side surface of the gate electrode 102. A silicon nitride film spacer 105 is provided in contact with the silicon nitride film 103 and the post-gate oxide film 104.
[0014]
With this silicon nitride film spacer 105 as a mask, a high concentration electrode diffusion layer 106 in which impurities are implanted in the semiconductor substrate 100 is provided so as to function as a source / drain. An LDD 107 is formed in the semiconductor substrate 100 on the gate electrode 102 side of the high concentration electrode diffusion layer 106.
[0015]
Next, a conventional LDD transistor manufacturing method will be described with reference to FIGS.
[0016]
As shown in FIG. 17, a gate oxide film 101 is formed on a semiconductor substrate 100, and a gate electrode 102 and a silicon nitride film 103 having a predetermined shape are sequentially formed thereon.
[0017]
Next, as shown in FIG. 18, a post-gate oxide film 104 is formed on the side surface of the gate electrode 102 and the exposed surface of the semiconductor substrate 100.
[0018]
Next, as shown in FIG. 19, an LDD 107 is formed in the semiconductor substrate 100 using the silicon nitride film 103, the gate electrode 102, and the post-gate oxide film 104 as a mask.
[0019]
Next, as shown in FIG. 20, a silicon nitride film spacer 105 is formed on the entire surface.
[0020]
Next, as shown in FIG. 21, the silicon nitride film spacer 105 on the silicon nitride film 103 and the semiconductor substrate 100 is removed, and the silicon nitride film spacer 105 is formed only on the side wall portion of the gate electrode 102.
[0021]
Next, as shown in FIG. 22, the high concentration electrode diffusion layer 106 is formed using the silicon nitride film 103 and the silicon nitride film spacer 105 as a mask.
[0022]
Next, as shown in FIG. 23, an electrode contact 108 for connecting to the high concentration electrode diffusion layer 106 is provided in contact with the silicon nitride film spacer 105.
[0023]
In addition, with miniaturization, high-concentration electrode prefabrication and low-concentration (LDD) electrode post-fabrication manufacturing methods are also required to minimize changes in the junction depth of the electrode section due to the process heat process. .
[0024]
That is, a conventional manufacturing method for forming a high concentration electrode and forming a low concentration (LDD) electrode will be described with reference to FIGS.
[0025]
First, as shown in FIG. 24, a gate oxide film 101, a gate electrode 102, and a silicon nitride film 103 are sequentially formed on a semiconductor substrate 100.
[0026]
Next, as shown in FIG. 25, a post-gate oxide film 104 is formed on the side surface of the gate electrode 102 and the surface of the semiconductor substrate 100.
[0027]
Next, as shown in FIG. 26, a silicon nitride spacer 105 is formed on the entire surface.
[0028]
Next, as shown in FIG. 27, the silicon nitride film spacer 105 is removed from portions other than the side walls of the silicon nitride film 103 and the gate electrode 102 to form a side wall shape, thereby forming the silicon nitride film 103, the gate electrode 102, and the silicon nitride film spacer 105. As a mask, the high concentration electrode diffusion layer 106 is formed by impurity implantation.
[0029]
Next, as shown in FIG. 28, the silicon nitride film spacer 105 is removed by wet etching, and an LDD 107 is formed in the semiconductor substrate 100 using the gate electrode 102 and the post-gate oxide film 104 as a mask.
[0030]
Next, as shown in FIG. 29, a contact electrode 108 connected to the high concentration electrode diffusion layer 106 is formed.
[0031]
In addition, as the use of semiconductor devices diversifies, it is important to provide a single integrated circuit with a large number of functions, and in order to achieve such a purpose, various types of field effect transistors are integrated into one integrated circuit. It must be formed on top.
[0032]
In other words, the semiconductor memory device is optimized by varying the characteristics of each transistor in accordance with functions such as a memory cell transistor, a logic portion transistor, and an input / output portion transistor.
[0033]
Next, a manufacturing method for forming various types of field effect transistors on one integrated circuit will be described with reference to FIGS.
[0034]
As shown in FIG. 30, a switching transistor region 110, a large current transistor region 111, and a low voltage transistor region 112 are provided on the semiconductor substrate 100. In each region, a gate electrode 102, a silicon nitride film 103 formed on the gate electrode 102, and a post-gate oxide film 104 are provided on the side surface of the gate electrode 102. Although not shown, an element isolation region is actually provided between each of the switching transistor region 110, the large current transistor region 111, and the low voltage transistor region 112.
[0035]
Next, as shown in FIG. 31, a photoresist 113 for performing photolithography is formed in addition to the switching transistor region 110. In the switching transistor region 110, the LDD 114 is formed on the side surfaces of the silicon nitride film 103 and the gate electrode 102 using the post-gate oxide film 104 as a mask. Subsequently, after removing the photoresist 113, a silicon nitride film serving as a spacer is formed on the entire surface by CVD, and annealing is performed.
[0036]
Next, as shown in FIG. 32, a silicon nitride film spacer 115 is formed on each transistor side wall, and a photoresist 116 for performing photolithography is formed in addition to the switching transistor region 110. The high concentration electrode 117 is formed using the silicon nitride film 103 and the silicon nitride film spacer 115 in the switching transistor region 110 as a mask.
[0037]
Next, as shown in FIG. 33, the silicon nitride film spacer 115 is removed, and a photoresist 118 for performing photolithography is formed in addition to the large current transistor region 111. In the large current transistor region 111, an LDD 119 is formed on the side surfaces of the silicon nitride film 103 and the gate electrode 102 using the post-gate oxide film 104 as a mask. Subsequently, after removing the photoresist 118, a silicon nitride film serving as a spacer is formed on the entire surface by the CVD method and annealed.
[0038]
Next, as shown in FIG. 34, silicon nitride film spacers 120 are formed on the sidewalls of the transistors, and a photoresist 121 for performing photolithography is formed in addition to the large current transistor region 111. The high concentration electrode 122 is formed using the silicon nitride film 103 and the silicon nitride film spacer 120 in the large current transistor region 111 as a mask.
[0039]
Next, as shown in FIG. 35, the silicon nitride spacer 120 is removed, and a photoresist 123 for performing photolithography is formed in addition to the low voltage transistor region 112. In the low voltage transistor region 112, the LDD 124 is formed on the side surfaces of the silicon nitride film 103 and the gate electrode 102 using the post-gate oxide film 104 as a mask. Subsequently, after removing the photoresist 123, a silicon nitride film serving as a spacer is formed on the entire surface by CVD, and annealing is performed.
[0040]
Next, as shown in FIG. 36, a silicon nitride film spacer 125 is formed on each transistor side wall, and a photoresist 126 for performing photolithography is formed in addition to the low voltage transistor region 112. A high concentration electrode 127 is formed using the silicon nitride film 103 and the silicon nitride film spacer 125 in the low voltage transistor region 112 as a mask.
[0041]
Next, as shown in FIG. 37, the photoresist 126 and the silicon nitride film spacer 125 are removed, and three types of transistors are formed on the semiconductor substrate.
[0042]
3 to 6 of Japanese Patent Laid-Open No. 11-313740, etc., a low concentration impurity diffusion layer is formed in a semiconductor substrate using a gate of a MOS transistor as a mask, and a gate sidewall made of an organic film is further formed. A manufacturing method for reducing a concentration gradient of a diffusion layer while forming a high-concentration diffusion layer in a semiconductor substrate using a sidewall as a mask, removing the sidewall by ashing, forming a thick sidewall, and reducing processes. Are listed.
[0043]
[Problems to be solved by the invention]
Conventionally, when a transistor is formed by an electrode tip manufacturing method, a complicated process must be adopted as shown in FIGS. 24 to 29, and the electrode forming contact is formed on the side wall of the silicon nitride film. It is difficult to form in a self-aligned manner, and this has been a major obstacle to forming a high-performance field-effect transistor with a small number of steps and a high degree of integration.
[0044]
Here, the high-performance field effect transistor means that even if the gate length is about 0.1 μm or less, the transistor threshold phenomenon due to the shortened gate length does not deviate from the design value of the circuit operation. It means having.
[0045]
Even if the short channel effect is suppressed using the conventional electrode tip preparation process, if the gate sidewall self-alignment method is not used in forming the contact to the source / drain, the contact between the gate and the source / drain contact The distance must be set large. That is, it is necessary to set the distance between the gate and the source / drain contact larger by a value obtained by estimating the alignment margin of the PEP (Photo Engraving Process) mask. For this reason, it is necessary to set the chip size of the semiconductor device large.
[0046]
In addition, forming the contact for electrode formation in a self-aligned manner by forming the spacer again after removing the spacer once is necessary because many heating steps are required for spacer formation. The process was long and complicated, making it difficult.
[0047]
That is, when forming the spacer, a TEOS film is deposited in an environment of, for example, 650 ° C. or a silicon nitride film is deposited in an environment of 725 ° C. by using a thermal CVD (Chemical Vapor Deposition) method. . In this forming method, 10 per minute. ^-3 Since the spacer material is deposited at a slow speed of about μm, it takes about one hour to reach the desired thickness, which hinders the improvement of the manufacturing process efficiency. .
[0048]
Furthermore, since the CVD method is used when the spacer is formed for the first time, heat is applied to the semiconductor substrate, the distribution of the impurity diffusion layer is disturbed, and the spacer for self-alignment at the time of contact formation is once again formed. In the formation, the abnormal diffusion, which is the disorder of the distribution of the impurity diffusion layer, becomes more remarkable, and the characteristics of the semiconductor device are likely to deteriorate.
[0049]
Further, when removing the spacer once formed by the CVD method, it is necessary to perform wet etching while maintaining a large selection ratio between the silicon nitride film and the oxide film due to the properties of the film. Even in this case, the gate oxide film under the gate electrode may be etched from the side surface, which may adversely affect the characteristics of the transistor.
[0050]
In addition, as the use of semiconductors diversifies, it is important to provide a single integrated circuit with a large number of functions, and in order to achieve this purpose, many types of field effect transistors are combined into one integrated circuit. It must be formed on top.
[0051]
In order to achieve this object with the conventional method, the ED effect (Transient Enhanced Diffusion) is suppressed by using a number of thermal processes to optimize the electrode structure, and the junction depth of the electrode structure is set to each field effect type. It must be optimized with a transistor, requires a very complicated process, and it is difficult to produce a large number of field-effect transistors with good controllability.
[0052]
That is, as shown in FIGS. 30 to 37, a spacer for forming a high concentration source / drain electrode first is formed, PEP is performed, and ion implantation is performed. Thereafter, the spacer is peeled off, LDP PEP is performed, and ion implantation is performed again. After that, a series of manufacturing processes for performing RTA need to be repeated for different transistors by the number of types of transistors, which is a very complicated process.
[0053]
Further, in each transistor process, a phenomenon occurs in which the length of the diffusion layer extends under the gate of the source / drain implanted for each first spacer under the process of forming another transistor. Further, the RIE process is stopped at the position of the oxide film formed on the semiconductor substrate around the gate.
[0054]
However, the thickness of the oxide film formed on the surface of the semiconductor substrate differs from part to part by RIE, and the film thickness is not uniform. For this reason, the variation in the thickness of the oxide film remaining on the surface of the semiconductor substrate before ion implantation becomes large, the variation in the depth of implantation into the semiconductor substrate during ion implantation becomes large, and impurities are formed. The controllability of the area to be deteriorated.
[0055]
The TED effect is to diffuse at a faster rate than usual through the introduced defects in the impurity-implanted ion implantation. If the impurity is kept at the interstitial position by the TED effect, the impurity diffuses abnormally early by the TED effect. Therefore, before heat is applied, it is necessary to perform annealing such as activation RTA to move the impurities to the appropriate lattice positions.
[0056]
Here, since the heat that generates the TED effect is generated even by the heat at the time of depositing the silicon oxide film by the CVD method, in order to prevent the abnormal diffusion of impurities due to the TED effect, the annealing process is performed for each deposition process of the insulating film or the like. -It is necessary to repeat the process.
[0057]
That is, conventionally, SiN or SiO ₂ Thus, a spacer is formed, and it takes a long time until the spacer is formed by performing a two-step heating process of about 650 ° C. to 725 ° C. by thermal CVD.
[0058]
Furthermore, in order to remove the formed spacers, it is necessary to use wet etching or dry etching, resulting in a complicated process.
[0059]
An object of the present invention is to solve the above-described problems of the prior art.
[0060]
In particular, an object of the present invention is to produce a high-performance field-effect transistor according to the application without complicating the manufacturing process, and to dramatically improve the degree of integration of semiconductor devices. A semiconductor device and a method for manufacturing the same are provided.
[0061]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is characterized in that a gate electrode and a gate electrode upper insulating film are formed on a semiconductor substrate, and on the semiconductor substrate, on the periphery of the gate electrode, and on the gate. An acrylic polymer, an aromatic sulfur compound, and glycoluril, which are mainly composed of ethyl lactate and 1-methoxy-2-propyl acetate used as an antireflection film for lithography as a first diffusion layer mask material on the electrode upper insulating film Forming a mixture containing a small amount of resin; forming a resist on the first diffusion layer mask material; providing an opening in the resist; and forming the first diffusion layer mask material in the opening portion as the gate electrode and A step of removing so as to leave on the side surface of the gate electrode upper insulating film, and the half of the first diffusion layer mask material left as a mask. A step of forming a first diffusion layer in the body substrate; a step of removing the remaining first diffusion layer mask material by ashing; and the gate electrode and the gate electrode upper insulating film as a mask. Forming a second diffusion layer in the semiconductor substrate; forming a gate sidewall on a side surface of the gate electrode and the gate electrode upper insulating layer; and being in contact with the gate sidewall and connected to the first diffusion layer And a step of forming an electrode contact.
[0062]
Another feature of the present invention is that a first gate electrode is formed on a semiconductor substrate, a first gate electrode upper insulating film is formed on the first gate electrode, and a second gate is formed on the semiconductor substrate. Forming an electrode and forming a second gate electrode upper insulating film on the second gate electrode; and on the semiconductor substrate, on the periphery of the first gate electrode, on the first gate electrode upper insulating film, 2) Mainly composed of ethyl lactate and 1-methoxy-2-propyl acetate used as an antireflection film for lithography on the periphery of the two gate electrodes and on the second gate electrode upper insulating film, acrylic polymer, aromatic sulfur compound, and glycol Forming a mixture containing a small amount of uril resin as a first diffusion layer mask material; forming a first resist on the first diffusion layer mask material; and Removing the first resist in the region, and leaving the first diffusion layer mask material on the first gate electrode side surface and the first gate electrode upper insulating film side surface by a first thickness. Removing from the periphery of the gate electrode, and forming a first diffusion layer in the semiconductor substrate using the first diffusion layer mask material left on the first gate electrode side surface and the first gate electrode upper insulating film side surface as a mask A step of removing the remaining first resist and the first diffusion layer mask material by an ashing process, on the semiconductor substrate, on the periphery of the first gate electrode, and on the first gate electrode upper insulation. Mainly composed of ethyl lactate and 1-methoxy-2-propyl acetate used as an antireflection film for lithography on the film, on the periphery of the second gate electrode, and on the second gate electrode upper insulating film Forming a mixture containing a small amount of an acrylic polymer, an aromatic sulfur compound, and a glycoluril resin as a second diffusion layer mask material, forming a second resist on the second diffusion layer mask material, and Removing the second resist in the second region; and a second thickness different from the first thickness on the second gate electrode side surface and the second gate electrode upper insulating film side surface with the second diffusion layer mask material A step of removing from the periphery of the second gate electrode so as to leave a portion, and the semiconductor using the second diffusion layer mask material left on the side surface of the second gate electrode and the side surface of the second gate electrode upper insulating film as a mask A step of forming a second diffusion layer in the substrate; a step of removing the remaining second resist and the second diffusion layer mask material by ashing; a side surface of the first gate electrode; Forming a first gate side wall on a side surface of the first gate electrode upper insulating layer; and forming a second gate side wall on the side surface of the second gate electrode and the side surface of the second gate electrode upper insulating layer. A feature of the present invention is a method for manufacturing a semiconductor device.
[0064]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.
[0065]
(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. Here, a manufacturing method of an LDD field effect transistor using a high concentration source / drain electrode pre-fabrication process using the present invention will be described.
[0066]
Here, the high concentration source / drain electrode pre-fabrication means a method in which a high concentration diffusion layer to be a source / drain electrode is first formed and then an LDD layer is formed.
[0067]
In this way, by using the high concentration source / drain electrode pre-fabrication manufacturing method, the LDD layer extends under the gate due to the diffusion caused by the thermal process at the time of spacer formation after the LDD formation, which has been conventionally produced, and the transistor characteristics are improved. Deviation from the design value can be prevented.
[0068]
FIG. 2 shows a cross-sectional shape after forming a gate oxide film 2 on a semiconductor substrate 1, depositing a gate electrode material thereon, processing the silicon nitride film 4 as a mask material, and forming a gate electrode 3. Indicates.
[0069]
Next, as shown in FIG. 3, the surface of the gate electrode 3 is oxidized as necessary, and a post-gate oxide film 5 is formed on the side surface of the gate electrode 3 and the surface of the semiconductor substrate 1. The post-gate oxide film 5 is formed with a film thickness of about 10 nm, for example.
[0070]
Note that no post-oxide film is formed on the surface of the silicon nitride film 4.
[0071]
That is, it is appropriate to oxidize the surface of the gate electrode in order to prevent impurities from being implanted into the gate material when performing impurity ion implantation for forming the LDD region through the gate electrode.
[0072]
Next, as shown in FIG. 4, an organic film coating layer (usually an antireflection film for lithography) 6 is applied according to the required film thickness, and then a resist 7 for lithography is applied to perform lithography for electrode formation. . The organic film coating process can be performed within 1 minute, for example, and can be formed in a very short time.
[0073]
Here, the organic film coating layer to be used needs to be able to be applied at room temperature or at a temperature up to about 250 ° C. 10 ^-1 It is necessary that the organic film has a property that it can be formed with good followability on the organic film coating layer on which a film having a thickness of about μm is formed, that is, a property with good coverage. Furthermore, as a property required for the organic film, it is necessary that the property of the film does not deteriorate even if a resist is formed on the organic film after the organic film is formed. Furthermore, it is necessary to process using RIE while maintaining a selection ratio with the resist, and to be usable as a mask material for ion implantation. Furthermore, the organic film is required to have a property that can be easily removed in the resist peeling step.
[0074]
As the organic film having the above-described properties, an organic film used as an antireflection film for lithography can be used. As the organic film, for example, a mixture containing ethyl lactate and 1-methoxy-2-propyl acetate as main components and further containing a small amount of an acrylic polymer, an aromatic sulfur compound, and a glycoluril resin can be used. The antireflection film for lithography was applied under the resist in order to prevent reflection due to the unevenness of the base, whereas the main purpose of this embodiment is to prevent reflection of the base. Instead, it is used as a film for processing.
[0075]
Here, the film thickness of the organic film is, for example, from about 0.01 μm to about 0. A thickness of about several μm is used, and a thickness of about 0.07 μm to about 0.1 μm is particularly preferable. That is, the thickness corresponding to the length of the portion where the LDD region to be formed in a later step is formed is formed to be the thickness of the organic film.
[0076]
Next, as shown in FIG. 5, a resist is deposited, an opening is provided by lithography, and processing is performed on the entire surface by anisotropic dry etching, below the portion covered with the resist other than the opening. The organic film coating layer remains in the electrode forming portion. In this way, the organic film coating layer spacer 8 is formed on the side surface of the gate 3, and the organic film coating layer is removed from other regions.
[0077]
Next, as shown in FIG. 6, impurity implantation is performed using the gate 3, the silicon nitride film 4 on the gate 3, and the organic film covering layer spacer 8 on the side surface of the gate 3 as a mask, so that a high concentration source / drain diffusion layer is formed. 9 is formed.
[0078]
In this process, the spacer material is different from that of the conventional process shown in FIG. 20, so that the temperature at the time of spacer formation can be lowered. For this reason, the phenomenon that the impurity concentration profile of the well portion becomes gentle due to the influence of heating can be suppressed. Further, in the spacer RIE process, the amount of oxide film remaining on the surface of the semiconductor substrate can be reduced as compared with the conventional example.
[0079]
At this time, the portion other than the electrode forming portion is covered with a photoresist for lithography, and no impurities are implanted.
[0080]
Next, as shown in FIG. 7, a high-concentration source / drain diffusion layer 9 is easily formed at a stage where a resist stripping process after normal lithography is performed thereafter.
[0081]
That is, only the spacer is peeled off, and a shape leaving the silicon oxide film on the gate electrode can be obtained by performing the resist peeling treatment. The side wall of the formed organic film is peeled off by ashing. Since the organic film does not need to be removed by wet etching, the side surface of the gate oxide film is not adversely affected, and deterioration of transistor characteristics can be prevented.
[0082]
On the other hand, in the conventional example, between the steps shown in FIGS. 27 and 28, the silicon nitride film on the gate electrode is peeled off in the step of peeling off the spacer nitride film, as in this embodiment. The shape cannot be obtained.
[0083]
Here, the high concentration source / drain means a high concentration source / drain which is usually used. ¹⁵ / Cm ² A dose amount of impurities at the time of ion implantation of the base is contained. That is, at least 1 × 10 ¹⁷ / Cm ^Three To 2 × 10 ¹⁷ / Cm ^Three Above, at the peak position, 1 × 10 ²⁰ / Cm ^Three It is formed at a concentration exceeding.
[0084]
Next, as shown in FIG. 8, with the silicon nitride film 4, the gate 3, and the post-gate oxide film 5 as a mask, the semiconductor substrate 1 has a relatively low concentration LDD or a relatively high concentration as required. Impurity implantation called extension is performed to obtain an LDD (extension) 10.
[0085]
Here, the LDD having a relatively low concentration is, for example, 1 × 10. ¹³ / Cm ² The ion implantation dose is about 1 × 10 at the peak position. ¹⁸ / Cm ^Three The concentration is about.
[0086]
For extensions with relatively high concentrations, for example, 1 × 10 ¹⁴ / Cm ² The ion implantation dose is about 1 × 10 at the peak position. ¹⁹ / Cm ^Three The concentration is about. Thereafter, heating is performed to activate impurities in the source / drain high concentration diffusion layer 9 and the LDD (extension) 10 formed in the semiconductor substrate.
[0087]
Next, as shown in FIG. 9, if the spacers 11 are formed with a silicon nitride film or the like as required, electrode contacts can be formed in a self-aligning manner. The spacer is formed with a thickness of, for example, about 0.2 μm depending on the breakdown voltage of the transistor.
[0088]
Next, as shown in FIG. 1, after covering the entire surface with an insulating film by CVD or the like, a contact hole is opened, a conductive film is buried therein, and a desired electrode is connected to obtain a semiconductor device.
[0089]
A contact electrode 12 is formed in contact with the spacer 11 so as to be connected to the source / drain high concentration diffusion layer 9. In this manner, the contact electrode 12 can be formed in a self-aligned manner on the spacer 11 provided on the gate side wall, whereby high integration can be achieved.
[0090]
Since the contact electrode 12 can be formed on the spacer 11 in a self-aligning manner as described above, it is not necessary to provide a margin for alignment with the contact electrode 12 in the region of the high concentration source / drain diffusion layer 9, and the transistor operation is performed. Above, the minimum necessary region may be formed as the region of the source / drain high concentration diffusion layer 9.
[0091]
Thus, the semiconductor device of the present embodiment includes the semiconductor substrate 1, the gate electrode 3 formed on the semiconductor substrate 1, the spacer 11 provided in contact with the side surface of the gate electrode 3, and the gate electrode 3. A gate electrode upper insulating film 4 surrounded by a side surface of the spacer 11, a contact electrode 12 provided in contact with the spacer 11, and a film other than the spacer 11 connected to the contact electrode 12. Using the organic film 8 as a mask, the high concentration source / drain diffusion layer 9 formed in the semiconductor substrate 1 and the gate electrode in the semiconductor substrate 1 after the high concentration source / drain diffusion layer 9 is formed. And an LDD (extension) 10 formed using 3 as a mask.
[0092]
Although the formed organic film coating layer spacer is peeled off by ashing treatment, since this ashing treatment is not a heating step, by performing this embodiment other than the heating step used in normal ion implantation or PEP, There is no need for heating or additional manufacturing steps. Therefore, the deterioration of the transistor due to the short channel effect or hot carrier injection can be prevented. As described above, in this embodiment, even a transistor having a gate length of about 0.1 μm or less can achieve high performance while achieving high integration.
[0093]
In the manufacturing method, when an NMOS transistor is formed on the entire surface of the semiconductor substrate before the step shown in FIG. 2, impurities such as phosphorus having a very low concentration may be introduced.
[0094]
Further, after the step shown in FIG. 9, in the case of forming an NMOS transistor at an angle of 20 degrees with respect to the surface of the semiconductor substrate by halo ion implantation using the organic film covering layer spacer and the gate as a mask, impurities such as boron For example, the concentration is about 4 × 10 ¹³ / Cm ² It may be introduced to the extent. FIG. 10 shows a state in which the halo impurity region 13 is formed so as to surround the LDD 10 by this halo ion implantation.
[0095]
Furthermore, it is also possible to provide a multi-stage impurity region in the semiconductor substrate by changing the implantation angle and dose amount of impurity implantation and introducing and heating the impurity many times using the organic film coating layer spacer. is there.
[0096]
Furthermore, the organic film coating layer spacer is formed with different film thicknesses several times according to the multi-stage impurity region introduced into the semiconductor substrate, and the process of impurity introduction, heating, and side wall removal is repeated to make the process more complicated. It is also possible to form various types of impurity diffusion layers in the semiconductor substrate near the gate.
[0097]
(Second Embodiment)
A method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
[0098]
As shown in FIG. 11, a transistor is formed on each semiconductor substrate 1, a switching transistor region 20 in which a switching transistor is formed, a large current transistor region 21 in which a large current transistor is formed, and a low voltage transistor. A voltage transistor region 22 is provided. Each transistor is provided with a gate 3 on a semiconductor substrate 1 via a gate oxide film 2 as in the first embodiment.
[0099]
A post-gate oxide film 5 is formed on the side surface of the gate 3. A silicon nitride film 4 is formed on the upper surface of the gate 3. Here, an organic film is formed above each transistor to cover the entire surface of the semiconductor substrate 1, the post-gate oxide film 5, and the silicon nitride film 4. Here, first, only the large current transistor region 21 is exposed from the resist 23, and lithography is performed.
[0100]
Next, organic film spacers 24 are formed only on the sidewalls of the transistors in the large current transistor region 21, and other organic films are removed from the large current transistor region 21. Thereafter, the high concentration source / drain regions 25 are formed using the organic film spacer 24 as a mask for impurity implantation. In the large current transistor region 21 that requires a large current driving capability, a setting such as shortening the distance from the gate end to the high-concentration source / drain is adjusted by changing the film thickness of the spacer to obtain a larger current. Can take a value.
[0101]
Next, as shown in FIG. 12, if the organic film coating layer 6 is peeled off by ashing and cleaning, a field effect transistor can be formed without going through a high-temperature thermal process. Here, the high temperature thermal process refers to a process of depositing a spacer oxide film and a nitride film by thermal CVD, and according to the present embodiment, such a spacer is formed by applying an antireflection film. A high-temperature heat process is not required. Here, after removing the organic film spacer 24, impurities are implanted into the semiconductor substrate 1 using the silicon nitride film 4, the gate 3, and the post-gate oxide film 5 as a mask to form an LDD 26.
[0102]
Thereafter, the switching transistor region 20 and the low-voltage transistor region 23 are sequentially manufactured by adjusting the spacer thickness and impurity concentration so as to obtain optimum characteristics in the same manner.
[0103]
Here, optimizing the field effect transistor means setting the effective gate length so as to prevent the threshold value from deviating from the design value even when the gate length of each transistor is miniaturized and short.
[0104]
In the switching transistor region 20 in which the switching characteristic is an important function, the cutoff characteristic is improved by increasing the distance from the gate end to the high-concentration source / drain and changing and adjusting the film thickness of the spacer. In the low voltage transistor region, the distance from the gate end to the high concentration source / drain is set short in order to reduce the area.
[0105]
Thereafter, the photoresist and the organic film coating layer are peeled off by ashing treatment and cleaning treatment, and activation annealing is performed to form a field effect transistor. Here, after removing the organic film spacer 24 made of an organic film as shown in FIG. 13, impurities are implanted into the semiconductor substrate 1 using the silicon nitride film 4, the gate 3, and the post-gate oxide film 5 as a mask. Then, the LDD layer 26 is formed.
[0106]
Here, the LDD layer is preferably formed when the gate length is short, or when the source / drain electric field is extremely strong.
[0107]
Next, as shown in FIG. 14, a second organic film coating layer 27 is newly formed on the entire surface so as to have an optimum sidewall thickness in other transistor regions. Thereafter, using the resist 28 in the same manner as the already formed transistor region, a high concentration source / drain region is formed, the second organic film covering layer 27 is removed, an LDD is formed, and other transistor regions are sequentially formed. It is formed by repeating the same manufacturing process.
[0108]
After the step of FIG. 14, an interlayer insulating film or the like is normally deposited on the top, but before the deposition step, after forming all the transistors in the semiconductor device, annealing is performed once. Here, the annealing temperature is, for example, 1050 ° C. and annealing for 3 seconds to 950 ° C. and annealing for about 10 seconds.
[0109]
Next, as shown in FIG. 15, if the spacers 11 are formed with a silicon nitride film or the like as required, electrode contacts can be formed in a self-aligning manner. The spacer is formed with a thickness of, for example, about 0.2 μm depending on the breakdown voltage of the transistor.
[0110]
Next, after an insulating film is coated on the entire surface by CVD or the like, a contact hole is formed, a conductive film is buried therein, and a desired electrode is connected to obtain the semiconductor device shown in FIG.
[0111]
A contact electrode 12 is formed in contact with the spacer 11 so as to be connected to the source / drain high concentration diffusion layer 9. In this manner, the contact electrode 12 can be formed in a self-aligned manner on the spacer 11 provided on the gate side wall, whereby high integration can be achieved.
[0112]
In this manner, an optimal field effect transistor can be formed for all transistors in the semiconductor device by using the same technique. If annealing for impurity activation is performed once thereafter, the abnormal diffusion due to the TED effect is finally suppressed, and each field effect transistor can be formed in an optimal and easy process.
[0113]
That is, in this embodiment, there is no thermal process in forming the spacer, and the spacer can be formed only by applying the antireflection film. For this reason, even if the spacer formation is repeated as many times as necessary for different types of transistors, the TED effect due to heat and the oxide film reduction phenomenon due to RIE do not occur. In this manner, an impurity diffusion layer can be formed by accurately injecting impurities into a position designed for each transistor.
[0114]
Thus, even if the steps of spacer formation, ion implantation, and spacer removal are repeated for each necessary number of times, there is no thermal process in each process, and therefore there is a low possibility that the TED effect will occur. When all the transistor formation steps are completed, for example, in order to suppress the TED effect due to the influence of heat in the step of forming the interlayer insulating film, RTA for activating the impurities is performed only once.
[0115]
In a semiconductor integrated circuit in which various field effect transistors are mixed, it becomes possible to efficiently produce field effect transistors according to various applications.
[0116]
Here, a sufficient amount of switching and a transistor and a large current transistor that needs to flow a large current are mounted on the same semiconductor device because a small amount of current flows in the on state without flowing a current in the off state. In this case, the side wall of the switching transistor is set to be thick, for example, about 0.3 μm when the gate width is smaller than about 0.75 μm.
[0117]
Further, in the case of a large current transistor, when the gate width is smaller than about 0.75 μm, the side wall has a thin film thickness of about 0.2 μm to several thousandths of a μm. In a large current transistor, the sidewall is thinned to shorten the LDD length, thereby preventing an increase in parasitic resistance.
[0118]
Also in this embodiment, a halo impurity region can be formed as in the first embodiment.
[0119]
Further, as in the first embodiment, the thickness of the impurities or organic film coating layer spacers that introduce the organic film coating layer spacer, introduce impurities into the semiconductor substrate, heat, and remove the organic film coating layer spacers multiple times are changed. By changing and repeating, a plurality of types of impurity regions can be formed on the semiconductor substrate.
[0120]
According to this embodiment, in a mixed semiconductor device in which a memory and a logic circuit are mixedly mounted, a transistor optimized for each transistor can be manufactured while suppressing an increase in the number of steps. That is, when forming each source / drain so as to match the gate length for each transistor, a series of processes such as spacer deposition, PEP, ion implantation, spacer peeling, and RTA are individually performed for each transistor of different size. It is possible to avoid repetition of the manufacturing process. As described above, in this embodiment, by repeating the manufacturing process of PEP and ion implantation for each transistor having a different size, a mixed semiconductor device can be obtained, and the number of manufacturing processes can be greatly reduced.
[0121]
This embodiment also has the same effect as the first embodiment.
[0122]
(Modification of the second embodiment)
The present modification can be applied to the case where each LDD region can be formed with the same characteristics even if the transistors have different characteristics. In this case, as shown in FIG. 16, high concentration source / drain regions are sequentially formed for each transistor region, and after removing all the organic films, the respective gates, silicon nitride films on the gates, and post-gate oxide films are formed. As a mask, an LDD region can be formed by impurity implantation. If the resist and the organic film coating layer are peeled off by ashing and cleaning, a field effect transistor can be formed without going through a high temperature thermal process. Here, the high temperature thermal process refers to a process of depositing a spacer oxide film and a nitride film by thermal CVD, and according to the present embodiment, such a spacer is formed by applying an antireflection film. A high-temperature heat process is not required.
[0123]
By forming in this way, the LDD region forming process can be performed at once, and the number of processes can be reduced. Further, an optimal field effect transistor can be optimally formed without going through a high temperature thermal process. When all the transistor formation steps are completed, for example, in order to suppress the TED effect due to the influence of heat in the step of forming the interlayer insulating film, RTA for activating the impurities is performed only once.
[0124]
Also in this embodiment, a halo impurity region can be formed as in the first embodiment.
[0125]
Further, as in the first embodiment, the thickness of the impurities or organic film coating layer spacers that introduce the organic film coating layer spacer, introduce impurities into the semiconductor substrate, heat, and remove the organic film coating layer spacers multiple times are changed. By changing and repeating, a plurality of types of impurity regions can be formed on the semiconductor substrate.
[0126]
In each of the above embodiments, the spacer is formed using an organic film. However, other films such as an inorganic film may be used as long as the film has the same characteristics as the organic film.
[0127]
The present invention is applied to a semiconductor device having a large-scale integrated circuit such as a volatile semiconductor memory device such as a DRAM, a nonvolatile semiconductor memory device, a logic LSI, or a memory-embedded logic LSI.
[0128]
【The invention's effect】
According to the present invention, a high-performance field-effect transistor can be produced in accordance with the application without causing a complicated manufacturing process, and the integration degree of a semiconductor device can be dramatically improved. A possible semiconductor device and a manufacturing method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device in the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the first embodiment of the present invention.
FIG. 11 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the second embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the second embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in a second embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 16 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device in a modification of the second embodiment of the present invention.
FIG. 17 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor device having an LDD structure.
FIG. 18 is a cross-sectional view showing a step of a conventional method of manufacturing a semiconductor device having an LDD structure.
FIG. 19 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device having an LDD structure.
FIG. 20 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device having an LDD structure.
FIG. 21 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor device having an LDD structure.
FIG. 22 is a cross-sectional view showing a step of a conventional method of manufacturing a semiconductor device having an LDD structure.
FIG. 23 is a cross-sectional view showing the structure of a conventional semiconductor device having an LDD structure.
FIG. 24 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device having an electrode tip-prepared LDD structure.
FIG. 25 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device having an electrode tip-prepared LDD structure.
FIG. 26 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device having an electrode tip-prepared LDD structure.
FIG. 27 is a cross-sectional view showing one step in a method of manufacturing a conventional semiconductor device having an electrode tip-prepared LDD structure.
FIG. 28 is a cross-sectional view showing one step in a method of manufacturing a conventional semiconductor device having an electrode tip-prepared LDD structure.
FIG. 29 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device having an electrode tip-prepared LDD structure.
FIG. 30 is a cross-sectional view showing a step of a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 31 is a cross-sectional view showing one step in a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 32 is a cross-sectional view showing one step in a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 33 is a cross-sectional view showing a step of a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 34 is a cross-sectional view showing one step of a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 35 is a cross-sectional view showing one step of a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 36 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device that optimizes a plurality of transistors.
FIG. 37 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device that optimizes a plurality of transistors.
[Explanation of symbols]
1 Semiconductor substrate
2 Gate oxide film
3 Gate
4 Silicon nitride film
5 Post-gate oxide film
6 Organic coating layer
7,28 resist
8 Organic coating layer spacer
9,25 High concentration source / drain diffusion layer
10, 26 LDD (extension)
11 Spacer
12 Contact electrode
13 Halo impurity region
20 Switching transistor region
21 High current transistor area
22 Low voltage transistor region
23 photoresist
24 Organic film spacer
27 Second organic coating

Claims (7)

Forming a gate electrode on the semiconductor substrate and a gate electrode upper insulating film on the gate electrode;
Mainly composed of ethyl lactate and 1-methoxy-2-propyl acetate used as an antireflection film for lithography as a first diffusion layer mask material on the semiconductor substrate, on the periphery of the gate electrode, and on the gate electrode upper insulating film Forming a mixture containing a small amount of an acrylic polymer, an aromatic sulfur compound, and a glycoluril resin ;
Forming a resist on the first diffusion layer mask material, providing an opening in the resist, and leaving the first diffusion layer mask material of the opening portion on the side surface of the gate electrode and the gate electrode upper insulating film; Removing, and
Forming a first diffusion layer in the semiconductor substrate using the remaining first diffusion layer mask material as a mask;
Removing the remaining first diffusion layer mask material by ashing;
Forming a second diffusion layer in the semiconductor substrate using the gate electrode and the gate electrode upper insulating film as a mask;
Forming a gate sidewall on a side surface of the gate electrode and the gate electrode upper insulating layer;
And a step of forming an electrode contact in contact with the gate sidewall and connected to the first diffusion layer. In the step of removing the first diffusion layer mask material so as to remain on the side surfaces of the gate electrode and the gate electrode upper insulating film, a thickness corresponding to the position of the first diffusion layer to be formed in the semiconductor substrate is set. has been manufacturing method of a semiconductor device according to claim 1, wherein said first diffusion layer mask material is removed so as to leave. Forming a first gate electrode on the semiconductor substrate and forming a first gate electrode upper insulating film on the first gate electrode;
Forming a second gate electrode on the semiconductor substrate and forming a second gate electrode upper insulating film on the second gate electrode;
Lactic acid used as an antireflection film for lithography on the semiconductor substrate, on the periphery of the first gate electrode, on the first gate electrode upper insulating film, on the periphery of the second gate electrode, and on the second gate electrode upper insulating film Forming as a first diffusion layer mask material a mixture containing ethyl and 1-methoxy-2-propyl acetate as a main component and a small amount of an acrylic polymer, an aromatic sulfur compound, and a glycoluril resin ;
Forming a first resist on the first diffusion layer mask material;
Removing the first resist in the first region;
Removing the first diffusion layer mask material from the periphery of the first gate electrode so as to leave a first thickness on the side surface of the first gate electrode and the side surface of the first gate electrode upper insulating film;
Forming a first diffusion layer in the semiconductor substrate using the first diffusion layer mask material left on the first gate electrode side surface and the first gate electrode upper insulating film side surface as a mask;
Removing the remaining first resist and the first diffusion layer mask material by ashing;
Lactic acid used as an antireflection film for lithography on the semiconductor substrate, on the periphery of the first gate electrode, on the first gate electrode upper insulating film, on the periphery of the second gate electrode, and on the second gate electrode upper insulating film Forming a mixture containing ethyl and 1-methoxy-2-propyl acetate as a main component and a small amount of an acrylic polymer, an aromatic sulfur compound, and a glycoluril resin as a second diffusion layer mask material;
Forming a second resist on the second diffusion layer mask material;
Removing the second resist in the second region;
The second diffusion layer mask material is removed from the periphery of the second gate electrode so as to leave a second thickness different from the first thickness on the side surface of the second gate electrode and the side surface of the second gate electrode upper insulating film. And a process of
Forming a second diffusion layer in the semiconductor substrate using the second diffusion layer mask material left on the second gate electrode side surface and the second gate electrode upper insulating film side surface as a mask;
Removing the remaining second resist and the second diffusion layer mask material by ashing;
Forming a first gate sidewall on the first gate electrode side surface and the first gate electrode upper insulating layer side surface;
Forming a second gate sidewall on the second gate electrode side surface and the second gate electrode upper insulating layer side surface;
A method for manufacturing a semiconductor device, comprising: After forming a second gate sidewall on the second gate electrode side surface and the second gate electrode upper insulating layer side surface,
Forming a first electrode contact in contact with the first gate sidewall and connected to the first diffusion layer;
Forming a second electrode contact in contact with the second gate sidewall and connected to the second diffusion layer;
The method of manufacturing a semiconductor device according to claim 3 , wherein: The step of removing the remaining first resist and the first diffusion layer mask material by ashing removes the first diffusion layer mask material in the first region, and includes the first gate electrode and the first gate electrode. The method comprises forming a third diffusion layer in the semiconductor substrate using the gate electrode upper insulating film as a mask, and removing the remaining first resist and the first diffusion layer mask material. A method for manufacturing a semiconductor device according to claim 3 or 4 . After the step of removing the remaining second resist and the second diffusion layer mask material by ashing, the first gate electrode and the first gate electrode upper insulating film are used as a mask in the semiconductor substrate. 4. The method according to claim 3 , further comprising: forming a third diffusion layer, and forming a fourth diffusion layer in the semiconductor substrate using the second gate electrode and the second gate electrode upper insulating film as a mask. A method for manufacturing a semiconductor device according to claim 4 . The method further comprises a step of heating and activating impurities in the first diffusion layer and the second diffusion layer in the semiconductor substrate after the step of removing the remaining second diffusion layer mask material. method for producing any one of a semiconductor device according to claim 3 to 6.

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