KR20020056275A - 반도체 소자 - Google Patents
반도체 소자 Download PDFInfo
- Publication number
- KR20020056275A KR20020056275A KR1020000085598A KR20000085598A KR20020056275A KR 20020056275 A KR20020056275 A KR 20020056275A KR 1020000085598 A KR1020000085598 A KR 1020000085598A KR 20000085598 A KR20000085598 A KR 20000085598A KR 20020056275 A KR20020056275 A KR 20020056275A
- Authority
- KR
- South Korea
- Prior art keywords
- type
- drift region
- high concentration
- type drift
- low voltage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (3)
- 고전압 소자와 저전압 소자가 동일 기판에 형성되는 고전압용 IC에 있어서,상기 저전압 소자 영역에도 고농도 웰이 형성됨을 특징으로 하는 반도체 소자.
- 도전형 반도체 기판에 각각 형성되는 고전압 PMOS용 제 1 고농도 N형 웰, 고전압 NMOS용 고농도 P형 웰 및 저전압 소자용 제 2 고농도 N형 웰과,상기 제 1 고농도 N형 웰내에 일정 간격을 갖고 형성되는 2개의 제 1 P형 드리프트 영역, 상기 고농도 P형 웰내에 일정 간격을 갖고 형성되는 2개의 제 1 N형 드리프트 영역, 상기 제 2 고농도 N형 웰내에 형성되는 저전압 PMOS용 제 2 N형 드리프트 영역 및 저전압 NOMS용 제 2 P형 드리프트 영역과,상기 제 1 P형 드리프트 영역 사이, 제 1 N형 드리프트 영역 사이, 제 2 N형 드리프트 영역 및 제 2 P형 드리프트 영역의 중간 부분의 기판위에 각각 형성되는 전극들을 포함하여 구성됨을 특징으로 하는 반도체 소자.
- 제 2 항에 있어서,상기 각 고농도 웰 및 각 드리프트 영역에 콘택 저항을 감소시키기 위해 형성되는 고농도 불순물 영역들과, 상기 제 2 N형 드리프트 영역 및 제 2 P형 드리프트 영역의 게이트 전극 양측에 형성되는 소오스/드레인 불순물들을 더 포함함을 특징으로 하는 반도체 소자.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000085598A KR100652071B1 (ko) | 2000-12-29 | 2000-12-29 | 반도체 소자 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000085598A KR100652071B1 (ko) | 2000-12-29 | 2000-12-29 | 반도체 소자 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020056275A true KR20020056275A (ko) | 2002-07-10 |
KR100652071B1 KR100652071B1 (ko) | 2006-11-30 |
Family
ID=27688772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000085598A KR100652071B1 (ko) | 2000-12-29 | 2000-12-29 | 반도체 소자 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100652071B1 (ko) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101035596B1 (ko) * | 2007-12-28 | 2011-05-19 | 매그나칩 반도체 유한회사 | 딥 트렌치 구조를 갖는 반도체 소자 |
KR101140584B1 (ko) * | 2010-02-17 | 2012-05-02 | (주)피코셈 | 고전압 반도체 소자 제조방법 |
CN105576021A (zh) * | 2014-10-09 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Nldmos器件及其制造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100190020B1 (ko) * | 1996-02-21 | 1999-06-01 | 윤종용 | 고전압 트랜지스터 및 그의 제조방법 |
-
2000
- 2000-12-29 KR KR1020000085598A patent/KR100652071B1/ko active IP Right Grant
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101035596B1 (ko) * | 2007-12-28 | 2011-05-19 | 매그나칩 반도체 유한회사 | 딥 트렌치 구조를 갖는 반도체 소자 |
US8049283B2 (en) | 2007-12-28 | 2011-11-01 | Magnachip Semiconductor, Ltd. | Semiconductor device with deep trench structure |
KR101140584B1 (ko) * | 2010-02-17 | 2012-05-02 | (주)피코셈 | 고전압 반도체 소자 제조방법 |
CN105576021A (zh) * | 2014-10-09 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Nldmos器件及其制造方法 |
CN105576021B (zh) * | 2014-10-09 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | Nldmos器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100652071B1 (ko) | 2006-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2001352077A (ja) | Soi電界効果トランジスタ | |
KR20010033347A (ko) | 벌크 씨모스 구조와 양립 가능한 에스오아이 구조 | |
TW201724454A (zh) | 包括分接頭單元的電路 | |
KR100231717B1 (ko) | 반도체장치 및 그의 제조방법 | |
US4219828A (en) | Multidrain metal-oxide-semiconductor field-effect | |
JP2004071903A (ja) | 半導体装置 | |
CN108735727B (zh) | 晶体管版图结构、晶体管及制作方法 | |
JPH10107280A (ja) | 半導体集積回路装置およびその製造方法 | |
KR100652071B1 (ko) | 반도체 소자 | |
JPH0492475A (ja) | 相補型薄膜トランジスタ | |
TWI469260B (zh) | 混合電晶體式功率選通切換電路及方法 | |
JPS63244874A (ja) | 入力保護回路 | |
US6285227B1 (en) | Latch ratio circuit with plural channels | |
US6597043B1 (en) | Narrow high performance MOSFET device design | |
US6410966B2 (en) | Ratio circuit | |
JPS63158866A (ja) | 相補形半導体装置 | |
KR100866711B1 (ko) | 반도체소자의 인버터 형성방법 | |
KR100287892B1 (ko) | 반도체 메모리 소자 및 그 제조방법 | |
TWM628743U (zh) | 溝渠式功率半導體裝置 | |
JPH02201964A (ja) | Mos型トランジスタ | |
JPH11220124A (ja) | 半導体装置 | |
KR950003238B1 (ko) | 다중-전극을 이용한 논리소자의 구조 | |
JPH0222858A (ja) | 半導体装置 | |
KR100244287B1 (ko) | 씨모스펫 | |
KR20240073773A (ko) | 반도체 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121022 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20131017 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20141020 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20151019 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20161020 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20171020 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20181016 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20191016 Year of fee payment: 14 |