KR20020001877A - 어드레스 스크램블링을 갖는 메모리 어레이 - Google Patents
어드레스 스크램블링을 갖는 메모리 어레이 Download PDFInfo
- Publication number
- KR20020001877A KR20020001877A KR1020017014385A KR20017014385A KR20020001877A KR 20020001877 A KR20020001877 A KR 20020001877A KR 1020017014385 A KR1020017014385 A KR 1020017014385A KR 20017014385 A KR20017014385 A KR 20017014385A KR 20020001877 A KR20020001877 A KR 20020001877A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- scrambling
- address
- shell
- shells
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G07—CHECKING-DEVICES
- G07F—COIN-FREED OR LIKE APPARATUS
- G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
- G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
- G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
- G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
- G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
- G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
- G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
- G06Q20/357—Cards having a plurality of specified features
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Business, Economics & Management (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Security & Cryptography (AREA)
- General Business, Economics & Management (AREA)
- Strategic Management (AREA)
- Accounting & Taxation (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Engineering & Computer Science (AREA)
- Storage Device Security (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
Claims (7)
- 다수의 기억 셸(10) 및 어드레스 버스(20)를 통해 공급된 논리 어드레스(23)에 의해 기억 셸(10)을 선택하는 선택장치(14)를 갖추고 있으며, 상기 셸은 그후 물리적으로 액세스되어지고, 선택장치(14)는 스크램블링이 시작되어졌을 때 선택장치(14)에 전송된 논리 어드레스(23)에 비예측적인 유형으로 기억 셸(10)을 할당하는 스크램블링 장치(15)를 포함하고, 할당된 기억 셸(10)은 그다음 물리적으로 액세스되어지는 메모리 어레이에 있어서, 상기 스크램블링 장치(15)가 비예측적인 유형으로 기억 셸(10)에 대해 논리 어드레스의 할당을 수행하는 것을 특징으로 하는 어드레스 스크램블링을 갖는 메모리 어레이.
- 제1항에 있어서,상기 선택장치(14)는 스크램블링 장치(15)가 개시되는 제어입력(16)을 가지는 것을 특징으로 하는 어드레스 스크램블링을 갖는 메모리 어레이.
- 제1항에 있어서,상기 선택장치(14)가 프로그램을 형성하는 지시 시퀀스(29)의 실행중에 스크램블링 프로세스에 의해 수행된 할당을 유지시키는 것을 특징으로 하는 어드레스 스크램블링을 갖는 메모리 어레이.
- 제1항에 있어서,상기 스크램블링 장치(15)가 각 케이스마다의 출발신호(26)에 응하여 메모리(11)중에 있는 모든 셸(10)에 대해 논리 어드레스(13)의 할당을 수행하는 것을 특징으로 하는 어드레스 스크램블링을 갖는 메모리 어레이.
- 제1항에 있어서,상기 메모리(11)가 랜덤-액세스 메모리인 것을 특징으로 하는 어드레스 스크램블링을 갖는 메모리 어레이.
- 제1항에 있어서,상기 메모리(11)가 휘발성 메모리인 것을 특징으로 하는 어드레스 스크램블링을 갖는 메모리 어레이.
- 메모리(11)가 기억 셸(10)들로 분할되고 그리고 기억되는 데이타 각각은 데이타 컨텐츠 및 메모리(11)에 기억 셸(10)을 지정하는 논리 어드레스(23)를 포함하고, 스크램블링이 수행됨에 있어서는 기억 셸(10)의 어드레스(13)가 스크램블링에 의해 논리 어드레스(23)로부터 얻어지고 그리고 데이타 컨텐트는 스크램블링에 의해 발생된 어드레스(13)에서 메모리(11)에 기억되어지는, 메모리(11)에 데이타 컨텐츠를 기억시시키는 방법에 있어서, 상기 스크램블링이 정규적으로 또는 어떤 이벤트의 발생에 응하여 비예측적인 유형으로 수행되어지는 것을 특징으로 하는 메모리에 데이타 컨텐츠를 기억시키는 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19922155A DE19922155A1 (de) | 1999-05-12 | 1999-05-12 | Speicheranordnung mit Adreßverwürfelung |
DE19922155.3 | 1999-05-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020001877A true KR20020001877A (ko) | 2002-01-09 |
KR100648325B1 KR100648325B1 (ko) | 2006-11-23 |
Family
ID=7908004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020017014385A KR100648325B1 (ko) | 1999-05-12 | 2000-05-11 | 스크램블링장치를 갖춘 메모리 어레이 및 이에 대한 데이타 컨텐츠 기억방법 |
Country Status (10)
Country | Link |
---|---|
US (1) | US6572024B1 (ko) |
EP (1) | EP1183690B1 (ko) |
JP (1) | JP2003500786A (ko) |
KR (1) | KR100648325B1 (ko) |
CN (1) | CN1185658C (ko) |
AT (1) | ATE229219T1 (ko) |
AU (1) | AU4921100A (ko) |
DE (2) | DE19922155A1 (ko) |
ES (1) | ES2187475T3 (ko) |
WO (1) | WO2000070620A1 (ko) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100813627B1 (ko) * | 2007-01-04 | 2008-03-14 | 삼성전자주식회사 | 멀티-비트 데이터를 저장할 수 있는 플래시 메모리 장치를제어하는 메모리 제어기와 그것을 포함한 메모리 시스템 |
KR101430087B1 (ko) * | 2011-12-01 | 2014-08-13 | 후지쯔 가부시끼가이샤 | 메모리 모듈 및 반도체 기억 장치 |
US9064546B2 (en) | 2013-02-26 | 2015-06-23 | Samsung Electronics Co., Ltd. | Memory device selecting different column selection lines based on different offset values and memory system including the same |
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JP4683442B2 (ja) * | 2000-07-13 | 2011-05-18 | 富士通フロンテック株式会社 | 処理装置および集積回路 |
WO2002071231A1 (en) | 2001-02-15 | 2002-09-12 | Nokia Corporation | Method and arrangement for protecting information |
DE10127181A1 (de) * | 2001-06-05 | 2002-12-19 | Infineon Technologies Ag | Sicherheitsmodul, Verfahren zum Konfigurieren desselben und Verfahren und Vorrichtung zum Herstellen desselben |
DE10340405B3 (de) | 2003-09-02 | 2004-12-23 | Infineon Technologies Ag | Integrierter Halbleiterspeicher |
US20060161743A1 (en) * | 2005-01-18 | 2006-07-20 | Khaled Fekih-Romdhane | Intelligent memory array switching logic |
US20060171234A1 (en) * | 2005-01-18 | 2006-08-03 | Liu Skip S | DDR II DRAM data path |
US20060171233A1 (en) * | 2005-01-18 | 2006-08-03 | Khaled Fekih-Romdhane | Near pad ordering logic |
US20060245230A1 (en) * | 2005-04-29 | 2006-11-02 | Ambroggi Luca D | Memory module and method for operating a memory module |
JP4583305B2 (ja) * | 2005-12-28 | 2010-11-17 | シャープ株式会社 | 記録方法、記録装置及びicカード |
JP2008003976A (ja) * | 2006-06-26 | 2008-01-10 | Sony Corp | メモリアクセス制御装置および方法、並びに、通信装置 |
JP2008027327A (ja) * | 2006-07-25 | 2008-02-07 | Sony Corp | メモリアクセス制御装置および方法、並びに、通信装置 |
JP5571883B2 (ja) * | 2007-06-18 | 2014-08-13 | 軒▲ソン▼科技有限公司 | デジタル情報の保護方法、装置およびコンピュータによるアクセス可能な記録媒体 |
IL210169A0 (en) | 2010-12-22 | 2011-03-31 | Yehuda Binder | System and method for routing-based internet security |
JP5839659B2 (ja) * | 2011-06-20 | 2016-01-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9236143B2 (en) * | 2011-12-28 | 2016-01-12 | Intel Corporation | Generic address scrambler for memory circuit test engine |
JP5986279B2 (ja) * | 2015-08-28 | 2016-09-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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DE102018128980A1 (de) | 2018-11-19 | 2020-05-20 | Technische Universität München | Verfahren und vorrichtung zum betreiben einer speicheranordnung |
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-
1999
- 1999-05-12 DE DE19922155A patent/DE19922155A1/de not_active Ceased
-
2000
- 2000-05-11 AU AU49211/00A patent/AU4921100A/en not_active Abandoned
- 2000-05-11 US US09/959,895 patent/US6572024B1/en not_active Expired - Lifetime
- 2000-05-11 JP JP2000618984A patent/JP2003500786A/ja active Pending
- 2000-05-11 KR KR1020017014385A patent/KR100648325B1/ko active IP Right Grant
- 2000-05-11 ES ES00931196T patent/ES2187475T3/es not_active Expired - Lifetime
- 2000-05-11 DE DE50000882T patent/DE50000882D1/de not_active Expired - Lifetime
- 2000-05-11 CN CNB008089507A patent/CN1185658C/zh not_active Expired - Fee Related
- 2000-05-11 AT AT00931196T patent/ATE229219T1/de not_active IP Right Cessation
- 2000-05-11 WO PCT/EP2000/004285 patent/WO2000070620A1/de active IP Right Grant
- 2000-05-11 EP EP00931196A patent/EP1183690B1/de not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100813627B1 (ko) * | 2007-01-04 | 2008-03-14 | 삼성전자주식회사 | 멀티-비트 데이터를 저장할 수 있는 플래시 메모리 장치를제어하는 메모리 제어기와 그것을 포함한 메모리 시스템 |
KR101430087B1 (ko) * | 2011-12-01 | 2014-08-13 | 후지쯔 가부시끼가이샤 | 메모리 모듈 및 반도체 기억 장치 |
US8972822B2 (en) | 2011-12-01 | 2015-03-03 | Fujitsu Limited | Memory module and semiconductor storage device |
US9064546B2 (en) | 2013-02-26 | 2015-06-23 | Samsung Electronics Co., Ltd. | Memory device selecting different column selection lines based on different offset values and memory system including the same |
Also Published As
Publication number | Publication date |
---|---|
AU4921100A (en) | 2000-12-05 |
ES2187475T3 (es) | 2003-06-16 |
DE50000882D1 (de) | 2003-01-16 |
EP1183690A1 (de) | 2002-03-06 |
DE19922155A1 (de) | 2000-11-23 |
CN1185658C (zh) | 2005-01-19 |
US6572024B1 (en) | 2003-06-03 |
EP1183690B1 (de) | 2002-12-04 |
WO2000070620A1 (de) | 2000-11-23 |
KR100648325B1 (ko) | 2006-11-23 |
CN1355922A (zh) | 2002-06-26 |
ATE229219T1 (de) | 2002-12-15 |
JP2003500786A (ja) | 2003-01-07 |
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