KR200155176Y1 - A semiconductor package - Google Patents
A semiconductor package Download PDFInfo
- Publication number
- KR200155176Y1 KR200155176Y1 KR2019960031826U KR19960031826U KR200155176Y1 KR 200155176 Y1 KR200155176 Y1 KR 200155176Y1 KR 2019960031826 U KR2019960031826 U KR 2019960031826U KR 19960031826 U KR19960031826 U KR 19960031826U KR 200155176 Y1 KR200155176 Y1 KR 200155176Y1
- Authority
- KR
- South Korea
- Prior art keywords
- lead frame
- semiconductor package
- semiconductor chip
- frame pad
- double
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
본 고안은 리드프레임패드에 안착되는 반도체 칩를 포함하여 이루어지는 반도체 패키지에 있어서, 접착력이 있는 부분와 접착력이 없는 부분로 이루어지며, 접착력이 있는 부분에 의해 반도체칩이 리드프레임패드의 상면에 접착되어 고정되는 양면접착테이프를 포함하여 이루어지는 반도체 패키지에 관한 것이다.The present invention is a semiconductor package comprising a semiconductor chip that is seated on the lead frame pad, consisting of a portion having an adhesive force and a non-adhesive force, the semiconductor chip is bonded and fixed to the upper surface of the lead frame pad by the adhesive portion A semiconductor package comprising a double-sided adhesive tape.
Description
제1도는 종래의 반도체 패키지를 설명하기 위한 도면이고,1 is a view for explaining a conventional semiconductor package,
제2도는 본 고안의 반도체 패키지를 설명하기 위한 도면이다.2 is a view for explaining a semiconductor package of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 에폭시 A : 양면접착테이프10: epoxy A: double sided adhesive tape
20 : 양면에 접착력이 있는 부분 20-1. 20-2 : 양면에 접착력이 없는 부분20: Part with adhesive force on both sides 20-1. 20-2: part without adhesive on both sides
11,21 : 리드프레임패드 12,22 : 이너리드11,21: Lead frame pad 12,22: Inner lead
13,23 : 반도체 칩13,23: semiconductor chip
본 고안은 반도체 패키지(package)에 관한 것으로, 특히, 반도체 칩을 리드프레임패드(leadframe pad) 상면에 다이본딩(die bonding)을 실시하는 공정에서 리드프레임 패드 상면과 반도체 칩 저면을 경제적이고 실용적으로 고정시킬 수 있는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package. In particular, in the process of die bonding a semiconductor chip to a leadframe pad, the upper surface of the leadframe pad and the bottom of the semiconductor chip may be economically and practically used. A semiconductor package can be fixed.
제1도는 종래의 반도체 패키지를 설명하기 위한 도면으로, 제1도의 (a)는 종래기술에 따른 리드프레임의 평면도이고, 제1도의 (b)는 제1도의 (a)의 I-I' 선의 단면도이다.FIG. 1 is a diagram for explaining a conventional semiconductor package. FIG. 1A is a plan view of a lead frame according to the prior art, and FIG. 1B is a cross-sectional view taken along the line II 'of FIG. 1A. .
첨부된 도면을 참고로 하여 종래의 반도체 패키지를 설명하면 다음과 같다.A semiconductor package according to the related art will now be described with reference to the accompanying drawings.
종래에는 반도체 패키지를 제조하기 위한 다이본딩공정에서 리드프레임패드(11)상면에 반도체 칩(13)을 고정하여 안착시키기 위하여 사용되는 물질로는 제1도의(a),(b)와 같이, 에폭시(epoxy)(10)가 사용되었다.Conventionally, as a material used to fix and seat the semiconductor chip 13 on the lead frame pad 11 in a die bonding process for manufacturing a semiconductor package, as shown in (a) and (b) of FIG. (epoxy) (10) was used.
즉, 리드프레임패드(11) 상면에 고정되는 반도체 칩(13)이 외부리드가 돌출되도록 몰딩되어 형성되는 반도체 패키지에 있어서, 종래에는 리드프레임패드(11)상면과 반도체 칩(13)의 저면 사이에 접착물질로써 에폭시(10)를 사용하여 리드프레임패드(11) 상면에 반도체 칩(13) 저면을 고정하였다.That is, in a semiconductor package in which a semiconductor chip 13 fixed to an upper surface of the lead frame pad 11 is molded so that external leads are protruded, conventionally, between the upper surface of the lead frame pad 11 and the bottom surface of the semiconductor chip 13. The bottom surface of the semiconductor chip 13 was fixed to the upper surface of the lead frame pad 11 using an epoxy 10 as an adhesive material.
그런 후, 반도체 칩(13)과 이너리드(12) 사이에 와이어본딩을 실시하였다.Then, wire bonding was performed between the semiconductor chip 13 and the inner lead 12.
그러나, 종래의 반도체 패키지에서 반도체 칩의 저면을 리드프레임패드의 상면에 고정시키면서 안착시키는 접착물질로 에폭시를 사용함에 따라, 에폭시의 베이크(bake)공정이 필수적으로 진행되어야 한다.However, in the conventional semiconductor package, as the epoxy is used as an adhesive material for fixing the bottom of the semiconductor chip to the top surface of the lead frame pad, the baking process of the epoxy must be performed.
따라서, 별도의 오븐이 필요하며, 이에 따라 공정이 까다롭고 또한 공정시간이 추가되는 문제점이 발생되며, 공정이 추가됨에 따라 비용 또한 증대된다.Therefore, a separate oven is required, and thus, a process is difficult and a problem of additional process time occurs, and as the process is added, the cost is also increased.
또한, 리드프레임패드 상면에 반도체 칩을 본딩할 시에, 미처 에폭시가 건조되지 않은 상태에서 반도체 칩을 안착시킬 경우 리드프레임패드와 반도체 칩 사이로 에폭시가 흘러나와 공정상에 에러(error)가 발생하기도 한다.In addition, when bonding the semiconductor chip to the upper surface of the lead frame pad, when the semiconductor chip is seated in the state where the epoxy is not dried, epoxy may flow between the lead frame pad and the semiconductor chip, resulting in an error in the process. do.
상기 문제점을 해결하고자 안출된 것으로, 본 고안의 목적은 다이본딩시 리드프레임 상면에 반도체 칩을 고정시키는 접착물질인 에폭시를 사용함으로써 발생되는 단점을 개선하여 공정시간 단축과 비용절감에 적합한 반도체 패키지를 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to improve the shortcomings caused by the use of epoxy, which is an adhesive material for fixing a semiconductor chip on the upper surface of the lead frame during die bonding to reduce the process time and reduce the cost Is to provide.
상기 목적을 달성하고자, 리드프레임패드 및 리드프레임패드에 안착되는 반도체 칩을 포함한 반도체 패키지에 있어서, 본 고안의 반도체 패키지는 상, 하면에 접착력이 있는 부분과 접착력이 없는 부분이 소정간격으로 패터닝되어져 있으며, 접착력이 있는 부분에 의해 반도체 칩을 리드프레임패드에 접착 및 고정시키는 양면접착테이프를 구비한 것이 특징이다.In order to achieve the above object, in a semiconductor package including a lead frame pad and a semiconductor chip seated on the lead frame pad, the semiconductor package of the present invention is patterned at a predetermined interval between the portion having the adhesive strength and the non-adhesive force on the upper and lower surfaces And a double-sided adhesive tape for adhering and fixing the semiconductor chip to the lead frame pad by an adhesive portion.
제2도는 본 고안의 반도체 패키지를 설명하기 위한 도면으로, 제2도의 (a)는 본 고안의 반도체 패키지에서 리드프레임의 상면에 반도체 칩을 고정시키는 수단으로 사용되는 양면접착테이프를 도시한 도면이고, 제2도의 (b)는 제1도의 (a)의 I-I'선의 단면도이다.2 is a view for explaining a semiconductor package of the present invention, Figure 2 (a) is a view showing a double-sided adhesive tape used as a means for fixing a semiconductor chip on the upper surface of the lead frame in the semiconductor package of the present invention (B) of FIG. 2 is sectional drawing of the II 'line | wire of (a) of FIG.
그리고, 제2도의 (c)∼(f)는 제2의 (a)의 I-I'선의 단면도로, 리드프레임패드 상면에 반도체 칩을 접착시키는 본 고안의 접착수단을 사용하는 과정을 보인 도면이다.(C) to (f) in FIG. 2 are cross-sectional views taken along the line II ′ of FIG. 2a, and show a process of using the adhesive means of the present invention to bond a semiconductor chip to the upper surface of the lead frame pad. to be.
이하, 첨부된 도면을 참고로 하여 본 고안의 반도체 패키지를 설명하면 다음과 같다.Hereinafter, a semiconductor package of the present invention will be described with reference to the accompanying drawings.
본 고안의 반도체 패키지는, 제2도의 (a),(b)와 같이, 리드프레임패드(21)와, 리드프레임패드에 안착되는 반도체 칩(23)과, 리드프레임패드(21)에 반도체 칩을 고정시키는 양면접착테이프(20)를 포함한다.In the semiconductor package of the present invention, as shown in FIGS. 2A and 2B, the lead frame pad 21, the semiconductor chip 23 seated on the lead frame pad, and the lead frame pad 21 are semiconductor chips. It includes a double-sided adhesive tape 20 for fixing the.
양면접착테이프(20)는 양면에 접착력이 있는 부분(20-2)과 양면에 접착력이 없는 부분(20-1)이 소정간격으로 반복적으로 페터닝되어져 있다. 양면접착테이프에 있어서, 양면에 접착력이 있는 부분(20-2)과 양면에 접착력이 없는 부분(20-1) 의 상, 하 양면에는 접착력이 없는 종이나 비닐류 등의 재질이 부착된다.In the double-sided adhesive tape 20, portions 20-2 having adhesive strength on both sides and portions 20-1 having no adhesive strength on both sides are repeatedly patterned at predetermined intervals. In the double-sided adhesive tape, materials such as paper or vinyl having no adhesive force are attached to the upper and lower surfaces of the portion 20-2 having the adhesive force on both sides and the portion 20-1 having the adhesive force on both sides.
여기에서 양면에 접착력이 있는 부분(20-2)은 리드프레임패드(21)와 대응된 부위에만 형성되며, 양면접착테이프는 상기에서 언급된 바와 같이, 양면에 접착력이 있는 부분과 양면에 접착력이 없는 부분이 반복적으르 형성된다. 즉, 양면접착테이프의 접착력이 있는 부분(20)과 다음의 접착력이 있는 부분의 간격은 리드프레임패드와 패드 사이의 간격과 일치한다.Here, the portion 20-2 having the adhesive force on both sides is formed only at the portion corresponding to the lead frame pad 21, and the double-sided adhesive tape has the adhesive force on both sides and the adhesive force on both sides, as mentioned above. Missing parts are formed repeatedly. That is, the distance between the adhesive portion 20 of the double-sided adhesive tape and the next adhesive portion coincides with the gap between the lead frame pad and the pad.
본 고안의 반도체 패키지에 있어서, 양면접착테이프를 사용하여 리드프레임패드 상면에 반도체 칩을 고정시키는 과정을 알아본다.In the semiconductor package of the present invention, a process of fixing a semiconductor chip to an upper surface of a lead frame pad by using a double-sided adhesive tape will be described.
제2도의 (c),(d)와 같이, 양면접착테이프(20)는 리드프레임패드(21)에 접착되는 부위에 해당되는 접착력이 없는 부분(20-1)을 제거하고, 리드프레임패드 상면에 접착력이 있는 부분(20)을 부착시킨다.As shown in (c) and (d) of FIG. 2, the double-sided adhesive tape 20 removes the non-adhesive portion 20-1 corresponding to the portion bonded to the lead frame pad 21, and the upper surface of the lead frame pad. Attach the adhesive 20 to the adhesive portion.
이 때, 접착력이 있는 부분(20)은 리드프레임패드(21)에 대응되는 부위에만 형성된다.At this time, the adhesive portion 20 is formed only in the portion corresponding to the lead frame pad 21.
그런 후, 제2도의 (e)와 같이, 양면접착테이프(20)의 상면에 있는 접착력이 없는 부분(20-2)을 양면에 접착력이 있는 부분(20)으로부터 제거하고 난후, 제2도의 (f)와 같이, 각각의 반도체 칩(23)을 픽업(pick up)하여 리드프레임패드(20)상면에 부착된 양면접착테이프의 접착력이 있는 부분(20)에 고정하여 안착시킨다.Then, as shown in (e) of FIG. 2, the non-adhesive portion 20-2 on the upper surface of the double-sided adhesive tape 20 is removed from the portion 20 having the adhesive force on both sides thereof, As in f), each semiconductor chip 23 is picked up and fixed to the adhesive portion 20 of the double-sided adhesive tape attached to the upper surface of the lead frame pad 20.
이러한 과정을 통하여 리드프레임패드(21) 상면에 반도체 칩(23)을 양면접착테이프(A)로서 고정시킨다. 본 고안의 반도체 패키지에서는 리드프레임패드와 반도체 칩 사이를 종래의 에폭시로 고정시키지 않고 양면접착테이프를 이용함에 따라, 원가를 절감할 수 있고, 에폭시틀 도포하는 데 걸리는 시간을 줄일 수 있다. 뿐만 아니라, 별도의 베이크공정이 필요하지 않아 오븐 등의 장치비를 절감할 수 있다.Through this process, the semiconductor chip 23 is fixed to the upper surface of the lead frame pad 21 as a double-sided adhesive tape (A). In the semiconductor package of the present invention, by using a double-sided adhesive tape without fixing the lead frame pad and the semiconductor chip with a conventional epoxy, the cost can be reduced and the time taken to apply the epoxy frame can be reduced. In addition, since a separate baking process is not required, an apparatus cost such as an oven can be reduced.
그리고, 리드프레임에 있어서, 리드프레임패드 위치에만 양면접착테이프의 접착력이 있는 부분이 부착되므로, 단시간에 여러 리드프레임패드에 반도체 칩을 부착시킬 수 있다.In the lead frame, since the adhesive portion of the double-sided adhesive tape is attached only to the lead frame pad position, the semiconductor chip can be attached to various lead frame pads in a short time.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960031826U KR200155176Y1 (en) | 1996-09-30 | 1996-09-30 | A semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960031826U KR200155176Y1 (en) | 1996-09-30 | 1996-09-30 | A semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980018418U KR19980018418U (en) | 1998-07-06 |
| KR200155176Y1 true KR200155176Y1 (en) | 1999-08-16 |
Family
ID=19468329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019960031826U KR200155176Y1 (en) | 1996-09-30 | 1996-09-30 | A semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200155176Y1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100773699B1 (en) | 2005-08-03 | 2007-11-05 | 조창국 | Disposable thin memory chips. |
-
1996
- 1996-09-30 KR KR2019960031826U patent/KR200155176Y1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100773699B1 (en) | 2005-08-03 | 2007-11-05 | 조창국 | Disposable thin memory chips. |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980018418U (en) | 1998-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5723899A (en) | Semiconductor lead frame having connection bar and guide rings | |
| KR970067781A (en) | Semiconductor device, manufacturing method thereof, and collective semiconductor device | |
| KR890015399A (en) | Manufacturing Method of Semiconductor Device | |
| KR200155176Y1 (en) | A semiconductor package | |
| TW419756B (en) | Process for producing BGA type semiconductor device, TAB tape for BGA type semiconductor device, and BGA type semiconductor device | |
| KR100268756B1 (en) | A structure of seperat type diepad for leadframe | |
| JP2589520B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JP2788011B2 (en) | Semiconductor integrated circuit device | |
| JPS62195Y2 (en) | ||
| JPS63293963A (en) | Resin-sealed semiconductor device | |
| JPH0621303A (en) | Lead frame for semiconductor device and manufacture thereof | |
| JP2587533B2 (en) | Lead frame | |
| JPH02144946A (en) | Semiconductor device | |
| JPH1168016A (en) | Resin-sealed semiconductor device | |
| JPS63288029A (en) | Resin-sealed semiconductor device | |
| KR0135890Y1 (en) | Lead on chip package | |
| KR200159003Y1 (en) | Semiconductor package of thermal discharge type | |
| JPS6155770B2 (en) | ||
| JPH10107198A (en) | Ic sealing package | |
| JPH0543294B2 (en) | ||
| JPH03297163A (en) | Lead frame for semiconductor device | |
| JPH03259555A (en) | Lead frame | |
| JPS63117436A (en) | Film carrier | |
| JP3349465B2 (en) | Semiconductor device | |
| KR970003888A (en) | Semiconductor lead frame and packaging method of semiconductor device using same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20050422 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |