JPS63288029A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS63288029A JPS63288029A JP12477787A JP12477787A JPS63288029A JP S63288029 A JPS63288029 A JP S63288029A JP 12477787 A JP12477787 A JP 12477787A JP 12477787 A JP12477787 A JP 12477787A JP S63288029 A JPS63288029 A JP S63288029A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- lead frame
- bonding
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 8
- 239000004840 adhesive resin Substances 0.000 description 9
- 229920006223 adhesive resin Polymers 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置、特にリードフレームの
半導体素子搭載部の接着面の形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to the shape of the bonding surface of a semiconductor element mounting portion of a lead frame.
第３図（ａ＋は、従来の樹脂封止型半導体装置の製造工
程途中における、リードフレームの半導体素子搭載部近
傍の部分平面図、同図ｆｂｌは同図（ａ）のリードフレ
ームの半導体素子搭載部に半導体素子を固着した状態の
断面図である。第３図ｆａｔ 、 （ｂ）において、周
囲に多数のり−ド２が配置されたリードフレームの半導
体素子搭載部２１に半導体素子５が接着用樹脂６によシ
固着されている。Figure 3 (a+ is a partial plan view of the vicinity of the semiconductor element mounting part of the lead frame in the middle of the manufacturing process of a conventional resin-sealed semiconductor device, and figure fbl is a partial plan view of the semiconductor element mounting part of the lead frame in figure (a)) 3 is a cross-sectional view of a state in which a semiconductor element is fixed to a semiconductor element 5. In FIG. It is fixed with resin 6.
従来の樹脂封止型半導体装置におけるリードフレームの
半導体素子搭載部は、単なる平面形状であシ、接着用樹
脂で半導体素子を固着する場合次の様な欠点を有してい
た。The semiconductor element mounting portion of the lead frame in a conventional resin-sealed semiconductor device has a simple planar shape, and has the following drawbacks when the semiconductor element is fixed with an adhesive resin.
１）半導体素子接着面積が小さい。1) The semiconductor element adhesion area is small.
２） 半導体素子接着用樹脂の量が限定される。2) The amount of resin for bonding semiconductor elements is limited.
前記１，２の為に、半導体素子の接着強度は十分とはい
えず、その接着強度を増加する手段の一つとして、半導
体素子接着用樹脂の量を増加させると、半導体素子の側
面に迄接着用樹脂がはみ出し、新たに次の様な欠点が表
われる。Because of the above points 1 and 2, the adhesive strength of the semiconductor element is not sufficient, and one way to increase the adhesive strength is to increase the amount of the resin for adhering the semiconductor element. The adhesive resin protrudes and new defects appear as follows.
３）接着用樹脂から発生するガスにより半導体素子の表
面が汚染され、ワイヤボンディングの強度が不充分とな
る。3) The surface of the semiconductor element is contaminated by the gas generated from the adhesive resin, and the strength of wire bonding becomes insufficient.
４）更に半導体素子の平行度が悪くなシ、ワイヤポンデ
ィフグに支障をきたす。4) Furthermore, the parallelism of the semiconductor elements is poor, which causes problems in wire pumping.
５）半導体装置としての信頼性（特に耐湿性）を損なう
。5) Reliability (especially moisture resistance) as a semiconductor device is impaired.
本発明の樹脂封止型半導体装置は、半導体素子を接着す
る手段として、接着用樹脂を使用するとともに、半導体
素子搭載部の半導体素子固着面に複数の窪みを形成して
いる。The resin-sealed semiconductor device of the present invention uses an adhesive resin as a means for bonding the semiconductor element, and also forms a plurality of depressions on the semiconductor element fixing surface of the semiconductor element mounting portion.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第１図（ａ）は本発明の一実施例に係るリードフレーム
の半導体素子搭載部近傍の部分平面図、同図（ｂ）は同
図（ａ）のＡ−Ａ断面図、同図（Ｃ）は同図（ａ）のリ
ードフレームの半導体素子搭載部に半導体素子を固着し
た状態の断面図である。これらの図において、周囲に多
数のり一ド２が配置されたリードフレームの半導体素子
搭載部１の半導体素子固着面には、複数の円形の窪み３
，３．・・−・・・が形成されている。そして、渾み３
を有する固着面に、半導体素子５が接着用樹脂６により
固着されている。1(a) is a partial plan view of the vicinity of the semiconductor element mounting portion of a lead frame according to an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG. ) is a cross-sectional view of a state in which a semiconductor element is fixed to the semiconductor element mounting portion of the lead frame shown in FIG. 2(a). In these figures, a plurality of circular depressions 3 are formed on the semiconductor element fixing surface of the semiconductor element mounting portion 1 of the lead frame around which many glues 2 are arranged.
,3. ...-... is formed. And, play 3
A semiconductor element 5 is fixed to the fixing surface with an adhesive resin 6.
第２図（１）ａ本発明の他の実施例に係るリードフレー
ムの半導体素子搭載部の近傍を示す平面図、同図（ｂｌ
は同図（ａ）のＡ−Ａ断面図、同図（Ｃ）は同図（ａ）
のリードフレームの半導体素子搭載部に半導体素子を搭
載した状態を示す断面図で必る。これらの図において、
リードフレームの半導体素子搭載部１１の半導体素子固
着面には、複数の三角形の窪み４，４・・・が形成され
ている。そして、この窪み４を有する固着面に半導体素
子５が接着用樹脂６により接着固定されている。しかし
て、半導体素子接着後は、半導体素子５の電極パッドと
リードフレームの半導体素子固着部の周囲に配置された
多数のり−ド２との間を金楓細線で接続し、外装樹脂で
包むことＫより、樹脂封止型半導体装置が得られる。FIG. 2(1)a is a plan view showing the vicinity of the semiconductor element mounting portion of a lead frame according to another embodiment of the present invention;
is a sectional view taken along line A-A in the same figure (a), and the same figure (C) is a cross-sectional view of the same figure (a).
This is a cross-sectional view showing a state in which a semiconductor element is mounted on a semiconductor element mounting portion of a lead frame. In these figures,
A plurality of triangular depressions 4, 4, . . . are formed on the semiconductor element fixing surface of the semiconductor element mounting portion 11 of the lead frame. A semiconductor element 5 is adhesively fixed to the fixing surface having the recess 4 using an adhesive resin 6. After the semiconductor element is bonded, the electrode pads of the semiconductor element 5 and the multiple glue points 2 arranged around the semiconductor element fixing part of the lead frame are connected with thin gold maple wires, and then wrapped with an exterior resin. A resin-sealed semiconductor device can be obtained from K.
以上説明したように本発明は、リードフレームの半導体
素子搭載部の半導体素子接着面に複数の護みを設けるこ
とＫより、
１）半導体素子接着用樹脂の量を増やせ接着力が増加す
る。As explained above, in the present invention, by providing a plurality of protections on the semiconductor element adhesion surface of the semiconductor element mounting portion of the lead frame, 1) the amount of semiconductor element adhesion resin can be increased and the adhesive strength can be increased;
２）接着用樹脂の量を増加させても接着用樹脂が半導体
素子の側面にはみ出ない。2) Even if the amount of adhesive resin is increased, the adhesive resin does not protrude to the side surface of the semiconductor element.
３）半導体素子の平行度がよくなり、ワイヤボンディン
グ性が向上する。3) The parallelism of semiconductor elements is improved, and wire bonding properties are improved.
４）半導体装置の信頼性（特に耐湿性）を損なう事が減
少する。4) Deterioration of reliability (especially moisture resistance) of semiconductor devices is reduced.
などの効果が得られる。Effects such as this can be obtained.
第１図（ａ）は本発明の一実施例に係るリードフレーム
の部分平面図、同図（ｂ）は同図（ａ）のＡ −Ａ断面
図、同図（Ｃ）は同図（ａ）のリードフレームに半導体
素子を搭載した状態の断面図、第２図（ａ）は本発明の
他の実施例に係るリードフレームの部分平面図、同図（
ｂ）は同図（ａ）のＡ−Ａ断面図、同図（ｅ）は同図（
ａ）のリードフレームに半導体素子を搭載した状態の断
面図、第３図（ａ）は従来の樹脂封止型半導体装置にお
けるリードフレームの部分平面図、同図（ｂ）は同図（
ａ）のリードフレームに半導体素子を搭載した状態の断
面図である。
１．１１．２１・・・・・・リードフレームの半導体素
子搭載部、２・・・・・・リードフレームのリード部、
３・・・・・・円形の窪み、４・・・・・・三角形の窪
み、５・・・・・・半導体素子、６・・・・・・接着用
樹脂。FIG. 1(a) is a partial plan view of a lead frame according to an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG. 2(a) is a sectional view of a semiconductor element mounted on the lead frame of FIG. 2(a), and FIG.
b) is a sectional view taken along line A-A in figure (a), and figure (e) is a cross-sectional view taken along line A-A in figure (a).
3(a) is a cross-sectional view of a state in which a semiconductor element is mounted on a lead frame, FIG. 3(a) is a partial plan view of a lead frame in a conventional resin-sealed semiconductor device, and FIG.
FIG. 3 is a cross-sectional view of a state in which a semiconductor element is mounted on the lead frame of FIG. 1.11.21... Semiconductor element mounting part of lead frame, 2... Lead part of lead frame,
3...Circular depression, 4...Triangular depression, 5...Semiconductor element, 6...Adhesive resin.
Claims (1)
し樹脂封止した半導体装置において、前記リードフレー
ムの半導体素子固着面に複数の窪みが形成されているこ
とを特徴とする樹脂封止型半導体装置。1. A resin-sealed semiconductor device in which a semiconductor element is mounted on a semiconductor element mounting portion of a lead frame and sealed with a resin, wherein a plurality of depressions are formed in a semiconductor element fixing surface of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12477787A JPS63288029A (en) | 1987-05-20 | 1987-05-20 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12477787A JPS63288029A (en) | 1987-05-20 | 1987-05-20 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63288029A true JPS63288029A (en) | 1988-11-25 |
Family
ID=14893855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12477787A Pending JPS63288029A (en) | 1987-05-20 | 1987-05-20 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63288029A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369059A (en) * | 1989-12-08 | 1994-11-29 | Cray Research, Inc. | Method for constructing a reduced capacitance chip carrier |
| WO2012019867A1 (en) * | 2010-08-10 | 2012-02-16 | Osram Opto Semiconductors Gmbh | Chip carrier, electronic component having a chip carrier, and method for producing a chip carrier |
-
1987
- 1987-05-20 JP JP12477787A patent/JPS63288029A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369059A (en) * | 1989-12-08 | 1994-11-29 | Cray Research, Inc. | Method for constructing a reduced capacitance chip carrier |
| WO2012019867A1 (en) * | 2010-08-10 | 2012-02-16 | Osram Opto Semiconductors Gmbh | Chip carrier, electronic component having a chip carrier, and method for producing a chip carrier |
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