KR20010111659A - Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding structure between a semiconductor chip and a substrate, a semiconductor package using the same, and a method of manufacturing the semiconductor package. The present invention provides a semiconductor package in which at least one semiconductor chip is stacked in a vertical direction. The structure of the package may include: a substrate having a circuit pattern including a plurality of bond fingers formed on an upper surface of the resin layer, and a circuit pattern including a plurality of ball lands formed on a lower surface of the package; A first semiconductor chip bonded to the center of the upper surface of the substrate by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means, and having a plurality of input / output pads formed on an inner circumferential surface of the first semiconductor chip; The I / O pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and a loop height formed between the first semiconductor chip and the substrate is a first semiconductor chip. A plurality of conductive wires, such as the top height of the; A body formed by encapsulating the first semiconductor chip, the second semiconductor chip, and the conductive wire with an encapsulant; It characterized in that it comprises a conductive ball fused to each borland of the substrate.

Description

Wire bonding structure between semiconductor chip and substrate, and semiconductor package using the same, and method for manufacturing the semiconductor package using the same

The present invention relates to a semiconductor package, and in more detail, a wire bonding structure between a semiconductor chip and a substrate that can stack at least one semiconductor chip in a vertical direction, a semiconductor package using the same, and a method of manufacturing the semiconductor package. It is about.

In general, a multilayer semiconductor package includes a plurality of semiconductor chips vertically in a substrate such as a printed circuit board, a circuit tape, a circuit film, or a lead frame. After lamination, it refers to bonding the stacked semiconductor chips or the semiconductor chips and the substrate with electrical connection means such as conductive wires. Such stacked semiconductor packages have been recently manufactured in large quantities because they can realize high performance by mounting a plurality of semiconductor chips and can increase the mounting density of the motherboard.

Here, a wire bonding structure between a semiconductor chip and a substrate for stacking a conventional semiconductor chip is shown in FIGS. 1A and 1B.

As shown, the first semiconductor chip 10 is bonded to the center of the upper surface of the substrate 1 by the bonding means 50, and the other semiconductor bonding means 50 is attached to the upper surface of the first semiconductor chip 10. The second semiconductor chip 20 is bonded. Of course, another semiconductor chip may be bonded to the upper surface of the second semiconductor chip 20 by mutual bonding means.

Meanwhile, a plurality of input / output pads 10a and 20a are formed around upper surfaces of the first semiconductor chip 10 and the second semiconductor chip 20, which are formed by the conductive wires 30 of the substrate 1. It is bonded to a predetermined area.

Such a bonding structure is generally formed with a ball (not shown) at one end of the conductive wire 30, the ball is first bonded to the input / output pads 10a and 20a, and then the other end draws a predetermined path. The second bonding is performed in a predetermined region of the substrate 1.

In addition, the bonding method forms a wire loop height LH of a predetermined height, as shown, so that most of the second semiconductor chips do not interfere with the conductive wires 30 bonded to the first semiconductor chip 10. 20 is smaller in size than the first semiconductor chip 10. (See FIG. 1A.) The loop height of the conductive wires 30 is usually from the surface of the first semiconductor chip 10 or the second semiconductor chip 20. FIG. It is about 8 mils (1 mil = 1/1000 inch).

Also, in the case where the size of the first semiconductor chip and the second semiconductor chip is the same or the size of the second semiconductor chip is larger, the adhesive means for adhering the second semiconductor chip to the first semiconductor chip in consideration of the wire loop height. It is manufactured with a sufficiently large thickness. (See Fig. 1b.)

However, the loop height and thick bonding means of the conductive wire as described above has the disadvantage of increasing the thickness of the entire semiconductor package.

In addition, when the thickness of the bonding means is large, the elasticity of the bonding means also increases, so that the bonding state of the conductive wires performed on the input / output pads of the semiconductor chip is not good, and it is also difficult to bond the semiconductor chip to the correct position. .

A conventional stacked semiconductor package 100 'employing such a semiconductor chip and substraight wire bonding structure is shown in FIG. 1C.

As shown, first, a conductive circuit pattern including a plurality of bond fingers 3 is formed on the upper surface of the hard resin layer 2, and a lower surface of the ball land 4 is formed. A circuit pattern is formed, and the upper and lower circuit patterns are provided with a substrate 1 interconnected by conductive via holes 5. In this case, the conductive circuit pattern including the bond finger 3 and the borland 4 is a conventional copper trace.

The first semiconductor chip 10 is bonded to the central portion of the upper surface of the substrate 1 by the bonding means 50, and the second semiconductor is bonded to the upper surface of the first semiconductor chip 10 by the bonding means 50. The chip 20 is bonded.

The input / output pads 10a and 20a of the first semiconductor chip 10 and the second semiconductor chip 20 are all connected to the bond fingers 3 of the substrate 1 by the conductive wires 30. A plurality of conductive balls 40 are fused to the ball lands 4 formed on the lower surface of the substrate 1. The conductive ball 40 is later fused to a predetermined pattern of the motherboard.

The first semiconductor chip 10, the second semiconductor chip 20, and the conductive wire 30 located on the upper surface of the substrate 1 may be epoxy molded to protect from external impact or contact. It is encapsulated with an encapsulant such as a compound or a glove top to form a predetermined body 60.

In the figure, reference numeral 6 denotes a cover coat coated on a surface thereof to protect the circuit pattern from the external environment.

In the semiconductor package 100 ′, the electrical signals of the first semiconductor chip 10 and the second semiconductor chip 20 are input / output pads 10a and 20a, the conductive wire 30, the bond finger 3, and the conductive via hole ( 5), exchanges electrical signals with the motherboard (not shown) through the ball 4 and the conductive ball (40).

However, such a conventional semiconductor package is a conventional wire bonding method (wire bonding method for performing first bonding to the input / output pad of the semiconductor chip and performing second bonding to the bond finger of the substrate). By using, there is a disadvantage in that the loop height (indicated by LH in FIG. 1A) formed by the conductive wire is formed higher than the upper surface of the semiconductor chip. That is, when the second semiconductor chip of the same size is stacked on the upper surface of the first semiconductor chip because the higher wire loop height is provided in the first bonding region, the lower surface of the conductive wire and the second semiconductor chip interfere with each other. Therefore, the size of the second semiconductor chip is mostly smaller than the size of the first semiconductor chip. In addition, in the case of stacking the same size and the same function of the semiconductor chip (Homogeneous semiconductor chip), for example, a plurality of memory semiconductor chip, a sufficiently thick adhesive means to prevent interference with the conductive wire by the loop height It is difficult to bond the semiconductor chip to the correct position as well as the wire bonding defects.

In addition, the thickness of the body formed of the encapsulant is also thick due to the wire loop height and the thick adhesive means, which causes the overall thickness of the semiconductor package to increase.

On the other hand, wire bonding may be easier when the size of the second semiconductor chip is larger than that of the first semiconductor chip due to the structure of the circuit pattern formed on the substrate. However, the conventional semiconductor package is very difficult to meet such a requirement, and thus, There is a problem that the degree of freedom in designing a circuit pattern formed on a straight line is greatly reduced.

This problem is not only a problem of a semiconductor package using a printed circuit board, a circuit tape, a circuit film, and a lead frame as the above-mentioned substrate. For example, a plurality of semiconductor chips in UT (Ultra Thin) semiconductor packages and multilayer substrates This problem is also caused by the stacked semiconductor package.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, a wire bonding structure between a semiconductor chip and a substrate that can be easily stacked semiconductor chips of the same size or the same function, and a semiconductor package using the same, and It is to provide a method for manufacturing the semiconductor package.

Another object of the present invention is to stack a semiconductor chip of a larger size than the semiconductor chip adhered to the substrates, thereby increasing the degree of freedom for the circuit pattern design of the substrate and the substrate The present invention provides a wire bonding structure, a semiconductor package using the same, and a method for manufacturing the semiconductor package.

Another object of the present invention is to minimize the wire loop height, to suppress the interference of the semiconductor chip stacked with the wire, as well as to reduce the overall thickness of the wire bonding structure between the semiconductor chip and the substrate And a semiconductor package using the same, and a method for manufacturing the semiconductor package.

1A and 1B are cross-sectional views illustrating a wire bonding structure between a conventional semiconductor chip and a substrate, and FIG. 1C is a cross-sectional view illustrating a stacked semiconductor package employing a wire bonding structure between a semiconductor chip and a substrate.

2A through 2E are cross-sectional views illustrating a wire bonding structure between a semiconductor chip and a substrate in accordance with the present invention.

3A and 3B are perspective views illustrating a wire bonding structure between a semiconductor chip and a substrate in accordance with the present invention.

4 is a cross-sectional view showing a semiconductor package according to the present invention.

5 is a cross-sectional view showing another semiconductor package according to the present invention.

6 is a cross-sectional view showing another semiconductor package according to the present invention.

7 is a cross-sectional view showing another semiconductor package according to the present invention.

Figure 8a is a cross-sectional view showing a conventional semiconductor package of Figure 8b is another semiconductor package of the present invention improved.

9A and 9B are cross-sectional views showing yet another semiconductor package according to the present invention.

10 is a cross-sectional view showing another semiconductor package according to the present invention.

-Description of the main symbols in the drawings-

101-106; Semiconductor package according to the present invention

One; Suprate 2; Resin layer

3; Bondfinger 4; Borland

5; Conductive via holes 6; Cover coat

7; Through hole 8; Stepped step

10; A first semiconductor chip 20; Second semiconductor chip

30 '; Third semiconductor chip 10a, 20a, 30a '; I / O pad

30; Conductive wire 31; Stud bump

40; Conductive ball 50; Adhesive means

60; Body 71; Chip board

72; lead

In order to achieve the above object, the wire bonding structure between the semiconductor chip and the substrate according to the present invention includes a substrate having a plurality of circuit patterns formed thereon and mounted on the motherboard; A first semiconductor chip bonded to the center of the upper surface of the substrate by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means and having a plurality of input / output pads formed on an inner circumference of the upper surface of the first semiconductor chip; I / O pads of the first semiconductor chip and the second semiconductor chip and bond fingers of the substrate are electrically connected to each other, and a loop height formed between the semiconductor chip and the substrate is a loop height of each semiconductor chip. Characterized by including a plurality of conductive wires, such as the top surface.

Here, the bonding means is electrically nonconductive.

In addition, the bonding means is preferably formed thicker than the thickness of the conductive wire so that the conductive wire bonded to the first semiconductor chip does not contact the lower surface of the second semiconductor chip.

At least one other semiconductor chip may be bonded to the upper portion of the second semiconductor chip by an adhesive means.

The first semiconductor chip may be the same as the second semiconductor chip, larger than the size of the second semiconductor chip, or smaller than the size of the second semiconductor chip.

A stud bump may be formed on an input / output pad of the first semiconductor chip or the second semiconductor chip, and an end portion of the conductive wire may be connected to the stud bump.

In addition, the input / output pads of the first semiconductor chip or the second semiconductor chip may be connected to the conductive wire by an edge or ribbon bonding method.

In addition, the input / output pads of the first semiconductor chip or the second semiconductor chip may be connected by a conductive wire and a tab bonding method.

At least one other semiconductor chip may be attached to an upper surface of the first semiconductor chip on the side of the second semiconductor chip.

At least one other semiconductor chip may be attached to the lower surface of the second semiconductor chip on the side of the first semiconductor chip.

In addition, in order to achieve the above object, the semiconductor package according to the present invention has a circuit pattern including a plurality of bond fingers on an upper surface of the resin layer, and a circuit pattern including a plurality of ball lands on a lower surface thereof. Wow; A first semiconductor chip bonded to the center of the upper surface of the substrate by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means, and having a plurality of input / output pads formed on an inner circumferential surface of the first semiconductor chip; The I / O pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and a loop height formed between the first semiconductor chip and the substrate is a first semiconductor chip. A plurality of conductive wires, such as the top height of the; A body formed by encapsulating the first semiconductor chip, the second semiconductor chip, and the conductive wire with an encapsulant; It characterized in that it comprises a conductive ball fused to each borland of the substrate.

In addition, in order to achieve the above object, the semiconductor package according to the present invention has a circuit pattern including a plurality of bond fingers on the upper surface of the outer circumference of the through hole centering on a resin layer having a predetermined size through hole formed in the center. Substrate is formed with a circuit pattern including a plurality of ball land; A first semiconductor chip positioned in the through hole of the substrate and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means, and having a plurality of input / output pads formed on an inner circumferential surface of the first semiconductor chip; The input / output pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and a loop height formed between the second semiconductor chip and the substrate is a second semiconductor chip. A plurality of conductive wires such as the top height of the wires; A body formed by encapsulating the through-hole, the first semiconductor chip, the second semiconductor chip, and the conductive wire of the substrate with an encapsulant; It characterized in that it comprises a conductive ball fused to each borland of the substrate.

In addition, in order to achieve the above object, the semiconductor package according to the present invention is provided with a substantially flat resin layer, and in the center of the upper surface of the resin layer, stepped steps are formed to face each other to form a predetermined opening. A ground layer is bonded, a circuit pattern including a bond finger is formed on an upper surface of the multilayer resin layer, and a circuit pattern including a ball land is formed on a lower surface of the flat resin layer; A first semiconductor chip attached to an upper surface of the flat resin layer inside the opening by an adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means, and having a plurality of input / output pads formed on an inner circumferential surface of the first semiconductor chip; The I / O pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and the loop height formed between the first semiconductor chip and the second semiconductor chip and the substrate is each of the semiconductor chips. Conductive wires such as the height of the upper surface thereof; A body formed by sealing the opening of the substrate, the first semiconductor chip, the second semiconductor chip, and the conductive wire with an encapsulant; It characterized in that it comprises a conductive ball fused to each borland of the substrate.

In addition, in order to achieve the above object, the semiconductor package according to the present invention comprises a first semiconductor chip having a plurality of input and output pads formed on the inner circumference of the upper surface; A second semiconductor chip adhered to an upper surface of the first semiconductor chip by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface of the first semiconductor chip; A chip mounting plate adhered to the bottom surface of the first semiconductor chip by an adhesive means; A plurality of leads formed spaced apart from the chip mounting plate by a predetermined distance; An electrically connected input / output pad and a lead of the first semiconductor chip and the second semiconductor chip, wherein a loop height formed between the first semiconductor chip and the lead includes a plurality of conductive wires such as an upper surface height of the first semiconductor chip; And a body formed by encapsulating a predetermined region of the first semiconductor chip, the second semiconductor chip, the chip mounting plate, the conductive wire, and the lead with an encapsulant.

The substrate may be one of a printed circuit board, a circuit tape, and a circuit film.

The adhesive means for bonding the first semiconductor chip and the second semiconductor chip to each other is preferably made of an electrically nonconductive material.

Preferably, the bonding means is formed to be thicker than at least the thickness of the conductive wires so that the conductive wires bonded to the first semiconductor chip do not come into contact with the bottom surface of the second semiconductor chip.

At least one other semiconductor chip (third semiconductor chip) may be attached to the upper portion of the second semiconductor chip by an adhesive means.

The first semiconductor chip may be the same size as the second semiconductor chip, the first semiconductor chip may be larger than the size of the second semiconductor chip, or the first semiconductor chip may be smaller than the size of the second semiconductor chip.

A stud bump may be formed on an input / output pad of the first semiconductor chip or the second semiconductor chip, and an end portion of the conductive wire may be connected to the stud bump.

The input / output pads of the first semiconductor chip or the second semiconductor chip may be connected to the conductive wires by a paper or ribbon bonding method.

The input / output pads of the first semiconductor chip or the second semiconductor chip may be connected to each other by a conductive wire and a tab bonding method.

The substrate has a bond finger on the upper surface of the resin layer and a ball land on the lower surface of the resin layer may be electrically connected to each other by conductive via holes.

At least one other semiconductor chip may be attached to an upper surface of the first semiconductor chip on the side of the second semiconductor chip.

In addition, at least one other semiconductor chip may be located on a lower surface of the second semiconductor chip on the side of the first semiconductor chip.

In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object comprises the steps of providing a substrate formed with a plurality of circuit patterns to be mounted on the motherboard; Bonding a first semiconductor chip having a plurality of input / output pads through an adhesive means on one surface of the substrate; Bonding a predetermined region of the input / output pad and the substrate of the first semiconductor chip with a conductive wire, such that the loop height of the conductive wire is equal to or less than an upper surface of the first semiconductor chip; Bonding a second semiconductor chip to an upper surface of the first semiconductor chip through an adhesive means; Bonding a predetermined region of the input / output pad and the substrate of the second semiconductor chip with a conductive wire; And sealing the first semiconductor chip, the second semiconductor chip, and the conductive wire with an encapsulant.

Here, the loop height of the conductive wire bonding between the input / output pad and the substrate of the second semiconductor chip may be less than or equal to the height of the top surface of the second semiconductor chip.

In addition, at least one other semiconductor chip may be attached to an upper portion of the second semiconductor chip.

In addition, the first semiconductor chip may be formed the same as the second semiconductor chip, larger than the size of the second semiconductor chip, or smaller than the size of the second semiconductor chip.

In addition, a stud bump may be formed on an input / output pad of the first semiconductor chip or the second semiconductor chip, and an end portion of the conductive wire may be connected to the stud bump.

In addition, the input / output pads of the first semiconductor chip or the second semiconductor chip may be connected to the conductive wire by an edge or ribbon bonding method.

In addition, the input / output pads of the first semiconductor chip or the second semiconductor chip may be connected by a conductive wire and a tap bonding method.

At least one other semiconductor chip may be attached to an upper surface of the first semiconductor chip on the side of the second semiconductor chip.

At least one other semiconductor chip may be attached to the lower surface of the second semiconductor chip on the side of the first semiconductor chip.

As described above, the semiconductor package according to the present invention is formed so that the loop height of the conductive wires connected to the input / output pads of each semiconductor chip is formed so as not to exceed the height of the upper surface of the semiconductor chip. The semiconductor chips can be easily stacked. Therefore, despite the semiconductor package of the same size as the prior art, it is possible to implement a semiconductor package with improved functionality.

In addition, since the semiconductor chip having a larger size than that of the lower surface semiconductor chip can be stacked on the upper surface, the design freedom of the circuit pattern formed on the substrate is increased. Therefore, the most efficient circuit pattern can be designed.

In addition, by minimizing the loop height of the conductive wires to minimize the electrical resistance between the semiconductor chip and the substrate, it is possible to effectively suppress the interference between the stacked semiconductor chip and the conductive wires, the body formed by being sealed with an encapsulant By reducing the thickness of the semiconductor package it is possible to reduce the volume of the overall semiconductor package.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

2A through 2E are cross-sectional views illustrating a wire bonding structure between a semiconductor chip and a substrate according to the present invention, and FIGS. 3A and 3B are perspective views illustrating a wire bonding structure between a semiconductor chip and a substrate according to the present invention. to be.

First, a substrate (printed circuit board, circuit film, circuit tape or lead frame, etc.) to be mounted on the motherboard is provided, and the first semiconductor chip (A) is attached to the center of the upper surface of the substrate (1). 10) is glued. A plurality of input / output pads 10a are formed on the inner circumference of the upper surface of the first semiconductor chip 10.

The second semiconductor chip 20 is adhered to the top surface of the first semiconductor chip 10 by an adhesive means 50, and a plurality of input / output pads 10a are formed on the inner circumference of the top surface of the second semiconductor chip 20. Formed. The size of the first semiconductor chip 10 and the second semiconductor chip 20 may have the same size as shown, in addition to the various sizes of the first semiconductor chip 10 and the second semiconductor chip 20 It may be provided. That is, in FIG. 2A, the first semiconductor chip 10 and the second semiconductor chip 20 have the same size, but as shown in FIG. 2B, the first semiconductor chip 10 is larger than the second semiconductor chip 20. As shown in FIG. 2C, the size of the second semiconductor chip 20 may be larger than that of the first semiconductor chip 10.

In addition, although not shown, at least one or more other semiconductor chips may be further bonded to the upper surface of the second semiconductor chip 20, which is merely an optional item of a person skilled in the art.

Meanwhile, as shown in FIG. 2D, another second semiconductor chip 20 and a third semiconductor chip 30 ′ may be further adhered to the upper surface of the first semiconductor chip 10. In addition, as shown in FIG. 2E, the first semiconductor chip 10 and the second semiconductor chip 20 are bonded to the upper surface of the central portion of the substrate 1, and the first semiconductor chip 10 and the first semiconductor chip 10 are bonded to each other. Another third semiconductor chip 30 may be mounted on the top surface of the second semiconductor chip 20.

Subsequently, the adhesion means 50 for adhering the first semiconductor chip 10 to the substrate 1 and the adhesion means 50 for adhering the second semiconductor chip 20 to the upper surface of the first semiconductor chip 10. It is preferable to use all electrically nonconductive materials. In addition, the adhesive means 50 may be a liquid adhesive or a film adhesive, or a tape adhesive.

In addition, the thickness of the adhesive means 50 is preferably used that is thicker than the thickness of the conductive wire 30 to be described below. In addition, the adhesive means 50 for adhering the second semiconductor chip 20 to the upper surface of the first semiconductor chip 10 allows the input / output pad 10a of the first semiconductor chip 10 to be avoided and attached. This is preferred, but not necessarily.

The input / output pad 10a of the first semiconductor chip 10 and the input / output pad 20a of the second semiconductor chip 20 are connected to the conductive finger 30 by a bond finger 3 located on the upper surface of the substrate 1. Interconnected. The loop height LH of the conductive wire 30 connected to the input / output pads 10a and 20a of the first semiconductor chip 10 and the second semiconductor chip 20 is equal to the top height of each semiconductor chip. Are similar or identical. More specifically, it is preferable that the loop height of the conductive wire 30 is about 5 mils from the surfaces of the first semiconductor chip 10 and the second semiconductor chip 20.

As described above, the method of forming the loop height of the conductive wire 30 to be similar to or the same as the height of the upper surface of each semiconductor chip may include the input / output pads 10a and 20a of the first semiconductor chip 10 or the second semiconductor chip 20. A stud bump 31 may be first formed of aluminum (Al) or gold wire on the stud bump, and the end of the conductive wire 30 may be connected to the stud bump 31. 3A and 3B, that is, the first end of the conductive wire 30 is first bonded to the bond finger 3, and the other end thereof is the first semiconductor chip 10 or the second semiconductor chip 20. The method is used to connect to the stud bumps 31 formed on the input / output pads 10a and 20a of (Second Bonding). It forms a ball at one end of a conventional normal wire bonding (conductive wire 30), and then first bonds the ball to the input / output pads 10a and 20a of the semiconductor chip, and the other end is a bond finger (3). (Reverse Wire Bonding), one end of the conductive wire 30 is first bonded to the bond finger 3, and the other end is connected to the input / output pad of the semiconductor chip. Method of secondary bonding to 10a, 20a).

The reverse wire bonding uses a capillary used during thermosonic Au ball bonding (a method of bonding heat by bonding heat to an area to be bonded simultaneously with ultrasonic energy during bonding).

In addition, instead of the reverse wire bonding, an end of the conductive wire 30 is edged or ribboned on the input / output pads 10a and 20a of the first semiconductor chip 10 or the second semiconductor chip 20. ) There is also a method of bonding and connecting. The edge or ribbon bonding method is a conventional Ultrasonic Al Wedge Bonding (Ultrasonic Al Wedge Bonding, a method of bonding only the ultrasonic vibration energy to the external paper by the frictional heat, the first and second bonding areas are all formed in the edge shape Use the edge used for).

In addition, the conductive wire 30 is bonded to the input / output pads 10a and 20a of the first semiconductor chip 10 and the second semiconductor chip 20 by a tape autobonding (TAB) bonding method, and then looped. You can also adjust the height. The tab bonding method is a method in which a plurality of conductive wires 30, a pattern or a lead 72, and the like are simultaneously bonded while being enclosed with an integral film or tape, as is well known.

Therefore, according to the wire bonding structure of the semiconductor chip and the substrate according to the present invention, the loop height of the conductive wire 30 formed on the upper surface of the first semiconductor chip 10 is the same as the upper surface of the first semiconductor chip 10. Or by being formed in a similar position, the second semiconductor chip 20 of various sizes can be located on the upper surface of the first semiconductor chip 10. In addition, the roof height of the conductive wires 30 formed on the upper surface of the second semiconductor chip 20 is also formed at the same position as the upper surface of the second semiconductor chip 20, so that the semiconductor package using the wire bonding structure is used. Becomes smaller in thickness.

4 is a cross-sectional view showing a semiconductor package 101 according to the present invention.

First, a circuit pattern including a plurality of bond fingers 3 is formed on an upper surface of the resin layer 2, and a substrate 1 on which a circuit pattern including a plurality of ball lands 4 is formed. have.

The circuit pattern including the bond finger 3 on the upper surface of the resin layer 2 and the circuit pattern including the ball land 4 on the lower surface of the resin layer 2 are connected to each other by the conductive via hole 5.

In addition, the surface of the resin layer 2 and the circuit pattern is coated with a cover coat 6 which is an insulating polymer resin, but the bond finger 3 and the borland 4 are open to the outside of the resin layer 2. .

Here, the resin layer 2 may be a general thermosetting resin, a film, a tape, or the like, and thus, the substrate 1 may include a printed circuit board, a circuit film, a circuit tape, or the like. The figure shows a conventional printed circuit board as a substrate.

Subsequently, the first semiconductor chip 10 is bonded to the center of the upper surface of the substrate 1 by an adhesive means 50, and a plurality of input / output pads 10a are formed on the inner circumference of the upper surface of the first semiconductor chip 10. ) Is formed.

In addition, the second semiconductor chip 20 is adhered to the upper surface of the first semiconductor chip 10 by an adhesive means 50, and a plurality of input / output pads 10a are formed on the inner circumference of the upper surface of the second semiconductor chip 20. ) Is formed. The size of the first semiconductor chip 10 and the second semiconductor chip 20 may have the same size as shown, and as will be described later, the first semiconductor chip 10 and the second semiconductor chip in various sizes. 20 may be provided.

In addition, although not shown, at least one or more other semiconductor chips may be further bonded to the upper surface of the second semiconductor chip 20, which is merely an optional item of a person skilled in the art.

The input / output pad 10a of the first semiconductor chip 10 and the input / output pad 20a of the second semiconductor chip 20 are connected to the conductive finger 30 by a bond finger 3 located on the upper surface of the substrate 1. Interconnected. Loop heights (indicated by LH in FIG. 4) of the conductive wires 30 connected to the input / output pads 10a and 20a of the first semiconductor chip 10 and the second semiconductor chip 20 are respectively semiconductor. It is formed to be similar to or the same as the height of the top surface of the chip.

Subsequently, the first semiconductor chip 10, the second semiconductor chip 20, and the conductive wire 30 are encapsulated with an encapsulant such as an epoxy molding compound or a glop top, and the predetermined semiconductor chip 10. The body 60 is formed. Although the body 60 may form the same surface as the peripheral surface of the substrate 1 as shown in FIG. 4, the first semiconductor chip 10, the second semiconductor chip 20, and the conductive wire 30 are formed. It is also possible to encapsulate only a certain area of the upper surface of the substrate 1 by encapsulating the bay, and the encapsulation shape can be arbitrarily determined.

Of course, when the epoxy molding compound is used as the encapsulating material, an upper mold having a cavity having a predetermined shape, and a lower mold on which the substrate 1 is placed, are connected to the upper mold. By forming a gate, a sealing operation is performed by filling the encapsulant at high pressure through the gate.

In addition, when using a glove top as the encapsulant, an encapsulation operation is performed by placing a dispenser containing the glove top in the encapsulation region of the upper substrate 1 and spraying a predetermined amount of glove top.

Finally, conductive balls 40 such as solder balls are fused to each of the ball lands 4 formed on the lower surface of the substrate 1, which is later mounted on the pattern of the motherboard.

Therefore, in the semiconductor package 101 according to the present invention, the loop height of the conductive wire 30 formed on the upper surface of the first semiconductor chip 10 is formed at the same or similar position as the upper surface of the first semiconductor chip 10. In addition, the second semiconductor chip 20 having the same size as the first semiconductor chip 10 may be positioned on the upper surface of the first semiconductor chip 10. In addition, the roof height of the conductive wire 30 formed on the upper surface of the second semiconductor chip 20 is also formed at the same position as the upper surface of the second semiconductor chip 20, so that the body 60 is formed of an encapsulant. ), The thickness of the semiconductor package becomes smaller, and thus the overall thickness of the semiconductor package becomes smaller.

On the other hand, wherein the thickness of the bonding means 50 for adhering the second semiconductor chip 20 to the upper surface of the first semiconductor chip 10 is thicker than the thickness of the conductive wire 30 as described above. The lower surface of (20) is not in contact with the conductive wires.

FIG. 5 is a cross-sectional view showing another semiconductor package 102 according to the present invention, and FIG. 6 is another semiconductor package 103 according to the present invention. Since the semiconductor packages 102 and 103 illustrated in FIGS. 5 and 6 are very similar in structure to the semiconductor package of FIG. 4, only the differences will be described.

First, the semiconductor package 102 illustrated in FIG. 5 has a smaller size of the second semiconductor chip 20 than the size of the first semiconductor chip 10. It has a structure similar to that of the conventional semiconductor package 100 ', but the loop height of the conductive wires 30 formed on the upper surface of each semiconductor chip is formed to be equal to the height of the upper surface of the semiconductor chip. These loop heights are implemented using reverse wire bonding, foreign bond bonding, ribbon bonding or tap bonding methods as described above. In addition, since the loop height of the conductive wire 30 formed by being connected to the input / output pad 20a of the second semiconductor chip 20 is formed to be the same as or similar to the height of the top surface of the second semiconductor chip 20, the body 60 may be formed. The thickness of the semiconductor package can be minimized, and therefore, the thickness of the entire semiconductor package can be minimized.

Meanwhile, in the semiconductor package 103 shown in FIG. 6, the size of the second semiconductor chip 20 is larger than that of the first semiconductor chip 10. This structure was almost impossible with the conventional normal bonding method. However, the present invention can be implemented by using the above-described reverse wire bonding, foreign bond bonding, ribbon bonding, or tap bonding method. Therefore, the design of the circuit pattern formed on the substrate 1 can be optimized and efficiently designed according to the purpose of the first semiconductor chip 10 and the second semiconductor chip 20, and the conductive wire 30 By shortening the length of as much as possible to reduce the electrical resistance. In addition, there is an advantage that can also minimize the thickness of the body (60).

7 is a cross-sectional view showing another semiconductor package 104 according to the present invention.

First, a plurality of bond fingers 3 are formed on the upper surface of the outer circumference of the through hole 7 centering on the resin layer 2 in which the through hole 7 having a predetermined size (larger than the size of the semiconductor chip) is formed in the center. A circuit pattern is formed, and a circuit pattern including a plurality of ball lands 4 is formed on a lower surface, and the circuit patterns on the lower and upper surfaces of the resin layer 2 are connected to each other via conductive via holes 5. 1) is provided. The resin layer 2 and the circuit pattern of the substrate 1 are coated with a cover coat 6 whose surface is a polymer resin, and the bond finger 3 and the ball land 4 of the circuit pattern have a cover coat ( 6) It is open to the outside.

On the other hand, the first semiconductor chip 10 is positioned in the through hole 7 of the substrate 1, and a plurality of input / output pads 10a are formed on the inner circumference of the upper surface of the first semiconductor chip 10. have. In addition, the second semiconductor chip 20 is mounted on the top surface of the first semiconductor chip 10 with an electrically non-conductive adhesive means 50 interposed therebetween, and the inner peripheral edge of the top surface of the second semiconductor chip 20. Also, a plurality of input / output pads 20a are formed. In addition, another plurality of semiconductor chips may be further stacked on the upper surface of the second semiconductor chip 20.

The input / output pad 10a of the first semiconductor chip 10 and the input / output pad 20a of the second semiconductor chip 20 and the bond finger 3 of the substrate 1 are electrically connected to each other by a conductive wire 30. Is connected. Here, the bonding method of the conductive wires 30 to the input / output pads 10a and 20a of the first semiconductor chip 10 and the second semiconductor chip 20 may include reverse wire bonding, foreign paper bonding, ribbon bonding, and tab bonding. By using a method or the like, the loop height of each conductive wire 30 is formed smaller than before. Therefore, as illustrated in FIG. 6, a plurality of semiconductor chips may be stacked, and the thickness of the body 60 may be minimized.

Here, the thickness of the bonding means 50 for adhering the second semiconductor chip 20 to the upper surface of the first semiconductor chip 10 is greater than the thickness of the conductive wire 30, so that each conductive wire 30 is formed in the second conductive chip 30. It does not short with the upper surface of the semiconductor chip 20.

The through hole 7, the first semiconductor chip 10, the second semiconductor chip 20, and the conductive wire 30 of the substrate 1 are encapsulated with an encapsulant such as an epoxy molding compound or a glove top. The body 60 is formed. Here, the lower surface of the first semiconductor chip 10, the lower surface of the encapsulant and the lower surface of the substrate 1 form the same surface, so that the lower surface of the first semiconductor chip 10 is directly exposed to air. In addition, as shown in FIG. 6, the body 60 forms the same surface as the side of the substrate 1, but may also form the body 60 in various shapes.

Finally, the conductive balls 40 such as solder balls are fused to each ball land 4 of the substrate 1 so as to be mounted on a predetermined pattern of the motherboard later.

FIG. 8A is a cross-sectional view of a conventional semiconductor package 105 'and FIG. 8B is another semiconductor package 105 according to the improved invention.

First, referring to FIG. 8B, a substantially flat resin layer 2 is provided at the lowermost portion, and a stepped stepped step of lower narrowing light facing each other at the center of the upper surface of the resin layer 2 is provided. 8) are formed to bond the multilayered resin layers 2a, 2b, and 2c to form a predetermined opening, and a circuit pattern including bond fingers 3 is formed on the upper surface of the multilayered resin layers 2a, 2b, and 2c. The circuit pattern including the ball lands 4 is formed on the lower surface of the flat resin layer 2 to form the substrate 1 having a multilayer structure. Here, the circuit patterns of each of the resin layers 2, 2a, 2b, and 2c are connected to each other by the conductive via holes 5.

The first semiconductor chip 10 is adhered to the upper surface of the flat resin layer 2 inside the opening by the adhesive means 50, and a plurality of input / output pads 10a are formed on the inner circumference of the upper surface of the first semiconductor chip 10. ) Is formed. In addition, the second semiconductor chip 20 is adhered to the upper surface of the first semiconductor chip 10 by an adhesive means 50. Similarly, a plurality of input / output pads may be formed on the inner circumference of the upper surface of the second semiconductor chip 20. 20a) is formed. In addition, the third semiconductor chip 30 'is bonded to the upper surface of the second semiconductor chip 20 by an adhesive means 50, and a plurality of input / output pads are formed on the inner circumference of the upper surface of the third semiconductor chip 30'. 30a ') is formed.

The bond fingers 3 formed on the input / output pads 10a, 20a, 30a 'of the first, second, and third semiconductor chips 10, 20, and 30' and the resin layers 2, 2a, 2b, and 2c are conductive. Conductive wires 30 interconnected by wires 30 and formed between the first, second, and third semiconductor chips 10, 20, and 30 'and the resin layers 2, 2a, 2b, and 2c. The loop height of is formed equal to or similar to the height of the top surface of each semiconductor chip. These loop heights are those implemented by reverse wire bonding, foreign bond bonding, ribbon bonding or tap bonding methods as described above.

Subsequently, the opening of the substrate 1, the first semiconductor chip 10, the second semiconductor chip 20, and the conductive wire 30 are encapsulated with an encapsulant such as an epoxy molding compound or a glove top to form a predetermined body ( 60).

In addition, the conductive balls 40 are fused to the ball lands 4 formed on the bottom surface of the lowermost resin layer 2 of the substrate 1 so that they can be mounted on the motherboard.

Such a semiconductor package 105 has an advantage in that a larger semiconductor chip can be efficiently mounted than the semiconductor package 105 'shown in Fig. 8A. That is, since the wire loop height for each semiconductor chip is not higher than the top height of the semiconductor chip, a larger semiconductor chip can be mounted on the top surface of each semiconductor chip. In addition, since the length of the conductive wire 30 is shorter than that of the conventional semiconductor package, the electrical resistance value is also reduced. In addition, since the wire loop height is small, the thickness of the body 60 formed by being encapsulated with the encapsulant becomes small, and thus, the thickness of the overall semiconductor package is also reduced.

9A and 9B are cross-sectional views showing further semiconductor packages 106a and 106b according to the present invention.

As shown in FIG. 9A, another second semiconductor chip 20 and a third semiconductor chip 30 ′ may be further adhered to an upper surface of the first semiconductor chip 10. Therefore, the lower surface of the second semiconductor chip 20 and the third semiconductor chip 30 'form the same surface. In addition, the first semiconductor chip 10, the second semiconductor chip 20, and the third semiconductor chip 30 ′ have input / output pads 10 a, 20 a, and 30 a ′ formed on an inner circumference of an upper surface thereof. The combined size of the second semiconductor chip 20 and the third semiconductor chip 30 ′ may be the same as, larger than, or smaller than the first semiconductor chip 10. Therefore, semiconductor chips of various sizes can be mounted in various shapes according to the purpose of use.

In addition, as shown in FIG. 9B, the first semiconductor chip 10 and the second semiconductor chip 20 are bonded to the upper surface of the central portion of the substrate 1, and the first semiconductor chip 10 and the second semiconductor chip 20 are bonded to each other. Another third semiconductor chip 30 may be mounted on the upper surface of the semiconductor chip 20. Here, the lower surface of the first semiconductor chip 10 and the second semiconductor chip 20 forms the same surface. The third semiconductor chip 30 ′ may be the same size, larger, or smaller than the combined size of the first semiconductor chip 10 and the second semiconductor chip 20 so that the semiconductor chip may be mounted in various shapes.

As described above, a structure in which a plurality of semiconductor chips are located on the same plane may be implemented in all embodiments of the present invention, and the present invention is not limited to the above embodiments.

10 is a cross-sectional view showing another semiconductor package 107 according to the present invention, showing that the present invention is also implemented on a lead frame.

As shown, the chip mounting plate 71 is provided at the center, and the lead 72 is positioned to be spaced apart from the chip mounting plate 71 by a predetermined distance. The chip mounting plate 71 and the lead 72 and the like are all formed of copper or a copper alloy and the like and are referred to as lead frames.

The first semiconductor chip 10 is bonded to the upper surface of the chip mounting plate 71 by non-conductive bonding means 50, and a plurality of input / output pads 10a are formed on the inner circumference of the upper surface of the first semiconductor chip 10. ) Is formed. In addition, the second semiconductor chip 20 is also bonded to the upper surface of the first semiconductor chip 10 by non-conductive bonding means 50, and a plurality of inputs and outputs are formed on the inner circumference of the upper surface of the second semiconductor chip 20. The pad 20a is formed. In the drawing, the sizes of the first semiconductor chip 10 and the second semiconductor chip 20 are shown to be the same, but as described above, the first semiconductor chip 10 is larger than the size of the second semiconductor chip 20. Alternatively, the size of the second semiconductor chip 20 may be larger than that of the first semiconductor chip 10.

The input / output pad 10a of the first semiconductor chip 10 and the input / output pad 20a and the lead 72 of the second semiconductor chip 20 are connected to the conductive wires 30.

In this case, the loop height of the conductive wire 30 formed by being connected to the input / output pad 10a of the first semiconductor chip 10 may be the same as or similar to the height of the top surface of the first semiconductor chip 10, thereby forming an upper portion thereof. The lower surface of the second semiconductor chip 20 and the conductive wire 30 are not shorted to each other. These loop heights are those implemented by reverse wire bonding, foreign bond bonding, ribbon bonding or tap bonding methods as described above. In addition, the loop height of the conductive wire 30 formed on the input / output pad 20a of the second semiconductor chip 20 may also be formed to be the same as the top surface of the second semiconductor chip 20 by using the above method. In addition, as shown in the drawing, the loop height may be formed in a conventional manner by normal wire bonding.

Finally, the chip mounting plate 71, the first semiconductor chip 10, the second semiconductor chip 20, the conductive wire 30, and the lead 72 are encapsulated with an encapsulant to form a predetermined body 60. Doing.

On the other hand, the mounting on the motherboard is performed by the lead 72 exposed to the outside of the body 60 is fused with a solder or the like to a predetermined pattern of the motherboard.

Next, the manufacturing method of the semiconductor package by this invention is demonstrated.

1. Substrate providing step, provides various types and forms of substrate such as printed circuit board, circuit film, circuit tape or lead frame that can be mounted on the motherboard.

2. Bonding the first semiconductor chip, bonding the first semiconductor chip having a plurality of input / output pads formed on the upper surface of the substrate through non-conductive bonding means.

3. In the first wire bonding step, bonding an input / output pad of the first semiconductor chip and a predetermined region of the substrate (for example, a bond finger of a printed circuit board or an inner lead of a lead frame) with conductive wires, wherein the conductive wires are bonded. The loop height of the wire is set to be equal to or less than the height of the upper surface of the first semiconductor chip.

4. A second semiconductor chip bonding step, the second semiconductor chip is bonded to the upper surface of the first semiconductor chip through the non-conductive bonding means. Of course, a plurality of input / output pads are formed on the upper surface of the second semiconductor chip.

5. As the second wire bonding step, bonding the input / output pad and the substrate of the second semiconductor chip with conductive wires.

Here, the loop height of the conductive wire bonding between the input and output pads of the second semiconductor chip and the substrate may be less than or equal to the height of the upper surface of the second semiconductor chip.

In addition, after the stud bump is formed in advance on the input / output pad of the first semiconductor chip or the second semiconductor chip, a method of connecting the end of the conductive wire to the substrate and connecting the other end on the stud bump can be used. have.

The end of the conductive wire may be connected to the substrate, and the other end of the conductive wire may be connected to the input / output pad of the first semiconductor chip or the second semiconductor chip by edge or ribbon bonding.

In addition, the input / output pads of the first semiconductor chip or the second semiconductor chip may be connected by a conductive wire and a tab bonding method.

On the other hand, at least one other semiconductor chip may be bonded to the upper portion of the second semiconductor chip. The first semiconductor chip may be the same size as the second semiconductor chip, larger than the size of the second semiconductor chip, or smaller than the size of the second semiconductor chip.

Finally, at least one other semiconductor chip may be bonded to the upper surface of the first semiconductor chip on the side of the second semiconductor chip, and at least one other semiconductor chip may be attached to the upper surface of the first semiconductor chip. It may be bonded to the lower surface of the semiconductor chip.

6. In the encapsulation step, the first semiconductor chip, the second semiconductor chip, and the conductive wire are encapsulated with an encapsulant so as to be protected from the external environment.

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

As described above, the wire bonding structure between the semiconductor chip and the substrate according to the present invention, the semiconductor package using the same, and a method of manufacturing the semiconductor package include the looped heights of the conductive wires connected to the input / output pads of the semiconductor chips. Since it is formed so as not to exceed the height of the upper surface of the semiconductor chip, there is an effect that can easily stack a plurality of semiconductor chips having the same or different sizes. Therefore, in spite of being a semiconductor package of the same size as in the prior art, there is an effect of realizing a semiconductor package having an improved function.

In addition, by stacking a semiconductor chip having a larger size than that of the conventional semiconductor chip, the degree of freedom in designing the circuit pattern formed on the substrate is increased. Therefore, the most efficient circuit pattern can be designed.

In addition, by minimizing the loop height of the conductive wires to minimize the electrical resistance between the semiconductor chip and the substrate, it is possible to effectively suppress the interference between the stacked semiconductor chip and the conductive wires, the body formed by being sealed with an encapsulant By reducing the thickness of the semiconductor package there is an effect that can be reduced in volume.

Claims (32)

A plurality of circuit patterns formed on the motherboard to form a plurality of circuit patterns; A first semiconductor chip bonded to the center of the upper surface of the substrate by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means and having a plurality of input / output pads formed on an inner circumference of the upper surface of the first semiconductor chip; I / O pads of the first semiconductor chip and the second semiconductor chip and bond fingers of the substrate are electrically connected to each other, and a loop height formed between the semiconductor chip and the substrate is a loop height of each semiconductor chip. A wire bonding structure between a semiconductor chip and a substrate comprising a plurality of conductive wires corresponding to an upper surface height. 2. The wire bonding structure of claim 1, wherein said bonding means is electrically nonconductive. The semiconductor chip and the substrate according to claim 1, wherein the bonding means is formed to be thicker than at least the thickness of the conductive wires so that the conductive wires bonded to the first semiconductor chip do not contact the lower surface of the second semiconductor chip. Wire bonding structure. The wire bonding structure of claim 1, wherein the conductive wire has a loop height of about 5 mils from the surface of the semiconductor chip. The wire bonding structure between the semiconductor chip and the substrate according to claim 1, wherein the first semiconductor chip is smaller than the size of the second semiconductor chip. The wire bonding between the semiconductor chip and the substrate according to claim 1, wherein a stud bump is formed on an input / output pad of the first semiconductor chip or the second semiconductor chip, and an end portion of the conductive wire is connected to the stud bump. rescue. The wire bonding structure between the semiconductor chip and the substrate according to claim 1, wherein the input / output pads of the first semiconductor chip or the second semiconductor chip are connected by conductive wires by edge or ribbon bonding. 2. The wire bonding structure of claim 1, wherein the input / output pads of the first semiconductor chip or the second semiconductor chip are connected by conductive wires and a tap bonding method. A substrate having a plurality of bond fingers formed on a top surface of the resin layer, and a circuit pattern including a plurality of ball lands formed on a bottom surface thereof; A first semiconductor chip bonded to the center of the upper surface of the substrate by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means, and having a plurality of input / output pads formed on an inner circumferential surface of the first semiconductor chip; The I / O pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and a loop height formed between the first semiconductor chip and the substrate is a first semiconductor chip. A plurality of conductive wires, such as the top height of the; A body formed by encapsulating the first semiconductor chip, the second semiconductor chip, and the conductive wire with an encapsulant; A semiconductor package including conductive balls fused to each borland of the substrate. A substrate having a circuit pattern including a plurality of bond fingers formed on an upper surface of the outer circumference of the through hole, and a circuit pattern including a plurality of ball lands formed on a lower surface of the resin layer having a through hole having a predetermined size in the center; A first semiconductor chip positioned in the through hole of the substrate and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means and having a plurality of input / output pads formed on an inner circumference of the upper surface of the first semiconductor chip; The input / output pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and a loop height formed between the second semiconductor chip and the substrate is a second semiconductor chip. A plurality of conductive wires such as the top height of the wires; A body formed by encapsulating the through-hole, the first semiconductor chip, the second semiconductor chip, and the conductive wire of the substrate with an encapsulant; A semiconductor package including conductive balls fused to each borland of the substrate. A substantially flat resin layer is provided, and a multi-layered resin layer is bonded to form a predetermined opening by forming a stepped step of a lower narrow light facing each other at the center of the upper surface of the resin layer. A circuit pattern including a bond finger is formed on an upper surface of the multilayer resin layer, and a circuit pattern including a ball land is formed on a lower surface of the flat resin layer; A first semiconductor chip attached to an upper surface of the flat resin layer inside the opening by an adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface; A second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive means, and having a plurality of input / output pads formed on an inner circumferential surface of the first semiconductor chip; The I / O pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the substrate are electrically connected to each other, and a loop height formed between the first semiconductor chip and the second semiconductor chip and the substrate is each of the semiconductor chips. Conductive wires such as the height of the upper surface thereof; A body formed by sealing the opening of the substrate, the first semiconductor chip, the second semiconductor chip, and the conductive wire with an encapsulant; A semiconductor package including conductive balls fused to each borland of the substrate. A first semiconductor chip having a plurality of input / output pads formed on an inner circumferential surface of the upper surface; A second semiconductor chip adhered to an upper surface of the first semiconductor chip by adhesive means, and having a plurality of input / output pads formed on an inner circumference of the upper surface of the first semiconductor chip; A chip mounting plate adhered to the bottom surface of the first semiconductor chip by an adhesive means; A plurality of leads formed spaced apart from the chip mounting plate by a predetermined distance; An electrically connected input / output pad and a lead of the first semiconductor chip and the second semiconductor chip, wherein a loop height formed between the first semiconductor chip and the lead includes a plurality of conductive wires such as an upper surface height of the first semiconductor chip; And a body formed by encapsulating a predetermined region of the first semiconductor chip, the second semiconductor chip, the chip mounting plate, the conductive wire, and the lead with an encapsulant. The semiconductor package of claim 9, wherein the substrate is one of a printed circuit board, a circuit tape, and a circuit film. The semiconductor package according to any one of claims 9 to 12, wherein the bonding means for bonding the first semiconductor chip and the second semiconductor chip to each other is electrically nonconductive. The method according to any one of claims 9 to 12, wherein the bonding means is formed at least thicker than the thickness of the conductive wires so that the conductive wires bonded to the first semiconductor chip do not contact the lower surface of the second semiconductor chip. Semiconductor package. The semiconductor package according to any one of claims 9 to 12, wherein at least one other semiconductor chip is adhered to the upper portion of the second semiconductor chip by an adhesive means. The semiconductor package according to any one of claims 9 to 12, wherein the first semiconductor chip is the same size as the second semiconductor chip. The semiconductor package according to any one of claims 9 to 12, wherein the first semiconductor chip is larger than the size of the second semiconductor chip. 13. The semiconductor package according to any one of claims 9 to 12, wherein the first semiconductor chip is smaller than the size of the second semiconductor chip. The semiconductor according to any one of claims 9 to 12, wherein a stud bump is formed on an input / output pad of the first semiconductor chip or the second semiconductor chip, and an end portion of the conductive wire is connected to the stud bump. package. The semiconductor package according to any one of claims 9 to 12, wherein the input / output pads of the first semiconductor chip or the second semiconductor chip are connected by conductive wires by edge or ribbon bonding. The semiconductor package according to any one of claims 9 to 12, wherein the input / output pads of the first semiconductor chip or the second semiconductor chip are connected by a conductive wire and a tap bonding method. The semiconductor package according to any one of claims 9 to 12, wherein the substrates have a bond finger on the upper surface of the resin layer and a ball land on the lower surface of the resin layer being electrically connected to each other by conductive via holes. The semiconductor package according to any one of claims 9 to 12, wherein at least one other semiconductor chip is attached to an upper surface of the first semiconductor chip at a side of the second semiconductor chip. 13. The semiconductor package according to any one of claims 9 to 12, wherein at least one other semiconductor chip is located on the side of the first semiconductor chip at a lower surface of the second semiconductor chip. Providing a substrate having a plurality of circuit patterns formed thereon so as to be mounted on the motherboard; Bonding a first semiconductor chip having a plurality of input / output pads through an adhesive means on one surface of the substrate; Bonding a predetermined region of the input / output pad and the substrate of the first semiconductor chip with a conductive wire, such that the loop height of the conductive wire is equal to or less than an upper surface of the first semiconductor chip; Bonding a second semiconductor chip to an upper surface of the first semiconductor chip through an adhesive means; Bonding a predetermined region of the input / output pad and the substrate of the second semiconductor chip with a conductive wire; The method of manufacturing a semiconductor package comprising the step of encapsulating the first semiconductor chip, the second semiconductor chip, the conductive wire and the like. 27. The method of claim 26, wherein the loop height of the conductive wire bonding between the input and output pads of the second semiconductor chip and the substrate is less than or equal to the height of the top surface of the second semiconductor chip. 27. The method of claim 26, wherein at least one other semiconductor chip is attached to an upper portion of the second semiconductor chip. 27. The method of claim 26, wherein the first semiconductor chip is the same size as the second semiconductor chip. 27. The method of claim 26, wherein a stud bump is formed on an input / output pad of the first semiconductor chip or the second semiconductor chip, and an end portion of the conductive wire is connected to the stud bump. 27. The method of claim 26, wherein the input / output pads of the first semiconductor chip or the second semiconductor chip are connected to the conductive wires by edge or ribbon bonding. 27. The method of manufacturing a semiconductor package according to claim 26, wherein the input / output pads of the first semiconductor chip or the second semiconductor chip are connected by a conductive wire and a tap bonding method.