KR20010063199A - Method for forming bit line contact of semiconductor - Google Patents
Method for forming bit line contact of semiconductor Download PDFInfo
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- KR20010063199A KR20010063199A KR1019990060190A KR19990060190A KR20010063199A KR 20010063199 A KR20010063199 A KR 20010063199A KR 1019990060190 A KR1019990060190 A KR 1019990060190A KR 19990060190 A KR19990060190 A KR 19990060190A KR 20010063199 A KR20010063199 A KR 20010063199A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 36
- 150000002500 ions Chemical class 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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Abstract
Description
본 발명은 반도체 비트라인 콘택 형성방법에 관한 것으로, 특히 비트라인 콘택홀 형성을 셀(cell) 영역과 페리 및 코어(peri & core) 영역에서 동시에 진행할 수 있도록 한 반도체 비트라인 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor bit line contact, and more particularly, to a method for forming a semiconductor bit line contact in which bit line contact hole formation can be simultaneously performed in a cell region and a peri and core region. .
종래의 반도체 비트라인 콘택 형성방법을 첨부한 도1a 내지 도1d의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A detailed description will now be made with reference to the procedure cross-sectional view of FIGS. 1A to 1D attached to a conventional method for forming a semiconductor bit line contact.
먼저, 도1a에 도시한 바와같이 셀영역과 페리/코어영역이 구분된 반도체기판(1) 상에 격리영역(2)을 형성한다.First, as shown in FIG. 1A, an isolation region 2 is formed on a semiconductor substrate 1 in which a cell region and a ferry / core region are divided.
그리고, 도1b에 도시한 바와같이 상기 격리영역(2)이 형성된 반도체기판(1)의 상부전면에 순차적으로 게이트산화막(3), 게이트전극(4) 및 캡절연막(5)을 적층한 다음 셀영역과 페리/코어영역에 형성되는 소자의 특성을 고려하여 서로 이격되도록 패터닝하여 제1게이트를 형성한다.As shown in FIG. 1B, the gate oxide film 3, the gate electrode 4, and the cap insulation film 5 are sequentially stacked on the upper surface of the semiconductor substrate 1 on which the isolation region 2 is formed. The first gate is formed by patterning the device to be spaced apart from each other in consideration of characteristics of devices formed in the region and the ferry / core region.
그리고, 도1c에 도시한 바와같이 상기 결과물 상에 저농도 이온주입을 통해 저농도 소스/드레인(미도시)을 형성한 다음 상부전면에 절연막(6)을 증착하고, 선택적으로 식각하여 셀영역 게이트의 측벽을 형성한 다음 상부전면에 폴리실리콘(7)을 증착하고, 상기 제1게이트의 캡절연막(5)이 노출될때까지 평탄화한 다음 상부에 산화막(8)을 형성하고, 그 상부에 감광막 패턴(미도시)을 형성하여 선택적으로 산화막(8)을 식각한 다음 감광막 패턴을 제거하고, 상부전면에 산화막을 형성한 다음 선택적으로 식각하여 산화막(8)의 측벽(9)을 형성하고, 산화막(8) 및 그 측벽(9)을 하드 마스크(hard mask)로 적용하여 폴리실리콘(7)을 식각함으로써, 셀영역의 제1게이트간 이격영역을 채우는 폴리플러그를 형성한다.As shown in FIG. 1C, a low concentration source / drain (not shown) is formed on the resultant through low concentration ion implantation, and then an insulating layer 6 is deposited on the upper surface thereof, and selectively etched to form sidewalls of the cell region gate. And then polysilicon (7) is deposited on the upper surface, and planarized until the cap insulating film (5) of the first gate is exposed, and then an oxide film (8) is formed thereon, and a photoresist pattern (not shown) is formed thereon. And then selectively etch the oxide film 8, and then remove the photoresist pattern, form an oxide film on the upper surface, and then selectively etch to form the sidewall 9 of the oxide film 8, oxide film (8) The polysilicon 7 is etched by applying the sidewall 9 as a hard mask to form a polyplug filling the spaced apart region between the first gates of the cell region.
그리고, 도1d에 도시한 바와같이 상기 결과물의 주변영역 상에 절연막(10)을 증착하고, 선택적으로 식각하여 절연막(6)이 형성된 주변영역 게이트의 측벽을 형성한 다음 불순물이온을 주입하여 소스/드레인(미도시)을 형성하고, 상부전면에 층간절연막(11)을 증착한 다음 평탄화하고, 셀영역의 층간절연막(11) 및 그 하부의 산화막(8)을 식각하여 선택된 폴리플러그가 노출되도록 제1비트라인 콘택홀(12)을 형성한 다음 요구되는 배선에 따라 주변영역의 액티브영역 또는 게이트전극(4)이 노출되도록 층간절연막(11) 또는 층간절연막(11)과 캡절연막(5)을 식각하여 제2비트라인 콘택홀(13)을 형성한다.As shown in FIG. 1D, an insulating film 10 is deposited on the peripheral region of the resultant, and selectively etched to form sidewalls of the peripheral region gate on which the insulating film 6 is formed, and then implanting impurity ions A drain (not shown) is formed, the interlayer insulating film 11 is deposited on the entire upper surface, and then planarized. The interlayer insulating film 11 of the cell region and the oxide film 8 under the etching are etched to expose the selected polyplug. After the 1-bit line contact hole 12 is formed, the interlayer insulating film 11 or the interlayer insulating film 11 and the cap insulating film 5 are etched to expose the active region or the gate electrode 4 in the peripheral region according to the required wiring. The second bit line contact hole 13 is formed.
그러나, 상기한 바와같은 종래의 반도체 비트라인 콘택 형성방법은 셀영역과 페리/코어영역 상의 층간절연막 두께가 상이하여 비트라인 콘택홀 형성을 위한 식각공정을 분리시켜 진행함에 따라 공정이 복잡하고, 층간절연막 상에 2회의 감광막 도포, 노광 및 현상을 실시함에 따라 표면손상이나 이물질이 발생할 수 있는 문제점이 있었다.However, the conventional method of forming a semiconductor bit line contact as described above is complicated by the process of separating the etching process for forming the bit line contact hole because the thickness of the interlayer insulating film on the cell region and the ferry / core region is different. There was a problem that surface damage or foreign matter may occur by applying two times the photosensitive film coating, exposure and development on the insulating film.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 비트라인 콘택홀 형성을 셀 영역과 페리 및 코어 영역에서 동시에 진행할 수 있는 반도체 비트라인 콘택 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a method for forming a semiconductor bit line contact which can simultaneously form a bit line contact hole in a cell region, a ferry and a core region. have.
도1a 내지 도1d는 종래 반도체 비트라인 콘택 형성방법을 보인 수순단면도.1A to 1D are cross-sectional views showing a conventional method for forming a semiconductor bit line contact.
도2a 내지 도2d는 본 발명의 일 실시예를 보인 수순단면도.2A to 2D are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
101:엔형 불순물이온이 주입된 폴리실리콘101: Polysilicon implanted with N-type impurity ion
102:피형 불순물이온이 주입된 폴리실리콘102: polysilicon implanted with the skin impurity ion
103:국부적 엔형 불순물이온주입층103: local en-type impurity ion implantation layer
104:비트라인 콘택홀104: bit line contact hole
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체 비트라인 콘택 형성방법은 셀영역과 페리/코어영역이 구분된 반도체기판 상에 분리영역을 형성하고, 상면과 측면에 절연막이 형성된 게이트를 이격 패터닝하는 공정과; 상기 결과물의 상부에 엔형 불순물이온이 도핑된 폴리실리콘을 증착하고, 게이트 상면의 절연막이 노출될때까지 평탄화한 다음 상부전면에 피형 불순물이온이 도핑된 폴리실리콘과 산화막을 순차적으로 형성하는 공정과; 상기 산화막의 상부에 플러그용 감광막 패턴을 형성한 다음 산화막과 피형 불순물이온이 도핑된 폴리실리콘을 순차적으로 식각하고, 플러그용 감광막 패턴을 제거한 다음 잔류하는 산화막과 피형 불순물이온이 도핑된 폴리실리콘을 하드마스크로 적용하여 엔형 불순물이온이 도핑된 폴리실리콘을 식각함으로써, 폴리플러그를 형성하는 공정과; 상기 결과물의 상부전면에 층간절연막을 형성하고, 평탄화한 다음 층간절연막 상부에 셀영역은 선택된 폴리플러그가 노출되도록, 그리고 페리/코어영역은 요구되는 배선에 따라 액티브 또는 게이트전극이 노출되도록 비트라인 콘택용 감광막 패턴을 동시에 형성하고, 셀영역의 피형 불순물이온이 도핑된 폴리실리콘이 노출될때까지 셀영역과 페리/코어영역을 동시에 식각하는 공정과; 상기 노출된 피형 불순물이온이 도핑된 폴리실리콘 상에 고농도 엔형 불순물이온을 주입한 다음 계속해서 페리/코어영역의 액티브 또는 게이트전극이 노출될때까지 식각을 진행하는 공정을 구비하여 이루어지는 것을 특징으로 한다.The semiconductor bit line contact forming method for achieving the object of the present invention as described above is to form a separation region on the semiconductor substrate is divided cell region and ferry / core region, patterning the gate formed with an insulating film on the upper surface and side Process of doing; Depositing polysilicon doped with N-type impurity ions on the resultant, flattening until the insulating film on the upper surface of the gate is exposed, and then sequentially forming polysilicon and oxide film doped with the impurity ions on the upper surface; After the plug photoresist pattern is formed on the oxide layer, the oxide and the doped ion-doped polysilicon are sequentially etched, the plug photoresist pattern is removed, and the remaining oxide film and the doped impurity doped polysilicon are hardened. Forming a poly plug by etching the polysilicon doped with N-type impurity ions by applying as a mask; A bit line contact is formed to form an interlayer insulating film on the upper surface of the resultant, and planarize, so that the cell region is exposed to the selected polyplug on the interlayer insulating film, and the ferry / core area is exposed to the active or gate electrode according to the required wiring. Simultaneously forming a photoresist film pattern, and simultaneously etching the cell region and the ferry / core region until polysilicon doped with the dopant ions in the cell region is exposed; And implanting a high concentration of N-type impurity ions onto the exposed silicon-doped impurity ions and subsequently etching until the active or gate electrodes of the ferry / core region are exposed.
상기한 바와같은 본 발명에 의한 반도체 비트라인 콘택 형성방법을 첨부한 도2a 내지 도2d의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The cross-sectional view of FIG. 2A to FIG. 2D attached to the method for forming a semiconductor bit line contact according to the present invention as described above will be described in detail as an embodiment.
먼저, 도2a 및 도2b는 종래의 도1a 및 도1b와 동일하게 진행되며, 도면상의 부호만 '21'부터 정의하였으므로, 상세한 설명은 이를 참조하기로 한다.First, FIGS. 2A and 2B are performed in the same manner as in FIGS. 1A and 1B, and only reference numerals '21' are defined in the drawings.
그리고, 도2c에 도시한 바와같이 상기 도2b의 결과물 상에 저농도 이온주입을 통해 저농도 소스/드레인(미도시)을 형성한 다음 상부전면에 절연막(26)을 증착하고, 선택적으로 식각하여 셀영역 게이트의 측벽을 형성한 다음 상부전면에 엔형 불순물이온이 주입된 폴리실리콘(101)을 증착하고, 제1게이트의 캡절연막(25)이 노출될때까지 평탄화한 다음 상부에 피형 불순물이온이 주입된 폴리실리콘(102)과 산화막(28)을 형성하고, 그 상부에 감광막 패턴(미도시)을 형성하여 선택적으로 산화막(28)을 식각한 다음 감광막 패턴을 제거하고, 상부전면에 산화막을 형성한 다음 선택적으로 식각하여 산화막(28)의 측벽(29)을 형성하고, 산화막(28) 및 그 측벽(29)을 하드 마스크로 적용하여 피형 불순물이온 및 엔형 불순물이온이 주입된 폴리실리콘(101,102)을 식각함으로써, 셀영역의 제1게이트간 이격영역을 채우는 폴리플러그를 형성한다.As shown in FIG. 2C, a low concentration source / drain (not shown) is formed on the resultant of FIG. 2B through low ion implantation, and then an insulating layer 26 is deposited on the upper surface of the cell. After forming the sidewalls of the gate, polysilicon 101 in which N-type impurity ions are implanted is deposited on the upper surface, and planarized until the cap insulation layer 25 of the first gate is exposed, and then poly-implanted impurity ions are implanted therein. The silicon 102 and the oxide film 28 are formed, and a photoresist pattern (not shown) is formed thereon to selectively etch the oxide film 28, and then the photoresist pattern is removed, and an oxide film is formed on the upper surface. Etching to form sidewalls 29 of the oxide film 28, and by applying the oxide film 28 and the sidewalls 29 as a hard mask to etch the polysilicon (101,102) implanted with the impurity ions and en-type impurity ions A polyplug is formed to fill the spaced apart region between the first gates of the cell region.
그리고, 도2d에 도시한 바와같이 상기 결과물의 주변영역 상에 절연막(30)을 증착하고, 선택적으로 식각하여 절연막(26)이 형성된 주변영역 게이트의 측벽을 형성한 다음 불순물이온을 주입하여 소스/드레인(미도시)을 형성하고, 상부전면에 층간절연막(31)을 증착한 다음 평탄화하고, 층간절연막(31) 상부에 셀영역은 선택된 폴리플러그가 노출되도록, 그리고 페리/코어영역은 요구되는 배선에 따라 액티브 또는 게이트전극(24)이 노출되도록 비트라인 콘택용 감광막 패턴(미도시)을 동시에 형성하고, 셀영역의 피형 불순물이온이 도핑된 폴리실리콘(101)이 노출될때까지 셀영역과 페리/코어영역을 동시에 식각한 다음 노출된 피형 불순물이온이 도핑된 폴리실리콘(102) 상에 고농도 엔형 불순물이온을 주입하여 국부적 엔형 불순물이온 주입층(103)을 형성하고, 계속해서 페리/코어영역의 액티브 또는 게이트전극이 노출될때까지 식각을 진행하여 비트라인 콘택홀(104)을 형성한다.As shown in FIG. 2D, an insulating film 30 is deposited on the peripheral region of the resultant, and selectively etched to form sidewalls of the peripheral region gate on which the insulating layer 26 is formed, and then implanting impurity ions A drain (not shown) is formed, the interlayer insulating film 31 is deposited on the top surface, and then planarized, and the cell region is exposed on the interlayer insulating film 31 so that the selected polyplug is exposed, and the ferry / core area is required. The photoresist pattern (not shown) for the bit line contact is simultaneously formed to expose the active or gate electrode 24, and the cell region and the ferry / sill are exposed until the polysilicon 101 doped with the dopant ions in the cell region is exposed. Simultaneously etching the core region and then implanting a high concentration of en-type impurity ions on the exposed silicon-doped impurity ions 102 to form a localized en-type impurity ion injection layer Subsequently, etching is performed until the active or gate electrode of the ferry / core region is exposed to form the bit line contact hole 104.
따라서, 셀영역과 페리/코어영역의 비트라인 콘택홀 식각을 동시에 진행하여도 상기 피형 불순물이온이 주입된 폴리실리콘(102)이 식각차단막으로 작용하여 셀영역의 과도식각에 따른 게이트전극(24)과 후속 비트라인의 단락을 방지할 수 있으며, 이후에 폴리플러그와 접촉되는 피형 불순물이온이 주입된 폴리실리콘(102) 상에 고농도 엔형불순물이온을 주입하여 국부적 엔형 불순물이온주입층(103)을 형성함에 따라 엔형 불순물이온이 주입된 폴리실리콘(101)의 폴리플러그와 국부적 엔형 불순물이온주입층(103)은 전기적으로 도통하게 된다.Accordingly, even when the bit line contact hole etching of the cell region and the ferry / core region is simultaneously performed, the polysilicon 102 implanted with the implanted impurity ions acts as an etch barrier and thus the gate electrode 24 according to the transient etching of the cell region. Short-circuit and subsequent bit lines can be prevented, and then, a high concentration en-type impurity ion implantation layer 103 is formed on the polysilicon 102 into which the implanted impurity ion in contact with the polyplug is implanted. As a result, the poly plug of the polysilicon 101 into which the N-type impurity ions are implanted and the local N-type impurity ion implantation layer 103 are electrically conductive.
상기한 바와같은 본 발명에 의한 반도체 비트라인 콘택 형성방법은 비트라인 콘택홀 형성을 셀 영역과 페리 및 코어 영역에서 동시에 진행함에 따라 공정을 단순화시키고, 종래 층간절연막 상에 2회의 감광막 도포, 노광 및 현상을 실시함에 따른 표면손상이나 이물질 발생을 억제할 수 있는 효과가 있다.As described above, the method for forming a semiconductor bit line contact according to the present invention simplifies the process as the bit line contact hole is simultaneously formed in the cell region, the ferry and the core region, and the two photoresist films are applied, exposed and There is an effect that can suppress the surface damage or the generation of foreign matter by the development.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990060190A KR20010063199A (en) | 1999-12-22 | 1999-12-22 | Method for forming bit line contact of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990060190A KR20010063199A (en) | 1999-12-22 | 1999-12-22 | Method for forming bit line contact of semiconductor |
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| KR20010063199A true KR20010063199A (en) | 2001-07-09 |
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| KR (1) | KR20010063199A (en) |
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1999
- 1999-12-22 KR KR1019990060190A patent/KR20010063199A/en not_active Application Discontinuation
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